Adaptive noise cancellation using FPGA

By Jerin K Antony M3- AEI

INTRODUCTION
LMS-least mean square adaptation
FPGA implementation difficulties Structural modeling, hand shakes.

BLOCK DIAGRAM

Description
d ( n) s ( n) v 0 ( n)

+
f

x(n) v1 (n)

y(n) e(n)

Variables Used
mu- larning rate. noisy_signal- signal + noise. reference_noise- amplitude and phase shifted version of noise in noisy_signal. order- order of filter, number of weights. xin_vector- order number of delayed inputs of reference_noise.

Variables Used, cont..

wt_vector- order number of weights used for filtering. counter_noise- filter output. error- subtracting counter_noise from noisy_signal.

order=2; mu=0.005; xin_vector=zeros(1,order); wt_vector=zeros(1,order); error=zeros(1,n);

start: for k-th sample, do the following: xin_vector(0)=reference_noise(k); counter_noise(k)=xin_vector*wt_vector';

error(k)=noisy_signal(k)-counter_noise(k);

wt_vector = wt_vector + 2*mu*error(k) .*xin_vector;

xin_vector(2:order)=xin_vector(1:order-1); wait for next audio sample and go to start.

Top Module

Entity (top module)

Afi- noisy_signal. bfi- reference noise. Mu2- learning rate times two. Ndfi- new data hand shake from adc. Rfdfi- ready for data hand shake from fpga. Clk- clock. Result- out put. Rdyfi- output data ready hand shake from

Sub Modules

Floating Point Multiplie

Entity (float multiplier)

Floating Point Adder

Entity (float adder)

FPGA Utilization

References
[1] S. Haykin, Adaptive Filter Theory, Prentice Hall, Upper Saddle River, NJ, 2002. [2] Xilinx, Inc., The Programmable Logic Data Book 2000, Xilinx, Inc, CA: 2002. [3] Sudhakar Yalamanchili, Introductory VHDL, From Simulation to Synthesis, Prentice Hall, 2001.