8086 Lecture

Cs-2nd yr 2011-12 (additional)
Naveen Kr. Dubey (ECE DEPT ..RKGITW)
9/4/2012
The minimum mode is selected by making the MN/MX equal to 1. The maximum mode is selected by making the MN/MX equal to 0. Minimum mode 8086 system has one microprocessor.
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interrupts
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Interrupts in 8086
An 8086 Interrupt can come from any of three sources. - Hardware Interrupt External interrupt applied to nonmaskable interrupt NMI. External interrupt applied to maskable interrupt INTR. - Software Interrupt
Execution of INT instruction.
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INTR INTERRUPT REQUEST: is a level triggered input which is sampled during the last clock cycle of each instruction to determine if the processor should enter into an interrupt acknowledge Operation INTA Interrupt Acknowledge from the MP NMI NON-MASKABLE INTERRUPT: an edge triggered input which causes an interrupt request to the P
Naveen Kr. Dubey (ECE DEPT ..RKGITW) 9/4/2012 12
In the 8086 there are a total of 256 interrupts (or interrupt types) INT 00 INT 01 INT FF In 80x86, the memory location to which an interrupt goes is always four times the value of the interrupt number . INT 03h goes to 000Ch
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Interrupt Vector Table IVT
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The lowest five types are dedicated to specific interrupts. Interrupts 5 to 31 are reserved by INTEL for complex Processors Upper 224 interrupt types ( 32 to 255) available to use for hardware or software interrupts.
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Interrupt Type zero INT 0 Divide by zero interrupt. If the quotient is too large to fit into AL/AX Divide by zero interrupt invoked. Interrupt Type one INT 1 Single step Interrupt If trap flag is set 8086 will do a type 1 interrupt after every instruction execution.
Non Maskable Interrupt Type 2 When 8086 receives a low to high transition on its NMI input.
Type 2 interrupt response cannot be disabled ( masked) by any program instruction.

Could be used for handling critical situations like power failure detection.
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Break Point Interrupt Type 3

INT 3 instruction to implement breakpoint routines.
The system execute instruction up to break point and then goes to break point routine. Used for debugging. Overflow Interrupt Type 4
INTO: Interrupt on overflow instruction used for invoking an interrupt after overflow in an arithmetic operation. If no overflow it will be a NOP instruction.
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Interrupt Priority
HIGH
1. Divide error, INT nn, INTO

2. NMI 3. INTR 4. Single Step
LOW
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What if 8086 receives INTR while executing DIV which produces divide-by-zero error? 8086 executes INT 00 (as it has higher priority) This clears the IF and thus disables INTR Complete routine of INT 00 is executed and in the end IRET is executed This enables the INTR again Now INTR will be processed
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What if 8086 receives NMI while executing DIV which produces divide-by-zero error?
8086 executes INT 00 (as it has higher priority)

This clears the IF but does not disable NMI Branching to ISR0 and then again to ISR2 Return back to ISR0 and then to mainline program
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Operand types: REG: AX, BX, CX, DX, AH, AL, BL, BH, CH, CL, DH, DL, DI, SI, BP, SP. SREG: DS, ES, SS, and only as second operand: CS. memory: [BX], [BX+SI+7], variable, etc...(see Memory Access). immediate: 5, -24, 3Fh, 10001101b, etc...
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Notes: When two operands are required for an instruction they are separated by comma. For example: REG, memory When there are two operands, both operands must have the same size (except shift and rotate instructions). For example: AL, DL DX, AX m1 DB ? AL, m1 m2 DW ? AX, m2
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Some instructions allow several operand combinations. For example: memory, immediate REG, immediate memory, REG REG, SREG
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These marks are used to show the state of the flags: 1 - instruction sets this flag to 1. 0 - instruction sets this flag to 0. r - flag value depends on result of the instruction. ? - flag value is undefined (maybe 1 or 0).
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CLC Clear Carry Flag CLD Clear Destination Flag CLI Clear Interrupt Flag (this disables H/W interrupts ) CMC Compliment Carry Flag CMP - REG, memory
memory, REG REG, REG memory, immediate REG, immediate
result is not stored anywhere, flags are set (OF, SF, ZF, AF, PF, CF) according to result.
CMPSB (No operands)
Compare bytes: ES:[DI] from DS:[SI]. Algorithm: DS:[SI] - ES:[DI] set flags according to result: OF, SF, ZF, AF, PF, CF if DF = 0 then SI = SI + 1 DI = DI + 1 else SI = SI - 1 DI = DI - 1

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CMPSW
Compare words: ES:[DI] from DS:[SI]. Algorithm: DS:[SI] - ES:[DI] set flags according to result: OF, SF, ZF, AF, PF, CF if DF = 0 then SI = SI + 2 DI = DI + 2 else SI = SI - 2 DI = DI - 2

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CWD
Convert Word to Double word. Algorithm: if high bit of AX = 1 then: DX = 65535 (0FFFFh) else DX = 0 Example:

MOV DX, 0 ; DX = 0 MOV AX, 0 ; AX = 0 MOV AX, -5 ; DX AX = 00000h:0FFFBh CWD ; DX AX = 0FFFFh:0FFFBh RET
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DAA
DAS
Decimal adjust After Addition. Corrects the result of addition of two packed BCD Values Decimal adjust After Subtraction. Corrects the result of subtraction of two packed BCD values.
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DEC DIV (Reg ,Memory)
Decrement.
Unsigned divide. Algorithm: when operand is a byte: AL = AX / operand AH = remainder (modulus) when operand is a word: AX = (DX AX) / operand DX = remainder (modulus)
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IDIV
Signed divide. Algorithm: when operand is a byte: AL = AX / operand AH = remainder (modulus) when operand is a word: AX = (DX AX) / operand DX = remainder (modulus) Example:
MOV AX, -203 ; AX = 0FF35h MOV BL, 4 IDIV BL ; AL = -50 (0CEh), AH = -3 (0FDh)
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IMUL (REG Memory)
Signed multiply. Algorithm: when operand is a byte: AX = AL * operand. when operand is a word: (DX AX) = AX * operand. Example:
MOV AL, -2 MOV BL, -4 IMUL BL ; AX = 8 RET
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IN (AL, im.byte AL, DX AX, im.byte AX, DX) INC (reg, memory) INT (immidiate byte) INTO
Input from port into AL or AX. Second operand is a port number. If required to access port number over 255 DX register should be used Increment. Interrupt numbered by immediate byte (0..255).
Interrupt 4 if Overflow flag is 1. Algorithm: if OF = 1 then INT 4
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IRET
LAHF
Interrupt Return. Pop from stack: IP CS flags register Load AH from 8 low bits of Flags register. Algorithm: AH = flags register
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LDS
Load memory double word into word register and DS. Algorithm: REG = first word DS = second word
LES
Load memory double word into word register and ES. Algorithm: REG = first word ES = second word
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LODSB
LODSW
Load byte at DS:[SI] into AL. Update SI. Algorithm: AL = DS:[SI] if DF = 0 then SI = SI + 1 else SI = SI 1 Load word at DS:[SI] into AX. Update SI.
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LOOP
LOOPE
Decrease CX, jump to label if CX not zero
Decrease CX, jump to label if CX not zero and Equal (ZF = 1)
LOOPNE
LOOPNZ LOOPZ
Decrease CX, jump to label if CX not zero and Not Equal (ZF = 0). ZF=0 ,CF!=0

ZF=1 ,CF!=0
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Cs-2nd yr 2011-12 (additional)

Naveen Kr. Dubey (ECE DEPT ..RKGITW)

Naveen Kr. Dubey (ECE DEPT ..RKGITW)

Naveen Kr. Dubey (ECE DEPT ..RKGITW)

Naveen Kr. Dubey (ECE DEPT ..RKGITW)

Naveen Kr. Dubey (ECE DEPT ..RKGITW)

Naveen Kr. Dubey (ECE DEPT ..RKGITW)

Naveen Kr. Dubey (ECE DEPT ..RKGITW)

Naveen Kr. Dubey (ECE DEPT ..RKGITW)

Naveen Kr. Dubey (ECE DEPT ..RKGITW)

Naveen Kr. Dubey (ECE DEPT ..RKGITW)

Execution of INT instruction.

Naveen Kr. Dubey (ECE DEPT ..RKGITW)

Naveen Kr. Dubey (ECE DEPT ..RKGITW)

Interrupt Vector Table IVT

Naveen Kr. Dubey (ECE DEPT ..RKGITW)

Naveen Kr. Dubey (ECE DEPT ..RKGITW)

Type 2 interrupt response cannot be disabled ( masked) by any program instruction.

Naveen Kr. Dubey (ECE DEPT ..RKGITW)

Break Point Interrupt Type 3

Naveen Kr. Dubey (ECE DEPT ..RKGITW)

1. Divide error, INT nn, INTO

Naveen Kr. Dubey (ECE DEPT ..RKGITW)

Naveen Kr. Dubey (ECE DEPT ..RKGITW)

8086 executes INT 00 (as it has higher priority)

Naveen Kr. Dubey (ECE DEPT ..RKGITW)

Naveen Kr. Dubey (ECE DEPT ..RKGITW)

Naveen Kr. Dubey (ECE DEPT ..RKGITW)

Naveen Kr. Dubey (ECE DEPT ..RKGITW)

Naveen Kr. Dubey (ECE DEPT ..RKGITW)

Naveen Kr. Dubey (ECE DEPT ..RKGITW)

Naveen Kr. Dubey (ECE DEPT ..RKGITW)

Naveen Kr. Dubey (ECE DEPT ..RKGITW)

Naveen Kr. Dubey (ECE DEPT ..RKGITW)

Naveen Kr. Dubey (ECE DEPT ..RKGITW)

Naveen Kr. Dubey (ECE DEPT ..RKGITW)

Naveen Kr. Dubey (ECE DEPT ..RKGITW)

CMPSB (No operands)

Naveen Kr. Dubey (ECE DEPT ..RKGITW)

Naveen Kr. Dubey (ECE DEPT ..RKGITW)

Naveen Kr. Dubey (ECE DEPT ..RKGITW)

Naveen Kr. Dubey (ECE DEPT ..RKGITW)

DEC DIV (Reg ,Memory)

Naveen Kr. Dubey (ECE DEPT ..RKGITW)

Naveen Kr. Dubey (ECE DEPT ..RKGITW)

IMUL (REG Memory)

Naveen Kr. Dubey (ECE DEPT ..RKGITW)

Interrupt 4 if Overflow flag is 1. Algorithm: if OF = 1 then INT 4

Naveen Kr. Dubey (ECE DEPT ..RKGITW)

Naveen Kr. Dubey (ECE DEPT ..RKGITW)

Naveen Kr. Dubey (ECE DEPT ..RKGITW)

Naveen Kr. Dubey (ECE DEPT ..RKGITW)

Naveen Kr. Dubey (ECE DEPT ..RKGITW)

Decrease CX, jump to label if CX not zero

Decrease CX, jump to label if CX not zero and Equal (ZF = 1)

Naveen Kr. Dubey (ECE DEPT ..RKGITW)

Naveen Kr. Dubey (ECE DEPT ..RKGITW)

Naveen Kr. Dubey (ECE DEPT ..RKGITW)

Naveen Kr. Dubey (ECE DEPT ..RKGITW)

Naveen Kr. Dubey (ECE DEPT ..RKGITW)

Naveen Kr. Dubey (ECE DEPT ..RKGITW)

Naveen Kr. Dubey (ECE DEPT ..RKGITW)

Naveen Kr. Dubey (ECE DEPT ..RKGITW)

Naveen Kr. Dubey (ECE DEPT ..RKGITW)