Chapter-2 : Processors

Subject : EC 404 Embedded Systems

Preliminaries
Here we see some general concepts in computer architecture including the different styles of computer architecture the nature of assembly language

Computer Architecture Taxonomy

von Neumann machine: The memory holds both data and instructions, and can be read or written when given an address CPU has several internal registers that store values used internally. i.e. Program counter (PC)

Harvard architecture: It has separate memories for data and program The program counter points to program memory, not data memory As a result, it is harder to write self-modifying programs on Harvard machines

Advantages of Harvard Arch

separation of program and data memories provides

higher performance for digital signal processing Processing signals in real-time places great strains on the data access system in two ways: 1) large amounts of data flow through the CPU 2) that data must be processed at precise intervals Data sets that arrive continuously and periodically are called streaming data Having two memories with separate ports provides higher memory bandwidth; not making data and memory compete for the same port also makes it easier to move the data at the proper times

 DSPs constitute a large fraction of all

microprocessors sold today,and most of them are Harvard architectures. A single example shows the importance of DSP: Most of the telephone calls in the world go through at least two DSPs, one at each end of the phone call. Another axis along which we can organize computer architectures relates to their instructions and how they are executed

 complex instruction set computers (CISC)

machines provided a variety of instructions that may perform very complex tasks, such as string searching they also generally used a number of different instruction formats of varying lengths One of the advances in the development of highperformance microprocessors was the concept of reduced instruction set computers (RISC) These computers tended to provide somewhat fewer and simpler instructions so that they could be efficiently executed in pipelined processors

 Early RISC designs substantially outperformed

CISC designs of the period As it turns out, we can use RISC techniques to efficiently execute at least a common subset of CISC instruction sets, so the performance gap between RISC-like and CISC-like instruction sets has narrowed somewhat Beyond the basic RISC/CISC characterization, we can classify computers by several characteristics of their instruction sets instruction set of the computer defines the interface between software modules and the underlying hardware

 It is the key to analyzing the performance of

programs. By understanding the types of instructions that the CPU provides, we gain insight into alternative ways to implement a particular function Instructions can have a variety of characteristics: Fixed versus variable length Addressing modes Numbers of operands Types of operations supported
The set of registers available for use by programs is

called the programming model, also known as the programmer model

Assembly Language

An example of ARM assembly language

 It should be remembered that early assemblers

were written in assembly language to fit in a very small amount of memory. Those early restrictions have carried into modern assembly languages by tradition

Format of ARM data processing instructions

ADDGT r0,r3,#5

 Assemblers must also provide some pseudo-ops

to help programmers create complete assembly language programs An example of a pseudo-op is one that allows data values to be loaded into memory locations These allow constants,for example, to be set into memory BIGBLOCK %10

ARM Ltd
The ARM processor core originates within a British

computer company called Acorn. In the mid-1980s they were looking for replacement for the 6502 processor used in their BBC computer range Other companies became interested in this processor, including Apple who were looking for a processor for their PDA project. After much discussion this led to Acorns processor design team splitting off from Acorn at the end of 1990 to become Advanced RISC Machines Ltd, now just ARM Ltd. Thus ARM Ltd now designs the ARM family of RISC processor cores, together with a range of other supporting technologies. One important point about ARM is that it does not fabricate silicon itself, but instead just produces the design - we are an Intellectual Property (or IP) company. Instead silicon is produced by companies who license the ARM processor

 Founded in November 1990

Spun out of Acorn Computers

Designs the ARM range of RISC

processor cores Licenses ARM core designs to semiconductor partners who fabricate and sell to their customers.
ARM does not fabricate silicon itself

Also develop technologies to assist with

the design-in of the ARM architecture

Software tools, boards, debug hardware,

application software, bus architectures, peripherals etc

ARM Partnership Model

ARMs business model centres around the

principle of partnership. At the centre of this are ARMs semiconductor partners who design, manufacture and market ARM-compliant products. Having so many partner companies producing silicon executing the same instruction set is a very important part of ARMs strength in the market place. However each of our semiconductor partners bring their own unique strengths to the partnership - each having their own technologies, applications knowledge, product focus, culture, geography, and key customers.

ARM Powered Products

Intellectual Property

ARM provides hard and soft views to licencees

RTL and synthesis flows GDSII layout soft views include gate level netlists hard views are DSMs to protect ARM IP

Licencees have the right to use hard or soft views of the IP

OEMs must use hard views

ARM Partnership Model

ARMs business model centres around the

principle of partnership. At the centre of this are ARMs semiconductor partners who design, manufacture and market ARM-compliant products. Having so many partner companies producing silicon executing the same instruction set is a very important part of ARMs strength in the market place. However each of our semiconductor partners bring their own unique strengths to the partnership - each having their own technologies, applications knowledge, product focus, culture, geography, and key customers.

ARM Processor Family

ARM7TDMI

Strong ARM
ARM9 ARM9TDMI ARM9E ARM10E ARM11 Cortex XScale

Example

ARM processor

ARM Architecture

ARM Memory Organization

Different versions of the ARMarchitecture are

identified by different numbers ARM7 is a von Neumann architecture machine, while ARM9 uses a Harvard architecture this difference is invisible to the assembly language programmer, except for possible performance differences heARM architecture supports two basic types of data: The standardARM word is 32 bits long. The word may be divided into four 8-bit bytes.

 ARM7 allows addresses up to 32 bits long.An

address refers to a byte,not a word So, word 0 in the ARM address space is at location 0, the word 1 is at 4, the word 2 is at 8,and so on

 General purpose computers have sophisticated

instruction sets. Some of this sophistication is required simply to provide the functionality of a general computer while other aspects of instruction sets may be provided to increase performance, reduce code size, or otherwise improve program characteristics

Data operation
In C we consider both arithmetic and logical

instructions as well as instructions for reading and writing memory

In the ARM processor, arithmetic and logical

operations cannot be performed directly on memory locations

 ARM is a load-store architecturedata

operands must first be loaded into the CPU and then stored back to main memory to save the results CPSR register is set automatically during every arithmetic, logical, or shifting operation ARM has 16 general-purpose registers, r0 through r15 0 - 1 = -1 : 0x0 - 0x1 = 0xffffffff, with NZCV1000

Basic ARM programming model

Arithmetic Instructions

ADD r0,r1,r2 ADD r0,r1,#2 RSB r0, r1,r2

 MUL instruction multiplies two values, but with

some restrictions: 1) No operand may be an immediate, 2) two source operands must be different registers MLA r0,r1,r2,r3 sets r0 to the value r1*r2+r3.

Logical instructions

exclusive or is called EOR BIC r0, r1, r2 which sets r0 to r1 and not r2. This instruction uses the second source operand as a mask Where a bit in the mask is 1

Shift/rotate instructions

- LSL and LSR modifiers perform left and right logical shifts, filling the least- s significant - bits of the operand with zeroes - arithmetic shift left is equivalent to an LSL -ASR copies the sign bitif the sign is 0, a 0 is copied, while if the

Comparision & move instruction

ARM load-store instruction

 The ARM load and store instructions do not

directly refer to main memory addresses, since a 32-bit address would not fit into an instruction that included an opcode and operands Instead,the ARM uses register-indirect addressing LDR r0,[r1] LDR r0,[r1, r2] LDR r0,[r1, #4]

Register-indirect addressing in the ARM

 we need to be able to set a register to an arbitrary

32-bit value. In the ARM,the standard way to set a register to an address is by performing arithmetic on the program counter By adding or subtracting to the PC a constant equal to the distance between the current instruction and the desired location, we can generate the desired address without performing a load an ADR pseudo-operation to simplify this step

Computing an absolute address using the PC

ADR r1,FOO

C statement : x = (a + b) - c;

Do yourself : y = a (b + c);

C statement: z = (a<< 2) | (b & 15);

 ARM also supports several forms of base-plus-

offset addressing example : LDR r0,[r1,#16] where, r1 is referred to as the base and the immediate value the offset which may have any value up to 4,096. another register may also be used as the offset Addressing mode has two other variations : autoindexing and post-indexing

 Auto indexing: LDR r0,[r1,#16]!

first adds 16 to the value of r1, and then uses that

new value as the address The ! operator causes the base register to be updated with the computed address so that it can be used again later Post-indexing does not perform the offset calculation until after the fetch has been performed LDR r0,[r1],#16

 The B (branch) instruction is the basic mechanism

inARM for changing the flow of control The address that is the destination of the branch is often called the branch target Braches are PC-relativethe branch specifies the offset from the current PC value to the branch target The offset is in words, but because the ARM is byte addressable, the offset is multiplied by four (shifted left two bits, actually) to form abyte address Thus, the instruction B #100 will add 400 to the current PC value

Flow of Control

C code:

Implementing C switch statement

The above statement could be coded like an if

statement by first testing testA, then testB, and so forth. However, it can be more efficiently implemented by using base-plus-offset addressing and building what is known as a branch table