TABLE OF CONTENTS

Sl.No: 1. 2. 3. 4. 5.

Name of the Experiment Study of Simulation Tools Study of Synthesis Tools Place and root and back annotation for FPGA Study of development tool for FPGA for schematic entry and Verilog Design and simulation of pipelined serial and parallel adder to add/subtract 8 number of size, 12-bits each in 2's complement Study of FPGA board and testing on board LEDs and switches using Verilog codes Design and simulation of back annotated Verilog files for multiplying two signed,8-bit numbers in 2's complement Design of traffic light controller using Verilog and above tools Testing the traffic controller design developed in Sl. NO.8 on the FPGA board Design a realtime clock and demonstrate its working on the FPGA board

Page 2 17 25 30

41 55

6. 7.

63 66 77 81

8. 9. 10.

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Expt.No: 1 Date:

STUDY OF SIMULATION TOOLS

Aim: To study the simulation tools.

Procedure: 1. Creating a New Project
Xilinx Tools can be started by clicking on the Project Navigator Icon on the Windows desktop. This should open up the Project Navigator window on your screen.

2. Opening a project
Select File->New Project to create a new project. This will bring up a new project window on the desktop. Fill up the necessary entries as follows:

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 Project Name: Write the name of your new project Project Location: The directory where you want to store the new project Leave the top level module type as HDL. Example: If the project name were and_gate, enter and_gate as the project name and then click Next. Clicking on NEXT should bring up the following window:

For each of the properties given below, click on the value area and select from the list of values that appear. O Device Family: Family of the FPGA/CPLD used. In this laboratory we will be using the Spartan3 FPGAs. O Device: The number of the actual device. For this lab you may enter XC3S400 (this can be found on the attached prototyping board) O Package: The type of package with the number of pins. The Spartan FPGA used in this lab is packaged in PQ208 package. O Speed Grade: The Speed grade is -4. O Synthesis Tool: XST [VHDL/Verilog] O Simulator: The tool used to simulate and verify the functionality of the design. ISE simulator is integrated in the Xilinx ISE. Hence choose ISE Simulator as the simulator. O Then click on NEXT to save the entries.

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All project files such as schematics, netlists, Verilog files, VHDL files, etc., will be stored in a subdirectory with the project name. A project can only have one top level HDL source file (or schematic). Modules can be added to the project to create a modular, hierarchical design. In order to open an existing project in Xilinx Tools, select File->Open Project to show the list of projects on the machine. Choose the project you want and click OK. Clicking on NEXT on the above window brings up the following window: (New Source Window)

3. Creating a Verilog HDL input file for a combinational logic design

First we will enter a design using a structural or RTL description using the Verilog HDL. You can create a Verilog HDL input file (.v file) using the HDL Editor available in the Xilinx ISE Tools (or any text editor). If adding an already existing source file (.v file) to the project, in the project Navigator window, select Project -> Add Copy Source and browse through the disk for the source file. If creating a new source file, in the Project Navigator window, select Project -> New Source. A window pops up. (Note: Add to project option is selected by default. If you do not select it then you will have to add the new source file to the project manually.)

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Select Verilog Module and in the File Name: area, enter the name of the Verilog source file you are going to create. Also make sure that the option Add to project is selected so that the source need not be added to the project again. Then click on Next to accept the entries. This pops up the following window:

In the Port Name column, enter the names of all input and output pins and specify the Direction accordingly. A Vector/Bus can be defined by entering appropriate bit numbers in the MSB/LSB columns. Then click on Next to get a window showing all the new source information. If any changes are to be made, just click on Back to go back and make changes. If everything is acceptable, click on Finish to continue. Page 5

4. Editing the Verilog source file

The source file will now be displayed in theProject Navigator window. The source file window can be used as a text editor to make any necessary changes to the source file. All the input/output pins will be displayed. Save your Verilog program periodically by selecting the File->Save from the menu. You can also edit Verilog programs in any text editor and add them to the project directory using Add Copy Source

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Adding

Logic in the generated Verilog Source code template: The Verilog source code template generated shows the module name, the list of ports and also the declarations (input/output) for each port. Combinational logic code can be added to the verilog code after the declarations and before the endmodule line. For example, an output c in an OR gate with inputs a and b can be described as, assign c = a & b; Remember that the names are case sensitive. Other constructs for modeling the logic function: A given logic function can be modeled in many ways in verilog. Here is another example in which the logic function is implemented as a truth table using a case statement:
module or_gate(a,b,z); input a; input b; output c; reg c; always @(a and b) begin case ({a,b}) 00: c = 1'b0; 01: c = 1'b0; 10: c = 1'b0; 11: c = 1'b1; endcase end endmodule

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1. Simulation of the coding:Run the Check syntax Process window > synthesize > double click check syntax>and remove errors, if present, with proper syntax & coding.

Click on the symbol of FPGA device and then right click > click on new source

Select the Test Bench Waveform and give the file name select entity click next and finish

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Select the desired parameters for simulating your design. In this case combinational circuit and simulation time click finish

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Assign all input signal using just click on this and save file. From the source process window, click Behavioral simulation from drop-down menu

Select the test bench file (.tbw) and click process button double click the Simulation Behavioral Model

Verify your design in wave window by seeing behavior of output signal with respect to input signal.

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Examples: AND Gate:

Output:
# # # # # # # # # AND Gate -----------------------------------------------Input1 Input2 Output -----------------------------------------------0 0 0 0 1 0 1 0 0 1 1 1 -------------------------------------------------

PROGRAM: AND Gate:

// Module Name: Andgate module Andgate(i1, i2, out); input i1; input i2; output out; and (out,i1,i2); endmodule // Module Name: Stimulus.v module Stimulus_v; // Inputs reg i1; reg i2; // Outputs wire out; Page 11

// Instantiate the Unit Under Test (UUT) Andgate uut ( .i1(i1), .i2(i2), .out(out) ); initial begin $display("\t\t\t\tAND Gate"); $display("\t\t--------------------------------------"); $display("\t\tInput1\t\t Input2\t\t Output"); $display("\t\t--------------------------------------"); $monitor("\t\t\t%b\t\t%b\t\t%b ",i1,i2,out); #4 $display("\t\t--------------------------------------"); end initial begin i1=1'b0; i2=1'b0; #1 i2=1'b1; #1 i1=1'b1; i2=1'b0; #1 i1=1'b1; i2=1'b1; #1 $stop; end endmodule Encoder:

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Output:
# # # # # # # # # 4to2 Encoder ------------------------------------Input Output ------------------------------------1000 00 0100 01 0010 10 0001 11 ------------------------------------

PROGRAM: Encoder:
// Module Name: Encd2to4 module Encd2to4(i0, i1, i2, i3, out0, out1); input i0; input i1; input i2; input i3; output out0; output out1; reg out0,out1; always@(i0,i1,i2,i3) case({i0,i1,i2,i3}) 4'b1000:{out0,out1}=2'b00; 4'b0100:{out0,out1}=2'b01; 4'b0010:{out0,out1}=2'b10; 4'b0001:{out0,out1}=2'b11; default: $display("Invalid"); endcase endmodule // Module Name: Stimulus.v Page 13

module Stimulus_v; // Inputs reg i0; reg i1; reg i2; reg i3; // Outputs wire out0; wire out1; // Instantiate the Unit Under Test (UUT) Encd2to4 uut ( .i0(i0), .i1(i1), .i2(i2), .i3(i3), .out0(out0), .out1(out1) ); initial begin $display("\t\t 4to2 Encoder"); $display("\t\t------------------------------"); Decoder:

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Output:
# # # # # # # # # 2to4 Decoder ------------------------------------Input Output ------------------------------------00 1000 01 0100 10 0010 11 0001 ------------------------------------

Decoder:
// Module Name: Decd2to4 module Decd2to4(i0, i1, out0, out1, out2, out3); input i0; input i1; output out0; output out1; output out2; output out3; reg out0,out1,out2,out3; always@(i0,i1) case({i0,i1}) 2'b00: {out0,out1,out2,out3}=4'b1000; 2'b01: {out0,out1,out2,out3}=4'b0100; 2'b10: {out0,out1,out2,out3}=4'b0010; 2'b11: {out0,out1,out2,out3}=4'b0001; default: $display("Invalid"); endcase endmodule module Stimulus_v; // Inputs reg i0; reg i1; // Outputs wire out0; wire out1; wire out2; wire out3; Page 15

RESULT:

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Exp. No: 2 Date : Aim:

STUDY OF SYNTHESIS TOOLS

To study the synthesis tools.

THEORY:

Now that you have created the source files, verified the designs behavior with simulation, and added constraints, you are ready to synthesize and implement the design. Implementing Design: Select file_name.v in the synthesis/implementation tab. In the Processes for Source window, click the + sign next to Implement Design. The Translate, Map, and Place & Route processes are displayed. Double-click the top level Implement Design process.ISE determines the current state of your design and runs the processes needed to pull your design through implementation. In this case, ISE runs the Translate, Map and PAR processes. Your design is now pulled through to a placed-and-routed state. This feature is called the pull through model. After the processes have finished running, notice the status markers in the Processes for Source window. You should see green checkmarks next to several of the processes, indicating that they ran successfully. If there are any yellow exclamation points, check the warnings in the Console tab or the Warnings tab within the Transcript window. If a red X appears next to a process, you must locate and fix the error before you can continue.

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Verification of Synthesis: Your synthesized design can be viewed as a schematic in the Register Transfer Level (RTL) Viewer. The schematic view shows gates and elements independent of the targeted Xilinx device. 1. In the Processes for Source window, double-click View RTL Schematic found in the Synthesize - XST process group. The top level schematic representation of your synthesized design opens in the workspace. (Refer above picture) 2. Right-click on the symbol and select Push Into the Selected Instance to view the schematic in detail. The Design tab appears in the Sources in Project window, enabling you to view the design hierarchy. In the schematic, you can see the design components you created in the HDL source, and you can push into symbols to view increasing levels of detail. 3. Close the schematic window.

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Examples:
Multiplexer:

Output:
# # # # # # # # # # # 4to1 Multiplexer ----------------------------------------------Input=1011 ----------------------------------------------Selector Output ----------------------------------------------{0,0} 1 {1,0} 0 {0,1} 1 {1,1} 1 -----------------------------------------------

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PROGRAM: Multiplexer:
// Module Name: Mux4to1 module Mux4to1(i0, i1, i2, i3, s0, s1, out); input i0; input i1; input i2; input i3; input s0; input s1; output out; wire s1n,s0n; wire y0,y1,y2,y3; not (s1n,s1); not (s0n,s0); and (y0,i0,s1n,s0n); and (y1,i1,s1n,s0); and (y2,i2,s1,s0n); and (y3,i3,s1,s0); or (out,y0,y1,y2,y3); endmodule // Module Name: Stimulus.v module Stimulus_v; // Inputs reg i0; reg i1; reg i2; reg i3; reg s0; reg s1; // Outputs wire out; // Instantiate the Unit Under Test (UUT) Mux4to1 uut ( .i0(i0), .i1(i1), .i2(i2), .i3(i3), .s0(s0), .s1(s1), .out(out) ); Page 21

initial begin $display("\t\t\t 4to1 Multiplexer"); $display("\t\t------------------------------------"); #1 $display("\t\t\t Input=%b%b%b%b",i0,i1,i2,i3); $display("\t\t------------------------------------"); $display("\t\tSelector\t\t\t\tOutput"); $display("\t\t------------------------------------"); $monitor("\t\t{%b,%b}\t\t\t\t\t%b",s0,s1,out); #4 $display("\t\t------------------------------------"); end initial begin i0=1; i1=0; i2=1; i3=1; #1 s0=0; s1=0; #1 s0=1; s1=0; #1 s0=0; s1=1; #1 s0=1; s1=1; #1 $stop; end endmodule Demultiplexer:

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Output:
# # # # # # # # # # # 1to4 Demultiplexer ----------------------------------------------Input=1 ----------------------------------------------Status Output ----------------------------------------------{0,0} 1000 {0,1} 0100 {1,0} 0010 {1,1} 0001 ---------------------------------------------

Demultiplexer:
// Module Name: Dux1to4 module Dux1to4(in, s0, s1, out0, out1, out2, out3); input in; input s0; input s1; output out0; output out1; output out2; output out3; wire s0n,s1n; not(s0n,s0); not(s1n,s1); and (out0,in,s1n,s0n); and (out1,in,s1n,s0); and (out2,in,s1,s0n); and (out3,in,s1,s0); endmodule // Module Name: stimulus.v module stimulus_v; // Inputs reg in; reg s0; reg s1; Page 23

// Outputs wire out0; wire out1; wire out2; wire out3; // Instantiate the Unit Under Test (UUT) Dux1to4 uut ( .in(in), .s0(s0), .s1(s1), .out0(out0), .out1(out1), .out2(out2), .out3(out3) ); initial begin $display("\t\t 1to4 Demultiplexer"); $display("\t\t------------------------------------"); #1 $display("\t\t\t\tInput=%b",in); $display("\t\t------------------------------------"); $display("\t\tStatus\t\t\t\tOutput"); $display("\t\t------------------------------------"); $monitor("\t\t{%b,%b}\t\t\t\t%b%b%b%b",s1,s0,out0,out1,out2,out3); #4 $display("\t\t------------------------------------"); end initial begin in=1; #1 s1=0;s0=0; #1 s1=0;s0=1; #1 s1=1;s0=0; #1 s1=1;s0=1; #1 $stop; end endmodule

Result:

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Expt.No: 3 Date :

STUDY OF PLACE AND ROOT AND BACK ANNOTATION FOR FPGAS.

AIM:

To study Place & Root and Back annotation for FPGAs. THEORY: After implementation is complete, you can verify your design before downloading it to a device. Viewing Placement: In this section, you will use the Floor planner to verify your pin outs and placement. Floor planner is also very useful for creating area groups for designs. 1. Select the file_name.v source file in the Sources in Project window. 2. Click the + sign to expand the Place & Route group of processes. 3. Double-click the View/Edit Placed Design (Floorplanner) process. The Floorplanner view opens. 4. Select ViewZoomToBox and then use the mouse to draw a box around the counter instance, shown in green on the right side of the chip. 5. This Fig 2 shows where the entire design was placed. Click on any of the components listed in the Design Hierarchy window to see where each component is placed. 6. Zoom in to the right side of the chip even more, and place your mouse over the K13pad. You can see that your pinout constraint was applied - the DIRECTION pin is placed at K13. 7. Close the Floorplanner without saving.

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2. Just double click View/Edit Routed Design to view interconnection wires and
blocks Click the pin to see where it is placed in FPGA. And Zoom particular area to see Place and Routing. If you want to change the place of the design, click and trace to another slice

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Zoom out to see entire gate placed in FPGA & close FPGA Editor.

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Viewing Resource Utilization in Reports: Many ISE processes produce summary reports which enable you to check information about your design after each process is run. Detailed reports are available from the Processes for Source window. You can also view summary information and access most often-utilized reports in the Design Summary. Click on the Design Summary tab at the bottom of the window. If you closed the summary during this tutorial, you can reopen it by doubleclicking the View Design Summary process.

Black Annotation:
Double click Back annotated Pin Location

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Result:
Place & Route, the process of optimization of logic cells for effective utilization of FPGA area and the speed of operation, is used to modify and infer the following: 1) RE-ASSIGNMENT OF PINS 2) RE-LOCATION OF SLICES 3) RUN TIME MINIMIZATION Page 29

Exp. No: 4 Date :

STUDY OF DEVELOPMENT TOOLS FOR FPGA FOR SCHEMATIC ENTRY & VERILOG

Aim: To study the Schematic tools. Theory:

This topic gives the overview of schematic entry using ISE .Here we give the explanation with an example of full adder. The step to generate a full adder is given in this chapter. We generate Truth Table for the required functionality. Solve the Equation and we get the gates required to implement the design.

The equations for Full-Adder,

Procedure:
1. 2. 3. 4. Started by clicking on the Project Navigator Icon on the Windows desktop. Select File->New Project to create a new project. Fill the necessary informations based on previous chapters. Then click on NEXT. 5. Click on the NEW SOURCE.

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Select the Categories and symbols or type the symbol name in this case just type xor2, and2, or2.

Click Add wire button and add wire as required.

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Click on Add IO markers

Double click on the Marker

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Enter the Name and click ok.

Final schematic diagram. Then synthesis or simulation process

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To view the VHF file generated Clock on View HDL functional model in Design utilities

Compilation and Implementation of the Design

The design has to be compiled and implemented before it can be checked for correctness, by running functional simulation or downloaded onto the prototyping board. With the top-level Verilog / VHDL file opened (can be done by doubleclicking that file) in the HDL editor window in the right half of the Project Navigator, and the view of the project being in the Module view , the implement design option can be seen in the process view. Design entry utilities and Create Programming File options can also be seen in the process view. To compile the design, expand the Implement design option by clicking on the add sign (+) in front of the implement design tab. Now click on the option Compile Design in the Processes window. It will go through steps like Check Syntax, Compile Logic, Interpret Feedbacks, Reformat Logic, and Optimize Hierarchy. If any of these steps could not be done or done with errors, it will place a X mark in front of that, otherwise a tick mark will be placed after each of them to indicate the successful completion. If everything is done successfully, a tick mark will be placed before the Compile Design option. If there are warnings, one can see mark in front of the option indicating that there are some warnings. One can look at the warnings or errors in the Console window present at the bottom of the Navigator window. Every time the design file is saved; all these marks disappear asking for a fresh compilation.

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To implement the design, double-click on the Implement Design option. It has many steps in it e.g., Translation, Fitter, Timing Analysis and Launch Tools. One can use the timing analyzer and post fit chip viewer from the Launch Tools section once the implementation is completed successfully. If the implementation is done successfully, a tick mark will be placed in front of the Implement Design option. The above two steps can be done in a single step by just double-clicking on the Implement Design option straightaway. This will do the compilation first and then the implementation.

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A bitstream file needs to be prepared for each design and downloaded onto the Pegasus prototyping board. This is done as follows: User Constraint File: 1. Connect the 5V DC power cable to the power input on the demo board (J4). 2. Connect the download cable between the PC and demo board (J7). 3. Select Synthesis/Implementation from the drop-down list in the Sources window. 4. Select design file in the Sources window. 5. In the Processes window, click the + sign to expand the Generate Programming File processes. 6. Double-click the Configure Device (iMPACT) process. 7. The Xilinx Web Talk Dialog box may open during this process. Click Decline. 8. Select Disable the collection of device usage statistics for this project only and click OK. iMPACT opens and the Configure Devices dialog box is displayed.

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9.

In the Welcome dialog box, select Configure devices using BoundaryScan (JTAG). 10. Verify that Automatically connect to a cable and identify BoundaryScan chain is selected. 11. Click Finish. 12. If you get a message saying that there are two devices found, click OK to continue. The devices connected to the JTAG chain on the board will be detected and displayed in the iMPACT window. 13. The Assign New Configuration File dialog box appears. To assign a configuration file to the xc3s400 device in the JTAG chain, select the counter.bit file and click Open. 14. If you get a Warning message, click OK. 15. Select Bypass to skip any remaining devices. 16. Right-click on the xc3s400 device image, and select Program. The Programming Properties dialog box opens. 17. Click OK to program the device. When programming is complete, the Program Succeeded message is displayed. On the board, LEDs 0, 1, 2, and 3 are lit, indicating that the counter is running. 18. Close iMPACT without saving. Note that you can assign pin numbers only to top-level Verilog / VHDL file.

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 For the AND_GATE example, the user constraint file used is as follows: # Pin 58 and 57 are FPGA pins connected to SW0 and SW1 in the Pegasus Board # Pin 51 of the FPGA is connected to LED0 in the Pegasus Board.
NET a LOC="P58"; NET b LOC="P57"; NET c LOC="P51";

Click on the Module View, choose the main design file and in the Process View -> User Constraints > Edit Constraints option; add the user constraint file for the design. Then, in the Process View window (left-bottom), double click on the Generate Programming file. Wait for the programming file to be generated and then click on the Generate Programming FileConfigure Device option. Once this is done, the following image pops up (JTAG Programmer Window). Choose the Select boundary scan option and click on NEXT. On clicking Next, the following image comes up: Choose the option Automatically connect to cable and identify device and click on Finish. Once this is done, a window pops up where you will see two devices connected in the Boundary scan. The first one xc3s400 is the Spartan FPGA. Right click on the xc3s400 device and select Assign New configuration file. Once this is done, click on Ok on the following pop up which will take you to the Select bit file window as shown Choose or_gate.bit

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Now Right click on the xs3s400 device and select program as shown below:

Once you select program, the following window will pop up. Click on OK [There is no need to check the Verify option].

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Once you click OK, you can see the status of the bitstream download in the lower half of the window.

Ensure that the Programmed Successfully message appears in the message window. If this doesnt appear, it could be due to the following reasons: 1. The JTAG cable is not connected between the FPGA board and the PC parallel port. 2. You did not select the proper device for download in the JTAG chain. 3. The bitstream generated was not for the device: XC2S50-PQ208 In order to use the respective input/output device on the board, the pin number of the device must be connected properly to the designs input/output. If the Programmed Successfully message appears in the message window, you can start testing your design in the FPGA board using the input and output devices on the board.

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Expt No: 5 Date :

IMPLEMENTATION OF SERIAL ADDER

Aim:

To design pipeline Serial Adder module for adding two 8-bit numbers using Verilog HDL
Apparatus Required:

PC with Windows XP. XILINX, Modelsim software. FPGA kit. RS 232 cable.

WORKING:

Step1: Two 8-bit numbers from A, B inputs are stored into two 8-bit shift registers by activating the LOAD signal. Step2: These registered inputs from both registers are shifted serially, From LSB to MSB bits into the 1-bit full adder section by the arrival of each clock pulse with the LOAD signal as low. Step3: The carry_out from full adder section is feed back as carry_in to the same full adder section and the sum Output bits from the full adder section are entered as serially into the serial in parallel out shift register by the arrival of each clock pulse. Step4: The addition process would take 8 clock cycles to complete. The sum and carry out bits are again stored into Parallel in parallel out register, by the arrival of the terminal count from the divide by 8 counter sections these sum and carry bits are appeared on out put LEDs.

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Serial adder

PROGRAM: Serial Adder:

module SERIALADDER_TOP( RST,LOAD,A3,A2,A0,A1,A5,A4,A6,A7,B7,B6,B4,B5,B1,B0, B2,B3,clk1,S3,S4,S0,Cout,S2,S1,S7,S6,S5,Done); input RST,LOAD,A3,A2,A0,A1,A5,A4; input A6,A7,B7,B6,B4,B5,B1,B0; input B2,B3,clk1; output S3,S4,S0,Cout,S2,S1,S7,S6; output S5,Done; wire w50,w51,w52,w53,w54,w55,w56,w57; wire w58,w59,w60,w61,w62,w63,w64,w65; wire w66,w67,w68,w69,w70,w71,w72,w73; wire w74,w75,w76,w77,w78,w79,w80,w81; wire w82,w83,w84,w85,w86,w87,w88,w89; wire w90,w91,w92,w93,w94,w95,w96,w97; wire w98,w99,w100,w101,w102,w103,w104,w105; Page 42

wire w106,w107,w108,w109,w110,w111,w112,w113; wire w114,w115,w116,w117,w118,w119,w120,w121; wire w122,w123,w124,w125,w126,w127,w128,w129; wire w130,w131,w132,w133,w134,w135,w136,w137; dreg #(12) dreg6(w32,w36,w34,w35,clk1); mux #(10) mux(w34,w32,LOAD,LOAD); or #(16) or2(w35,RST,Done); dreg #(12) dreg7(w38,w39,w37,w31,clk1); dreg #(12) dreg8(Cout,w49,w38,RST,Done); or #(86) or21(w31,RST,LOAD); mux #(12) mux_Sh1(w51,w50,A5,LOAD); mux #(12) mux_Sh2(w53,w52,A6,LOAD); dreg #(6) dreg2_Sh3(w54,w55,w51,RST,clk1); dreg #(6) dreg1_Sh4(w52,w57,w56,RST,clk1); mux #(12) mux_Sh5(w58,w54,A4,LOAD); dreg #(6) dreg3_Sh6(w60,w61,w59,RST,clk1); mux #(12) mux_Sh7(w56,RST,A7,LOAD); dreg #(6) dreg1_Sh8(w50,w62,w53,RST,clk1); mux #(12) mux_Sh9(w59,w63,A2,LOAD); dreg #(6) dreg3_Sh10(w63,w65,w64,RST,clk1); mux #(12) mux_Sh11(w64,w66,A3,LOAD); mux #(12) mux_Sh12(w68,w67,A0,LOAD); dreg #(6) dreg3_Sh13(w14,w69,w68,RST,clk1); mux #(12) mux_Sh14(w70,w60,A1,LOAD); dreg #(6) dreg3_Sh15(w67,w71,w70,RST,clk1); dreg #(6) dreg3_Sh16(w66,w72,w58,RST,clk1); mux #(12) mux_Sh17(w74,w73,B5,LOAD); mux #(12) mux_Sh18(w76,w75,B6,LOAD); dreg #(6) dreg2_Sh19(w77,w78,w74,RST,clk1); dreg #(6) dreg1_Sh20(w75,w80,w79,RST,clk1); mux #(12) mux_Sh21(w81,w77,B4,LOAD); dreg #(6) dreg3_Sh22(w83,w84,w82,RST,clk1); mux #(12) mux_Sh23(w79,RST,B7,LOAD); dreg #(6) dreg1_Sh24(w73,w85,w76,RST,clk1); mux #(12) mux_Sh25(w82,w86,B2,LOAD); dreg #(6) dreg3_Sh26(w86,w88,w87,RST,clk1); mux #(12) mux_Sh27(w87,w89,B3,LOAD); mux #(12) mux_Sh28(w91,w90,B0,LOAD); dreg #(6) dreg3_Sh29(w23,w92,w91,RST,clk1); mux #(12) mux_Sh30(w93,w83,B1,LOAD); dreg #(6) dreg3_Sh31(w90,w94,w93,RST,clk1); dreg #(6) dreg3_Sh32(w89,w95,w81,RST,clk1); not #(23) inv_Di33(w96,w31); xor #(15) xor2_Di34(w98,w97,w96); xor #(15) xor2_Di35(w101,w99,w100); dreg #(2) dreg137_Di36(w103,w104,w102,w31,clk1); xor #(15) xor2_Di37(w107,w105,w106); and #(15) and2_Di38(w106,w103,w108); dreg #(15) dreg138_Di39(w97,w110,w109,w31,clk1); Page 43

dreg #(2) dreg139_Di40(w99,w112,w111,w31,clk1); mux #(12) mux_Di41(w113,w107,w31,Done); and #(26) and2_Di42(w100,w97,w96); dreg #(6) dreg140_Di43(Done,w115,w114,w31,clk1); and #(26) and2_Di44(w108,w99,w100); mux #(12) mux_Di45(w111,w101,w31,Done); mux #(12) mux_Di46(w109,w98,w31,Done); dreg #(17) dreg141_Di47(w105,w116,w113,w31,clk1); xor #(15) xor2_Di48(w117,w103,w108); mux #(12) mux_Di49(w102,w117,w31,Done); and #(15) and3_Di50(w114,w118,w116,w32); and #(15) and3_Di51(w118,w110,w99,w103); dreg #(6) dreg108_Se52(w43,w119,w44,RST,clk1); dreg #(6) dreg110_Se53(w41,w120,w42,RST,clk1); dreg #(6) dreg111_Se54(w44,w121,w45,RST,clk1); dreg #(6) dreg104_Se55(w45,w122,w46,RST,clk1); dreg #(6) dreg105_Se56(w48,w123,w40,RST,clk1); dreg #(6) dreg107_Se57(w46,w124,w47,RST,clk1); dreg #(6) dreg105_Se58(w47,w125,w48,RST,clk1); dreg #(6) dreg106_Se59(w42,w126,w43,RST,clk1); xor #(26) xor2_fu60(w127,w14,w23); and #(15) and2_fu61(w128,w14,w23); xor #(15) xor2_fu62(w40,w127,w38); and #(15) and2_fu63(w129,w127,w38); or #(15) or2_fu64(w37,w129,w128); dreg #(6) dreg116_SH65(S4,w130,w45,RST,Done); dreg #(6) dreg117_SH66(S3,w131,w44,RST,Done); dreg #(6) dreg118_SH67(S5,w132,w46,RST,Done); dreg #(6) dreg119_SH68(S7,w133,w48,RST,Done); dreg #(6) dreg120_SH69(S1,w134,w42,RST,Done); dreg #(6) dreg121_SH70(S6,w135,w47,RST,Done); dreg #(6) dreg122_SH71(S2,w136,w43,RST,Done); dreg #(6) dreg123_SH72(S0,w137,w41,RST,Done); endmodule // Simulation parameters in Verilog Format always #1000 RST=~RST; #2000 LOAD=~LOAD; #4000 A3=~A3; #8000 A2=~A2; #16000 A0=~A0; #32000 A1=~A1; #64000 A5=~A5; #128000 A4=~A4; #256000 A6=~A6; #512000 A7=~A7; #1024000 B7=~B7; #2048000 B6=~B6; #4096000 B4=~B4; Page 44

#8192000 B5=~B5; #16384000 B1=~B1; #32768000 B0=~B0; #65536000 B2=~B2; #131072000 B3=~B3; #1000 clk1=~clk1; // Simulation parameters // RST CLK 10 10 // LOAD CLK 20 20 // A3 CLK 40 40 // A2 CLK 80 80 // A0 CLK 160 160 // A1 CLK 320 320 // A5 CLK 640 640 // A4 CLK 1280 1280 // A6 CLK 2560 2560 // A7 CLK 5120 5120 // B7 CLK 10240 10240 // B6 CLK 20480 20480 // B4 CLK 40960 40960 // B5 CLK 81920 81920 // B1 CLK 163840 163840 // B0 CLK 327680 327680 // B2 CLK 655360 655360 // B3 CLK 1310720 1310720 // clk1 CLK 10.00 10.00

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Output:

IMPLEMENTATION OF PARALLEL PIPELINE ADDER & SUBTRACTOR

Aim:

To design pipelined Adder and Sub tractor for two 8-bit numbers using Verilog HDL.
WORKING:

The adder/subtractor works on the principle of addition of 2s complement input with another input for subtraction. Step1: Circuit loads two 8-bit numbers from A, B inputs and stores these two numbers in two 8-bit registers. Step2: The registered inputs from B- reg and its complements are applied to the multiplexer section. By using the selection line Add/Sub of mux it selects one of the B inputs.
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Step3: Multiplexer output is complimented form of B when selection line as sub and same inputs of B when selection line as add. Step4: Both registered outputs are applied to the parallel adder section in first clock cycle, and result is stored in 9-bit register and registered output appears on out put LEDs. Step5: Circuit acts as adder when selection line is zero and acts as Subtractor when selection line is one.

BLOCK DIAGRAM:

PROGRAM: module Adder_Subtractor_Top( B5,addbsub,clk1,RST,A7,A6,A5,A4, A3,A2,A1,B7,B6,B4,B3,B2, B1,B0,A0,Q7,COUT,Q0,Q1,Q2, Q3,Q4,Q5,Q6); input B5,addbsub,clk1,RST,A7,A6,A5,A4; input A3,A2,A1,B7,B6,B4,B3,B2; input B1,B0,A0; output Q7,COUT,Q0,Q1,Q2,Q3,Q4,Q5; output Q6; wire w68,w69,w70,w71,w72,w73,w74,w75; wire w76,w77,w78,w79,w80,w81,w82,w83; wire w84,w85,w86,w87,w88,w89,w90,w91; wire w92,w93,w94,w95,w96,w97,w98,w99; wire w100,w101,w102,w103,w104,w105,w106,w107; wire w108,w109,w110,w111,w112,w113,w114,w115; wire w116,w117,w118,w119,w120,w121,w122,w123; wire w124,w125,w126,w127,w128,w129,w130; not #(17) inv(w21,RST); Page 47

dreg #(12) dreg2(w23,w24,w22,RST,clk1); not #(10) inv(w66,w23); mux #(10) mux(COUT,w23,w66,addbsub); not #(10) inv(w67,w21); mux #(17) mux(w50,w67,w21,addbsub); dreg #(3) dreg16_re1(w16,w68,B4,RST,clk1); dreg #(3) dreg17_re2(w15,w69,B3,RST,clk1); dreg #(3) dreg18_re3(w13,w70,B0,RST,clk1); dreg #(3) dreg19_re4(w12,w71,B1,RST,clk1); dreg #(3) dreg20_re5(w14,w72,B2,RST,clk1); dreg #(3) dreg21_re6(w18,w73,B6,RST,clk1); dreg #(3) dreg22_re7(w19,w74,B7,RST,clk1); dreg #(3) dreg23_re8(w17,w75,B5,RST,clk1); mux #(19) mux_mu9(w26,w19,w76,addbsub); mux #(19) mux_mu10(w25,w18,w77,addbsub); not #(12) inv_mu11(w78,w17); mux #(19) mux_mu12(w31,w16,w79,addbsub); not #(12) inv_mu13(w80,w15); not #(12) inv_mu14(w81,w14); not #(12) inv_mu15(w82,w12); not #(12) inv_mu16(w83,w13); not #(12) inv_mu17(w76,w19); not #(12) inv_mu18(w77,w18); mux #(19) mux_mu19(w32,w17,w78,addbsub); not #(12) inv_mu20(w79,w16); mux #(19) mux_mu21(w27,w15,w80,addbsub); mux #(19) mux_mu22(w28,w14,w81,addbsub); mux #(19) mux_mu23(w29,w12,w82,addbsub); mux #(19) mux_mu24(w30,w13,w83,addbsub); dreg #(3) dreg16_re25(Q4,w84,w45,RST,clk1); dreg #(3) dreg17_re26(Q3,w85,w41,RST,clk1); dreg #(3) dreg18_re27(Q0,w86,w43,RST,clk1); dreg #(3) dreg19_re28(Q1,w87,w44,RST,clk1); dreg #(3) dreg20_re29(Q2,w88,w42,RST,clk1); dreg #(3) dreg21_re30(Q6,w89,w47,RST,clk1); dreg #(3) dreg22_re31(Q7,w90,w48,RST,clk1); dreg #(3) dreg23_re32(Q5,w91,w46,RST,clk1); or #(17) or2_fa1_pa33(w94,w92,w93); xor #(17) xor2_fa2_pa34(w95,w30,w50); and #(10) and2_fa3_pa35(w93,w30,w50); and #(10) and2_fa4_pa36(w92,w95,w49); xor #(10) xor2_fa5_pa37(w43,w95,w49); or #(17) or2_fa6_pa38(w98,w96,w97); xor #(17) xor2_fa7_pa39(w99,w29,w94); and #(10) and2_fa8_pa40(w97,w29,w94); and #(10) and2_fa9_pa41(w96,w99,w51); xor #(10) xor2_fa10_pa42(w44,w99,w51); or #(17) or2_fa11_pa43(w102,w100,w101); xor #(17) xor2_fa12_pa44(w103,w28,w98); Page 48

and #(10) and2_fa13_pa45(w101,w28,w98); and #(10) and2_fa14_pa46(w100,w103,w52); xor #(10) xor2_fa15_pa47(w42,w103,w52); or #(17) or2_fa16_pa48(w106,w104,w105); xor #(17) xor2_fa17_pa49(w107,w27,w102); and #(10) and2_fa18_pa50(w105,w27,w102); and #(10) and2_fa19_pa51(w104,w107,w53); xor #(10) xor2_fa20_pa52(w41,w107,w53); or #(17) or2_fa21_pa53(w110,w108,w109); xor #(17) xor2_fa22_pa54(w111,w31,w106); and #(10) and2_fa23_pa55(w109,w31,w106); and #(10) and2_fa24_pa56(w108,w111,w54); xor #(10) xor2_fa25_pa57(w45,w111,w54); or #(17) or2_fa26_pa58(w114,w112,w113); xor #(17) xor2_fa27_pa59(w115,w32,w110); and #(10) and2_fa28_pa60(w113,w32,w110); and #(10) and2_fa29_pa61(w112,w115,w55); xor #(10) xor2_fa30_pa62(w46,w115,w55); or #(17) or2_fa31_pa63(w118,w116,w117); xor #(17) xor2_fa32_pa64(w119,w25,w114); and #(10) and2_fa33_pa65(w117,w25,w114); and #(10) and2_fa34_pa66(w116,w119,w57); xor #(10) xor2_fa35_pa67(w47,w119,w57); or #(10) or2_fa36_pa68(w22,w120,w121); xor #(17) xor2_fa37_pa69(w122,w26,w118); and #(10) and2_fa38_pa70(w121,w26,w118); and #(10) and2_fa39_pa71(w120,w122,w56); xor #(10) xor2_fa40_pa72(w48,w122,w56); dreg #(3) dreg16_re73(w54,w123,A4,RST,clk1); dreg #(3) dreg17_re74(w53,w124,A3,RST,clk1); dreg #(3) dreg18_re75(w49,w125,A0,RST,clk1); dreg #(3) dreg19_re76(w51,w126,A1,RST,clk1); dreg #(3) dreg20_re77(w52,w127,A2,RST,clk1); dreg #(3) dreg21_re78(w57,w128,A6,RST,clk1); dreg #(3) dreg22_re79(w56,w129,A7,RST,clk1); dreg #(3) dreg23_re80(w55,w130,A5,RST,clk1); endmodule // Simulation parameters in Verilog Format always #1000 B5=~B5; #2000 add/sub=~add/sub; #500 clk1=~clk1; #4000 RST=~RST; #8000 A7=~A7; #16000 A6=~A6; #32000 A5=~A5; #64000 A4=~A4; #128000 A3=~A3; #256000 A2=~A2; Page 49

#512000 A1=~A1; #1024000 B7=~B7; #2048000 B6=~B6; #4096000 B4=~B4; #8192000 B3=~B3; #16384000 B2=~B2; #32768000 B1=~B1; #65536000 B0=~B0; #131072000 A0=~A0; // Simulation parameters // B5 CLK 10 10 // add/sub CLK 20 20 // clk1 CLK 5.000 5.000 // RST CLK 40 40 // A7 CLK 80 80 // A6 CLK 160 160 // A5 CLK 320 320 // A4 CLK 640 640 // A3 CLK 1280 1280 // A2 CLK 2560 2560 // A1 CLK 5120 5120 // B7 CLK 10240 10240 // B6 CLK 20480 20480 // B4 CLK 40960 40960 // B3 CLK 81920 81920 // B2 CLK 163840 163840 // B1 CLK 327680 327680 // B0 CLK 655360 655360 // A0 CLK 1310720 1310720

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Output:

IMPLEMENTATION OF PARALLEL PIPELINE ADDER

Aim:

To implement Parallel Pipeline Adder using Verilog HDL

WORKING:

Step1: Circuit loads two 8-bit numbers from A, B inputs and stores these two numbers in two 8-bit registers, also store carry input in one bit register. Step2: Registered two 8-bit inputs and carry input are applied to the parallel adder section in first clock cycle. Step3: 8-bit sum and single bit carry out puts from the parallel adder are stored in 9-bit registers and the result appears on output LEDs in the second clock cycle.

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BLOCK DIAGRAM:

PROGRAM: module Adder_Par_Top( Cin,RST,B7,clk1,A7,A6,A5,A4, A3,A2,A1,A0,B6,B5,B4,B3, B2,B1,B0,R0,R7,R6,R5,R4, R3,R2,R1,Cout); input Cin,RST,B7,clk1,A7,A6,A5,A4; input A3,A2,A1,A0,B6,B5,B4,B3; input B2,B1,B0; output R0,R7,R6,R5,R4,R3,R2,R1; output Cout; wire w58,w59,w60,w61,w62,w63,w64,w65; wire w66,w67,w68,w69,w70,w71,w72,w73; wire w74,w75,w76,w77,w78,w79,w80,w81; wire w82,w83,w84,w85,w86,w87,w88,w89; wire w90,w91,w92,w93,w94,w95,w96,w97; wire w98,w99,w100,w101,w102,w103,w104,w105; wire w106,w107,w108,w109,w110,w111,w112; dreg dreg1(w3,w47,Cin,RST,clk1); dreg dreg2(Cout,w57,w18,w56,clk1); or or2_fa1_pa1(w60,w58,w59); xor xor2_fa2_pa2(w61,w1,w3); and and2_fa3_pa3(w59,w1,w3); and and2_fa4_pa4(w58,w61,w2); xor xor2_fa5_pa5(w19,w61,w2); or or2_fa6_pa6(w64,w62,w63); xor xor2_fa7_pa7(w65,w4,w60); Page 52

and and2_fa8_pa8(w63,w4,w60); and and2_fa9_pa9(w62,w65,w5); xor xor2_fa10_pa10(w20,w65,w5); or or2_fa11_pa11(w68,w66,w67); xor xor2_fa12_pa12(w69,w6,w64); and and2_fa13_pa13(w67,w6,w64); and and2_fa14_pa14(w66,w69,w7); xor xor2_fa15_pa15(w21,w69,w7); or or2_fa16_pa16(w72,w70,w71); xor xor2_fa17_pa17(w73,w8,w68); and and2_fa18_pa18(w71,w8,w68); and and2_fa19_pa19(w70,w73,w9); xor xor2_fa20_pa20(w22,w73,w9); or or2_fa21_pa21(w76,w74,w75); xor xor2_fa22_pa22(w77,w10,w72); and and2_fa23_pa23(w75,w10,w72); and and2_fa24_pa24(w74,w77,w11); xor xor2_fa25_pa25(w23,w77,w11); or or2_fa26_pa26(w80,w78,w79); xor xor2_fa27_pa27(w81,w12,w76); and and2_fa28_pa28(w79,w12,w76); and and2_fa29_pa29(w78,w81,w13); xor xor2_fa30_pa30(w24,w81,w13); or or2_fa31_pa31(w84,w82,w83); xor xor2_fa32_pa32(w85,w14,w80); and and2_fa33_pa33(w83,w14,w80); and and2_fa34_pa34(w82,w85,w17); xor xor2_fa35_pa35(w25,w85,w17); or or2_fa36_pa36(w18,w86,w87); xor xor2_fa37_pa37(w88,w16,w84); and and2_fa38_pa38(w87,w16,w84); and and2_fa39_pa39(w86,w88,w15); xor xor2_fa40_pa40(w26,w88,w15); dreg dreg16_re41(w11,w89,A4,RST,clk1); dreg dreg17_re42(w9,w90,A3,RST,clk1); dreg dreg18_re43(w2,w91,A0,RST,clk1); dreg dreg19_re44(w5,w92,A1,RST,clk1); dreg dreg20_re45(w7,w93,A2,RST,clk1); dreg dreg21_re46(w17,w94,A6,RST,clk1); dreg dreg22_re47(w15,w95,A7,RST,clk1); dreg dreg23_re48(w13,w96,A5,RST,clk1); dreg dreg16_re49(w10,w97,B4,RST,clk1); dreg dreg17_re50(w8,w98,B3,RST,clk1); dreg dreg18_re51(w1,w99,B0,RST,clk1); dreg dreg19_re52(w4,w100,B1,RST,clk1); dreg dreg20_re53(w6,w101,B2,RST,clk1); dreg dreg21_re54(w14,w102,B6,RST,clk1); dreg dreg22_re55(w16,w103,B7,RST,clk1); dreg dreg23_re56(w12,w104,B5,RST,clk1); dreg dreg16_re57(R4,w105,w23,RST,clk1); Page 53

dreg dreg17_re58(R3,w106,w22,RST,clk1); dreg dreg18_re59(R0,w107,w19,RST,clk1); dreg dreg19_re60(R1,w108,w20,RST,clk1); dreg dreg20_re61(R2,w109,w21,RST,clk1); dreg dreg21_re62(R6,w110,w25,RST,clk1); dreg dreg22_re63(R7,w111,w26,RST,clk1); dreg dreg23_re64(R5,w112,w24,RST,clk1); endmodule Output:

RESULT:

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Exp.No: 6 Date: Aim:

STUDY OF FPGA BOARD AND TESTING ONBOARD LEDs AND SWITCHES

To study FPGA board and test onboard LEDs and switches using verilog code. Testing a Digital Logic Circuit in FPGA
Testing a downloaded design requires connecting the inputs of the design to switches or ports and the outputs of the design to LEDs or 7-segment displays. In case of sequential circuits, the clock input(s) must also be connected to clock sources. These inputs and outputs can be connected to appropriately on the Digital Lab workbench. Model of the XC3S400 VLSI development board:

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Features which can be used to test the digital logic in the design: SPARTAN -3 FPGA: 400 k logic cell SPARTAN -3 FPGA in PQ208 Plastic Quad Flat Package (MXS3FK-PQ208-IM ) Three families Spartan 3 /Spartan 3L/Spartan 3 XA. Very low cost, high-performance logic solution for high-volume, consumeroriented applications. -Densities as high as 74,880 logic cells. -Three power rails for core (1.2V), I/Os (1.2V to 3.3V) and Auxiliary purposes (2.5V). -326 MHz system clock rate. -90 nm process technology. Select IO Signaling. -Up to 784 I/O pins. -622 Mb/s data transfer rate per IO. -18 single-ended signal standards. Logic Resources -Abundant Logic cells with shift register capability. -Wide Multiplexers. -Fast look-ahead carry logic. -Dedicated 18 x 18 Multipliers. Select RAM Hierarchical Memory. -Up to 1,872 Kbits of total block RAM. -Up to 520 Kbits of Distributed RAM. Digital Clock Manager (up to 4DCMs) -Clock skew elimination. -Frequency synthesis -High resolution phase shifting. Eight global clock lines and abundant routing. Seven Segment Display: Six-character multiplexed seven-segment LED display. Serial Interface: One RS-232 channel using MAX3223, 9 pin two channel serial interfaces. DB9 9-pin female connector (DCE connector). RS-232 transceiver/level translator using MAX3223 in SSOP package. Uses straight-through serial cable to connect to computer or workstation serial port. LCD Interface: 16 Character/ Digit 2 Row LCD. Traffic Light Control Interface: 16 green LEDS, 8 Red LEDS, 4 Yellow LEDS. Traffic Light Interface module will be connected using 60 pin Connector (J5). RTC: Six 7Segment Displays.

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Analog Interface: 12 bit AD7891 ADC and 12 bit AD7541 DAC. Analog Input Eight channels using ADC using AD7891, (500Ksps, 12 bit). Analog Output- Two channels using Two DACs-AD7541. (12 bit, 100 ns conversion time) DIP Switches: 16 DIP switches. LEDs: 23 onboard LEDS 16 output LEDs (OL 0 OL 15). Done LED.(DONE) 6 Power ON LEDs (LED12VN, LED12V, LED5V, LED3.3V, LED2.5V, LED1.2V). Push Button Switches: 16 momentary-contact push button switches in 4x4 matrix. User selectable configuration modes: Boundary scan, Master serial. User selectable Interface hardware: Traffic Light, RTC, ADC-DAC. Free IOs: 34 pin FRC Connector (J7) provided for free I/Os. Clock Oscillator: 4 MHz crystal clock oscillator. Socket for an auxiliary crystal oscillator clock source. JTAG port: JTAG download cable (parallel III) interface. Power Supplies: 5 volts regulated power supply provided along with the board. On board 3.3V, 2.5V, 1.2V regulators. FPGA supplies viz. Vccint (1.2V) & Vcco (3.3V) are generated on board In order to use the respective input/output device on the board, the pin number of the device must be connected properly to the designs input/output. In the Pegasus board, the pin number of these inputs/outputs are mentioned in the board manual and also mentioned in the components of the board. Observing outputs using the on-board LEDs and Seven Segment Displays: The Pegasus boards have six on-board 7-segment displays, which is connected to the corresponding on-board Spartan FPGA chip. This display can be used to observe the outputs of your design without using any additional wires if the design conforms to the pin assignments for the on-board 7-segment display. The figure below shows the 7-segment display with the conventional labeling of individual segments.

The Pegasus board contains a 6-digit common anode seven-segment LED display. The display is multiplexed, so only seven cathode signals (CA, CB, CC, CD, CE, CF, CG) exist to drive all 28 segments in the display. Six digit-enable signals (AN1, AN2, AN3, AN4, AN5, AN6) drive the common anodes, and these signals determine which digit the cathode signals illuminate.

LCD Interface
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SPARTAN-3 -IM includes a LCD Module, which is a dot matrix liquid crystal display that displays alphanumeric, Kana (Japanese) characters and symbols. Built in controller provides connectivity between LCD and FPGA. This LCD has a built in Dot Matrix controller, with font 5 X 7 or 5 X 10 dots, display data RAM for 80 characters ( 80 x 8 bit) and a character generator ROM which provides 160 characters with 5x7 font and 32 characters with font of 5x10. All the functions required for LCD are provided internally. Internal refresh is provided by the Controller.

Data Lines Connection LCD has 8 bit bidirectional data bus interface to FPGA. When Enable signal is at low level, this data bus remains in high impedance state. Interface details of the data lines with SPARTAN-3 FPGA are as in Table. Control Line Interface: The control lines of LCD comprises of RS, R/W# and E The significance of the above mentioned control signals is as follows: RS: Register select signal used to select Data register or a Command/Status register. High on RS selects the data register. Low on RS selects the Command/Status register. R/W#: Read/Write select control line. High on R/W # selects the read operation Low on R/W # selects the write operation. E: Enable signal used to enable or disable the data bus. Low on the enable signal puts the data bus into a high impedance state. High on the enable signal selects the data bus

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CONTROL BIT LCD_E LCD_RS LCD_RW_BAR Note: PR1 is used to adjust the contrast of LCD Display

FPGA PIN 168 171 169

ASCIICODE The ASCII code for 5x 7 LCD Display is given in Figure

Consolidated UCF for the Complete Board:

Clock and Reset net net net KEYS net net net net net net net net "RL<0>" "RL<1>" "RL<2>" "RL<3>" "SL<0>" "SL<1>" "SL<2>" "SL<3>" Loc= Loc= Loc= Loc= Loc= Loc= Loc= Loc= "p96"; "p95"; "p94"; "p85"; "p86"; "p87"; "p90"; "p93"; "CLK_4M" Loc= "CLK_OPT" Loc= "RESET" Loc= "p181"; "p180"; "p182";

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LCD Interface net net net net net net net net net net net "LCD_D<0>" "LCD_D<1>" "LCD_D<2>" "LCD_D<3>" "LCD_D<4>" "LCD_D<5>" "LCD_D<6>" "LCD_D<7>" "LCD_E" "LCD_RS" "LCD_RW_BAR" Loc= Loc= Loc= Loc= Loc= Loc= Loc= Loc= Loc= Loc= Loc= "p167"; "p166"; "p165"; "p162"; "p161"; "p156"; "p155"; "p154"; "p168"; "p171"; "p169";

Seven Segment Interface net net net net net net net net Display net net net net net net Input Switches net net net net net net net net net net "IL<0>" "IL<1>" "IL<2>" "IL<3>" "IL<4>" "IL<5>" "IL<6>" "IL<7>" "IL<8>" "IL<9>" Loc= Loc= Loc= Loc= Loc= Loc= Loc= Loc= Loc= Loc= "p57"; "p52"; "p51"; "p50"; "p48"; "p46"; "p45"; "p44"; "p43"; "p42"; "DIS<0>" "DIS<1>" "DIS<2>" "DIS<3>" "DIS<4>" "DIS<5>" Loc= Loc= Loc= Loc= Loc= Loc= "p97"; "p100"; "p101"; "p102"; "p132"; "p133"; "SEGA" "SEGB" "SEGC" "SEGD" "SEGE" "SEGF" "SEGG" "SEGDP" Loc= Loc= Loc= Loc= Loc= Loc= Loc= Loc= "p144"; "p143"; "p141"; "p140"; "p139"; "p138"; "p137"; "p135";

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net net net net net net Test LEDs net net net net net net net net net net net net net net net net RTC net net net net net net net net net net net net net net

"IL<10>" "IL<11>" "IL<12>" "IL<13>" "IL<14>" "IL<15>"

Loc= Loc= Loc= Loc= Loc= Loc=

"p40"; "p39"; "p37"; "p36"; "p35"; "p34";

"OL<0>" "OL<1>" "OL<2>" "OL<3>" "OL<4>" "OL<5>" "OL<6>" "OL<7>" "OL<8>" "OL<9>" "OL<10>" "OL<11>" "OL<12>" "OL<13>" "OL<14>" "OL<15>"

Loc= Loc= Loc= Loc= Loc= Loc= Loc= Loc= Loc= Loc= Loc= Loc= Loc= Loc= Loc= Loc=

"p68"; "p67"; "p65"; "p64"; "p63"; "p62"; "p61"; "p58"; "p80"; "p79"; "p78"; "p77"; "p76"; "p74"; "p72"; "p71";

"RTC_DIS<0>" "RTC_DIS<1>" "RTC_DIS<2>" "RTC_DIS<3>" "RTC_DIS<4>" "RTC_DIS<5>" "RTC_SEGA" "RTC_SEGB" "RTC_SEGC" "RTC_SEGD" "RTC_SEGE" "RTC_SEGF" "RTC_SEGG" "RTC_SEGDP"

Loc= Loc= Loc= Loc= Loc= Loc= Loc= Loc= Loc= Loc= Loc= Loc= Loc= Loc=

"p16"; "p15"; "p19"; "p18"; "p21"; "p22"; "p24"; "p20"; "p27"; "p26"; "p29"; "p28"; "p33"; "p31";

#J6-1 #J6-2 #J6-3 #J6-4 #J6-5 #J6-6 #J6-7 #J6-8 #J6-5 #J6-6 #J6-3 #J6-4 #J6-1 #J6-2

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Traffic Control net net net net net net net net net net net net net net net net net net net net net net net net net net net net "TRC_LE" "TRC_LN" "TRC_LS" "TRC_LW" "TRC_SE" "TRC_SN" "TRC_SS" "TRC_SW" "TRC_RE" "TRC_RN" "TRC_RS" "TRC_RW" "TRC_PEG" "TRC_PNG" "TRC_PSG" "TRC_PWG" "TRC_PER" "TRC_PNR" "TRC_PSR" "TRC_PWR" "TRC_REDE" "TRC_REDN" "TRC_REDS" "TRC_REDW" "TRC_YE" "TRC_YN" "TRC_YS" "TRC_YW" Loc= Loc= Loc= Loc= Loc= Loc= Loc= Loc= Loc= Loc= Loc= Loc= Loc= Loc= Loc= Loc= Loc= Loc= Loc= Loc= Loc= Loc= Loc= Loc= Loc= Loc= Loc= Loc= "p107"; "p125"; "p150"; "p130"; "p115"; "p123"; "p152"; "p146"; "p114"; "p122"; "p111"; "p147"; "p116"; "p128"; "p12"; "p148"; "p117"; "p124"; "p13"; "p149"; "p109"; "p120"; "p108"; "p126"; "p106"; "p119"; "p113"; "p131"; #J3-20 #J3-9 #J3-25 #J3-6 #J3-17 #J3-11 #J3-26 #J3-4 #J3-18 #J3-12 #J3-23 #J3-3 #J3-16 #J3-7 #J3-28 #J3-2 #J3-15 #J3-10 #J3-27 #J3-1 #J3-22 #J3-13 #J3-21 #J3-8 #J3-19 #J3-14 #J3-24 #J3-5

Result:

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Exp.No: 7 SIMULATION OF BACK ANNOTATED VERILOG FILES FOR Date: MULTIPLYING TWO SIGNED, 8-BIT NUMBERS IN 2'S COMPLEMENT Aim:
To design and simulate back annotated verilog files for multiplying two signed 8 bit numbers in 2s complement form and must be pipelined and completely RTL compliant. VHDL Code (VHDL Module) 4 bit Multiplier: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY multiplier IS port( clk: in std_logic; a,b: in std_logic_vector(3 downto 0); product: out std_logic_vector(9 downto 0)); end multiplier; architecture Behavioral of multiplier is signal cin: std_logic:=0; signal s1,s2,s3,s4: std_logic_vector(7 downto 0); signal a1,a2,a3,a4: std_logic_vector(7 downto 0); signal sum1: std_logic_vector(8 downto 1); signal sum2: std_logic_vector(8 downto 1); signal carry1: std_logic_vector(8 downto 1); signal carry2: std_logic_vector(8 downto 1); signal out1,out2: std_logic_vector(8 downto 0); signal sum2,carry3: std_logic_vector(9 downto 1); begin process(clk) begin if clk event and clk=1 then s1<=0000 & a; s2<=000 & a & 0; s3<=00 & a & 00; s4<=0 & a & 000; if b(0)=1 then a1<=s1; else a1<=00000000; end if; if b(1)=1 then a2<=s2; else a2<=00000000; end if;

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if b(2)=1 then a3<=s3; else a3<=00000000; end if; if b(3)=1 then a4<=s4; else a4<=00000000; end if; -----------------------------------------------------------------------------carry1(1)<=(a1(0) and a2(0)) or (a2(0) and cin) or (cin and a1(0)); carry1(2)<=(a1(1) and a2(1)) or (a2(1) and carry1(1)) or (carry1(1) carry1(3)<=(a1(2) and a2(2)) or (a2(2) and carry1(2)) or (carry1(2) carry1(4)<=(a1(3) and a2(3)) or (a2(3) and carry1(3)) or (carry1(3) carry1(5)<=(a1(4) and a2(4)) or (a2(4) and carry1(4)) or (carry1(4) carry1(6)<=(a1(5) and a2(5)) or (a2(5) and carry1(5)) or (carry1(5) carry1(7)<=(a1(6) and a2(6)) or (a2(6) and carry1(6)) or (carry1(6) carry1(8)<=(a1(7) and a2(7)) or (a2(7) and carry1(7)) or (carry1(7) out1<=carry1(8) & sum1; sum1(1)<=a1(0) xor a2(0) xor cin; sum1(2)<=a1(1) xor a2(1) xor carry1(1); sum1(3)<=a1(2) xor a2(2) xor carry1(2); sum1(4)<=a1(3) xor a2(3) xor carry1(3); sum1(5)<=a1(4) xor a2(4) xor carry1(4); sum1(6)<=a1(5) xor a2(5) xor carry1(5); sum1(7)<=a1(6) xor a2(6) xor carry1(6); sum1(8)<=a1(7) xor a2(7) xor carry1(7); -------------------------------------------------------------------------------carry2(1)<=(a3(0) and a4(0)) or (a4(0) and carry2(2)<=(a3(1) and a4(1)) or (a4(1) and carry2(3)<=(a3(2) and a4(2)) or (a4(2) and carry2(4)<=(a3(3) and a4(3)) or (a4(3) and carry2(5)<=(a3(4) and a4(4)) or (a4(4) and carry2(6)<=(a3(5) and a4(5)) or (a4(5) and carry2(7)<=(a3(6) and a4(6)) or (a4(6) and carry2(8)<=(a3(7) and a4(7)) or (a4(7) and out2<=carry2(8) & sum2; sum2(1)<=a3(0) xor a4(0) xor cin; sum2(2)<=a3(1) xor a4(1) xor carry2(1); sum2(3)<=a3(2) xor a4(2) xor carry2(2); sum2(4)<=a3(3) xor a4(3) xor carry2(3); sum2(5)<=a3(4) xor a4(4) xor carry2(4); sum2(6)<=a3(5) xor a4(5) xor carry2(5); sum2(7)<=a3(6) xor a4(6) xor carry2(6); sum2(8)<=a3(7) xor a4(7) xor carry2(7); cin) or (cin and a3(0)); carry2(1)) or (carry2(1) carry2(2)) or (carry2(2) carry2(3)) or (carry2(3) carry2(4)) or (carry2(4) carry2(5)) or (carry2(5) carry2(6)) or (carry2(6) carry2(7)) or (carry2(7)

and a1(1)); and a1(2)); and a1(3)); and a1(4)); and a1(5)); and a1(6)); and a1(7));

and a3(1)); and a3(2)); and a3(3)); and a3(4)); and a3(5)); and a3(6)); and a3(7));

----------------------------------------------------------------------------

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carry3(1)<=(out1(0) and out2(0) or (out2(0) and cin) or (cin and out1(0))); carry3(2)<=( out1(1) and out2(1) or (out2(1) and carry3(1)) or (carry3(1) and out1(1))); carry3(3)<=( out1(2) and out2(2) or (out2(2) and carry3(2)) or (carry3(2) and out1(2))); carry3(4)<=( out1(3) and out2(3) or (out2(3) and carry3(3)) or (carry3(3) and out1(3))); carry3(5)<=( out1(4) and out2(4) or (out2(4) and carry3(4)) or (carry3(4) and out1(4))); carry3(6)<=( out1(5) and out2(5) or (out2(5) and carry3(5)) or (carry3(5) and out1(5))); carry3(7)<=( out1(6) and out2(6) or (out2(6) and carry3(6)) or (carry3(6) and out1(6))); carry3(8)<=( out1(7) and out2(7) or (out2(7) and carry3(7)) or (carry3(7) and out1(7))); carry3(9)<=( out1(8) and out2(8) or (out2(8) and carry3(8)) or (carry3(8) and out1(8))); sum3(1)<= out1(0) xor out2(0) xor carry3(1); sum3(2)<= out1(1) xor out2(1) xor carry3(2); sum3(3)<= out1(2) xor out2(2) xor carry3(3); sum3(4)<= out1(3) xor out2(3) xor carry3(4); sum3(5)<= out1(4) xor out2(4) xor carry3(5); sum3(6)<= out1(5) xor out2(5) xor carry3(6); sum3(7)<= out1(6) xor out2(6) xor carry3(7); sum3(8)<= out1(7) xor out2(7) xor carry3(8); sum3(9)<= out1(8) xor out2(8) xor carry3(9); -------------------------------------------------------------------------product<=carry3(9) & sum3; ----------------------------------------------------------------------------end if; end process; end Behavioral;

Result:

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Exp.No: 8 Date: Aim:

DESIGN OF TRAFFIC LIGHT CONTROLLER USING VERILOG

To design and simulate Traffic Light Controller using Verilog module.

Design Description: Initially all Red Lights will be ON (South, west, North, East, Pedestrian) Green Lights of will be ON, Right, Left & Straight paths are free for Traffic. Yellow Phase is split as yellow1 & yellow2. In yellow1 phase yellow lights will be on and respective left & pedestrian paths are free for traffic. In Yellow2 Phase only yellow lights will be ON Same flow is repeated for all four paths. (South, West, North, East).

Verilog Module:
`timescale 1ns / 1ps module traffic_controller_verilog(clk, rst, ls, lw, ln, le, ss, sw, sn, se, rs, rw, rn, re, red_s, red_w, red_n, red_e, ys, yw, yn, ye, ps_r,pw_r,pn_r,pe_r,ps_g, pw_g, pn_g, pe_g, l_n, y_n, redn, png, l_w, y_w, redw, pwg, l_e, y_e, rede, peg, l_s, y_s, reds, psg); input clk; input rst; output ls,lw,ln,le; output ss,sw,sn,se; output rs,rw,rn,re; output red_s,red_w,red_n,red_e; output ys,yw,yn,ye; output ps_r,pw_r,pn_r,pe_r; output ps_g,pw_g,pn_g,pe_g; output l_n,y_n,redn,png ; output l_w,y_w,redw,pwg ; output l_e,y_e,rede,peg ; output l_s,y_s,reds,psg ; reg l_n,y_n,redn,png ; reg l_w,y_w,redw,pwg ; reg l_e,y_e,rede,peg ; reg l_s,y_s,reds,psg ; reg ls,lw,ln,le; reg ss,sw,sn,se; reg rs,rw,rn,re; reg red_s,red_w,red_n,red_e; reg ys,yw,yn,ye; reg ps_r,pw_r,pn_r,pe_r; reg ps_g,pw_g,pn_g,pe_g; reg [3:0]ps,ns; reg [30:0] div;

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reg [3:0] cnt; wire clk_s; parameter [3:0]start = 4'b0000; parameter [3:0]south_g = 4'b0001; parameter [3:0]south_orange = 4'b0010; parameter [3:0]south_r = 4'b0011; parameter [3:0]west_g = 4'b0100; parameter [3:0]west_orange = 4'b0101; parameter [3:0]west_r = 4'b0110; parameter [3:0]east_g = 4'b0111; parameter [3:0]east_orange = 4'b1000; parameter [3:0]east_r = 4'b1001; parameter [3:0]north_g = 4'b1010; parameter [3:0]north_orange = 4'b1011; parameter [3:0]north_r = 4'b1100; always@ (posedge clk or posedge rst) begin if (rst) div <= 2'b00; else div <= div + 1; end assign clk_s = div[20]; //***************************Counter************************ always@(posedge clk_s or posedge rst) begin if (rst) cnt <= 4'b0; else cnt <= cnt + 1; end //**************************Memory_logic******************** always@(posedge clk_s or posedge rst) begin if (rst) ps <= start; else ps <= ns; end always @(ps) case (ps) start : ns <= south_g; south_g: begin if(cnt == 10) ns <= south_orange; else ns <= south_g; end south_orange: begin if(cnt == 14) ns <= south_r; else

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ns <= south_orange; end south_r : begin if(cnt == 15) ns <= west_g; else ns <= south_r; end west_g : begin if(cnt == 10) ns <= west_orange; else ns <= west_g; end west_orange : begin if(cnt == 14) ns <= west_r; else ns <= west_orange; end west_r : begin if(cnt == 15 ) ns <= north_g; else ns <= west_r; end north_g : begin if(cnt == 10) ns <= north_orange; else ns <= north_g; end north_orange : begin if(cnt == 14) ns <= north_r; else ns <= north_orange; end north_r : begin if(cnt == 15) ns <= east_g; else ns <= north_r; end east_g : begin if(cnt == 10) ns <= east_orange; else ns <= east_g; end east_orange : begin if(cnt == 14)

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ns <= east_r; else ns <= east_orange; end east_r : begin if(cnt == 15) ns <= south_g; else ns <= east_r; end default : ns <= start; endcase //**********************Output_logic******************** always@(ps) begin red_s <= 0; red_w <= 0; red_n <= 0; red_e <= 0; redn <= 0; redw <= 0; rede <= 0; reds <= 0; rs <= 0; rw <= 0; rn <= 0; re <= 0; ss <= 0; sw <= 0; sn <= 0; se <= 0; ls <= 0; lw <= 0; ln <= 0; le <= 0; l_n <= 0; l_w <= 0; l_e <= 0; l_s <= 0; ps_g <= 0; pw_g <= 0; pn_g <= 0; pe_g <= 0; png <= 0; pwg <= 0; peg <= 0; psg <= 0; ys <= 0; yw <= 0; yn <= 0; ye <= 0; y_n <= 0;

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y_w <= 0; y_e <= 0; y_s <= 0; ps_r <= 0; pw_r <= 0; pn_r <= 0; pe_r <= 0; case (ps) start : begin red_s <= 1; red_w <= 1; red_n <= 1; red_e <= 1; redn <= 1; redw <= 1; rede <= 1; reds <= 1; end south_g : begin ls <= 1; l_s <= 1; rs <= 1; ss <= 1; le <= 1; l_e <= 1; red_w <= 1; red_n <= 1; red_e <= 1; redw <= 1; redn <= 1; rede <= 1; ps_r <= 1; pw_r <= 1; pn_r <= 1; pe_r <= 1; end south_orange : begin pn_g <= 1; png <= 1; le <= 1; ls <= 1; l_s <= 1; ys <= 1; y_s <= 1; red_w <= 1; red_n <= 1; red_e <= 1; redw <= 1; redn <= 1; rede <= 1; ps_r <= 1; pw_r <= 1;

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pe_r <= 1; end south_r : begin ls <= 1; l_s <= 1; red_w <= 1; red_n <= 1; red_e <= 1; ps_r <= 1; pw_r <= 1; pn_r <= 1; pe_r <= 1; end west_g : begin lw <= 1; ls <= 1; rw <= 1; sw <= 1; l_w <= 1; l_s <= 1; red_s <= 1; red_n <= 1; red_e <= 1; redw <= 1; redn <= 1; rede <= 1; ps_r <= 1; pw_r <= 1; pn_r <= 1; pe_r <= 1; end west_orange : begin lw <= 1; ls <= 1; l_w <= 1; l_s <= 1; pe_g <= 1; peg <= 1; yw <= 1; y_w <= 1; red_s <= 1; red_n <= 1; red_e <= 1; reds <= 1; redn <= 1; rede <= 1; ps_r <= 1; pw_r <= 1; pn_r <= 1; end west_r : begin lw <= 1;

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l_w <= 1; red_s <= 1; red_n <= 1; red_e <= 1; reds <= 1; redn <= 1; rede <= 1; ps_r <= 1; pw_r <= 1; pn_r <= 1; pe_r <= 1; end north_g : begin ln <= 1; l_n <= 1; rn <= 1; sn <= 1; lw <= 1; l_w <= 1; red_s <= 1; red_w <= 1; red_e <= 1; reds <= 1; redw <= 1; rede <= 1; ps_r <= 1; pw_r <= 1; pn_r <= 1; pe_r <= 1; end north_orange : begin ln <= 1; lw <= 1; l_n <= 1; l_w <= 1; ps_g <= 1; psg <= 1; yn <= 1; y_n <= 1; red_s <= 1; red_w <= 1; red_e <= 1; reds <= 1; redw <= 1; rede <= 1; pw_r <= 1; pn_r <= 1; pe_r <= 1; end north_r : begin ln <= 1; l_n <= 1;

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red_s <= 1; red_w <= 1; red_e <= 1; reds <= 1; redw <= 1; rede <= 1; ps_r <= 1; pw_r <= 1; pn_r <= 1; pe_r <= 1; end east_g : begin re <= 1; se <= 1; le <= 1; ln <= 1; l_n <= 1; l_e <= 1; red_s <= 1; red_w <= 1; red_n <= 1; reds <= 1; redw <= 1; rede <= 1; ps_r <= 1; pw_r <= 1; pn_r <= 1; pe_r <= 1; end east_orange : begin ln <= 1; le <= 1; l_n <= 1; l_e <= 1; pw_g <= 1; pwg <= 1; ye <= 1; y_e <= 1; red_s <= 1; red_w <= 1; red_n <= 1; reds <= 1; redw <= 1; rede <= 1; ps_r <= 1; pn_r <= 1; pe_r <= 0; end east_r : begin le <= 1; l_e <= 1; red_s <= 1;

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red_w <= 1; red_n <= 1; reds <= 1; redw <= 1; rede <= 1; ps_r <= 1; pw_r <= 1; pn_r <= 1; pe_r <= 1; end default : begin red_s <= 0; red_w <= 0; red_n <= 0; red_e <= 0; rs <= 0; rw <= 0; rn <= 0; re <= 0; ss <= 0; sw <= 0; sn <= 0; se <= 0; ls <= 0; lw <= 0; ln <= 0; le <= 0; ps_g <= 0; pw_g <= 0; pn_g <= 0; pe_g <= 0; ys <= 0; yw <= 0; yn <= 0; ye <= 0; ps_r <= 0; pw_r <= 0; pn_r <= 0; pe_r <= 0; l_n <= 0; l_w <= 0; l_e <= 0; l_s <= 0; png <= 0; pwg <= 0; peg <= 0; psg <= 0; y_n <= 0; y_w <= 0; y_e <= 0; y_s <= 0; redn <= 0;

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redw <= 0; rede <= 0; reds <= 0; end endcase end endmodule --******************************************************

Description of above Code: To Start the Traffic light controller 1. Initially the Red light of all the directions is ON. 2. Traffic starts from the South Direction; hence the green light of South direction goes ON. The signals that are ON, now are : ls ( left south ) -1. rs ( right south ) -1. ss ( straight south ) -1. le ( left east ) -1. red_w ( red west ) -1. red_n (red north ) -1. red_e (red east ) -1. ps_r ( pedestrian south red) -1. pw_r ( pedestrian west red) -1. pn_r ( pedestrian north red) -1. pe_r ( pedestrian east red) -1. Similarly when Orange light of South direction is ON then the signals that are ON, now are ls ( left south ) -1. ys ( yellow south ) -1. le ( left east ) -1. red_w ( red west ) -1. red_n (red north ) -1. red_e (red east ) -1. ps_r ( pedestrian south red) -1. pw_r ( pedestrian west red) -1.

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pn_r ( pedestrian north red) -1. pe_r ( pedestrian east red) -1. Similarly when Red light of South direction is ON then the signals that are ON, now are ls ( left south ) -1. red_w ( red west ) -1. red_n (red north ) -1. red_e (red east ) -1. ps_r ( pedestrian south red) -1. pw_r ( pedestrian west red) -1. pn_r ( pedestrian north red) -1. pe_r ( pedestrian east red) -1. During this time all ways are Blocked for 1 second except left south ( ls -1 ) and so on. After that it goes clockwise for all Direction (i.e.:- South then West then North then East) similarly.

Result:

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Exp.No: 9 Date:

TESTING THE TRAFFIC CONTROLLER DESIGN DEVELOPED IN SI. NO.8 ON THE FPGA BOARD

Spartan-3 FPGA development board, which is available in college, includes a TRAFFIC LIGHT Interface Module. This module is interfaced to the Trainer using 60 pin FRC cable. Traffic Light controller is implemented in FPGA and verified using Traffic Light Interface Module. There are simple rules for traffic lights on one node, and complex ways of regulating a whole infrastructure of them. It is necessary to adjust general algorithms. Design Description: Initially all Red Lights will be ON (South, west, North, East, Pedestrian) Green Lights of will be ON, Right, Left & Straight paths are free for Traffic. Yellow Phase is split as yellow1 & yellow2. In yellow1 phase yellow lights will be on and respective left & pedestrian paths are free for traffic. In Yellow2 Phase only yellow lights will be ON Same flow is repeated for all four paths. (South, West, North, East).

Flowchart:

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 To implement Traffic Light controller refer the waveform given below.

Abbreviation Used:
South PSG - Pedestrian South Green PSR - Pedestrian South Red RS - Right South LS - Left South SS - Straight South YS - Yellow South REDS - Red South North PNG - Pedestrian North Green PNR - Pedestrian North Red RN - Right North LN - Left North SN - Straight North YN - Yellow North REDN - Red North West PWG - Pedestrian West Green PWR - Pedestrian West Red RW - Right West LW - Left West SW - Straight West YW - Yellow West REDW - Red West East PEG - Pedestrian East Green PER - Pedestrian East Red RE - Right East LE - Left East SE - Straight East YE - Yellow East REDE - Red East

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Experimental Set up:

Component Diagram:

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Result:

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Exp.No: 10 Date:

DESIGN A REALTIME CLOCK AND DEMONSTRATE ITS WORKING ON THE FPGA BOARD

Aim: To implement Real Time Clock using Verilog HDL. Real Time Clock (Verilog Module)
//--This is real time clock in this we use //4mhz clock //to generate 1 sec clock we use enable signal high for last 1 count // sec1 counter for reading sec // sec2 counter for reading sec // min1 counter for reading min // min2 counter for reading min // hr1 counter for reading hr // hr2 counter for reading hr module finalclock_verilog(sgout,dis,hr2,hr1,min2,min1,sec1,sec2,load,tc1,tc2,tc3,tc4,tc5,tc6,enable,r eset,clock); output [3:0]sec1,sec2,min1,min2,hr1,hr2; output [7:0]sgout; output [5:0]dis; output tc1,tc2,tc3,tc4,tc5,tc6,enable; input reset,clock,load; reg [3:0]sec1_rg,sec2_rg,min1_rg,min2_rg,hr1_rg,hr2_rg; reg [21:0] pulsegen ; reg [2:0]cnk2; reg [3:0]mout; reg [7:0]sgout_rg; reg [5:0]dis_sig; //reg tc,tc1,tc2,tc3,tc4,tc5,tc6,enable; //reg sec1_rg(3:0),sec2_rg(3:0),min1_rg(3:0),min2_rg(3:0),hr1_rg(3:0); //reg hr2_rg(3:0),pulsegen(21:0),sel(2:0); //reg mout(3:0),sgout(7:0),ck1(22:0),cnk2(2:0); //*************************** Pulse Generator ****************** always@(posedge clock or posedge reset) begin if (reset) pulsegen <= 22'b0; else begin if (pulsegen == 22'b1111010000100100000000) pulsegen <= 22'b0; else pulsegen <= pulsegen + 1; end end //Enable signal to generate 1-sec pulse for sec1 counter assign enable = (pulsegen == 22'b1111010000100100000000) ; //enable signal for sec1 counter //************************ Second_cntr1 ************************* always@(posedge clock or posedge reset) begin if (reset ) sec1_rg <= 4'b0000; else if (load) begin

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sec1_rg <= 4'b0100; end else begin if (enable) begin if (sec1_rg == 4'b1001) sec1_rg <= 4'b0000; else sec1_rg <= sec1_rg + 1; end end end assign sec1 = sec1_rg; //------------------tc1 signal to start sec2 counter--------------------------assign tc1 = (sec1_rg == 4'b1001) && (enable == 1); //--************************* Second_cntr2 *********************** always@(posedge clock or posedge reset) begin if (reset ) sec2_rg <= 4'b0000; else if (load) begin sec2_rg <= 4'b0100; end else begin if (tc1) begin if (sec2_rg == 4'b0101) begin sec2_rg <= 4'b0000; end else begin sec2_rg <= sec2_rg + 1; end end end end assign sec2 = sec2_rg; //-------------------------tc2 signal to start min1 counter------------------assign tc2 = (sec2_rg == 4'b0101) && (tc1 == 1); //--************************ Minute_cntr1 ************************* always@(posedge clock or posedge reset) begin if (reset ) min1_rg <= 4'b0000; else if (load) begin min1_rg <= 4'b0100; end else begin if (tc2) begin if (min1_rg == 4'b1001)

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begin min1_rg <= 4'b0000; end else begin min1_rg <= min1_rg + 1; end end end end assign min1 = min1_rg; //------------------------tc3 signal to start min2 counter-------------------assign tc3 = (min1_rg == 4'b1001) && (tc2 == 1); //--************************ Hour_cntr1 ************************* always@(posedge clock or posedge reset) begin if (reset) min2_rg <= 4'b0000; else if (load) begin min2_rg <= 4'b0100; end else begin if (tc3) begin if (min2_rg == 4'b0101) begin min2_rg <= 4'b0000; end else begin min2_rg <= min2_rg + 1; end end end end assign min2 = min2_rg; //---------------------tc4 signal to start hr1 counter-------------------------assign tc4 = (min2_rg == 4'b0101) && (tc3 == 1); //--************************ Hour_cntr1 ************************* always@(posedge clock or posedge reset) begin if (reset) hr1_rg <= 4'b0000; else if (load) begin hr1_rg <= 4'b0001; end else begin if (tc6) begin hr1_rg <= 4'b0000; end else begin if (tc4)

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begin if (hr1_rg == 4'b1001) begin hr1_rg <= 4'b0000; end else begin hr1_rg <= hr1_rg + 1; end end end end end assign hr1 = hr1_rg; //---------------------tc5 signal to start hr2 counter-------------------------assign tc5 = (hr1_rg == 4'b1001) && (tc4 == 1); //------------------------tc6 signal to reset at 23:59:59-------------------------assign tc6 = (hr2_rg == 4'b0010) && (hr1_rg == 4'b0011) && (tc4 == 1); //--************************ Hour_cntr2 ************************* always@(posedge clock or posedge reset) begin if (reset) hr2_rg <= 4'b0000; else if (load) begin hr2_rg <= 4'b0000; end else begin if (tc6) begin hr2_rg <= 4'b0000; end else begin if (tc5) begin if (hr2_rg == 4'b0010) begin hr2_rg <= 4'b0000; end else begin hr2_rg <= hr2_rg + 1; end end end end end assign hr2 = hr2_rg; always@(posedge pulsegen[9] or posedge reset) begin if (reset) cnk2 <= 3'b0; else

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begin if (cnk2 == 3'b101) cnk2 <= 3'b0 ; else cnk2 <= cnk2 + 1; end end always@(cnk2) case (cnk2) 3'b000 : mout <= sec1; 3'b001 : mout <= sec2; 3'b010 : mout <= min1; 3'b011 : mout <= min2; 3'b100 : mout <= hr1; 3'b101 : mout <= hr2; endcase always@(mout) case (mout) 4'b0000 : sgout_rg <= 8'b11000000; 4'b0001 : sgout_rg <= 8'b11111001; 4'b0010 : sgout_rg <= 8'b10100100; 4'b0011 : sgout_rg <= 8'b10110000; 4'b0100 : sgout_rg <= 8'b10011001; 4'b0101 : sgout_rg <= 8'b10010010; 4'b0110 : sgout_rg <= 8'b10000010; 4'b0111 : sgout_rg <= 8'b11111000; 4'b1000 : sgout_rg <= 8'b10000000; 4'b1001 : sgout_rg <= 8'b10011000; endcase always@(cnk2) case (cnk2) 3'b000 : dis_sig <= 6'b111110; 3'b001 : dis_sig <= 6'b111101; 3'b010 : dis_sig <= 6'b111011; 3'b011 : dis_sig <= 6'b110111; 3'b100 : dis_sig <= 6'b101111; 3'b101 : dis_sig <= 6'b011111; endcase assign sgout = ~ sgout_rg; assign dis = ~ dis_sig; endmodule

Result:

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Possible University Practical Questions Verilog (Behavior & Dataflow Modeling) 1) Full Adder using 2 Half-Adders. 2) Full Adder using only NAND gates. 3) Full Adder using only NOR gates. 4) Full Subtractor using 2 Half-Subtractors. 5) Full Subtractor using only NAND gates. 6) Full Subtractor using only NOR gates. 7) D - Flip-Flop using +ive clock cycle. 8) D - Flip-Flop using -ive clock cycle. 9) T - Flip-Flop using +ive clock cycle. 10) T - Flip-Flop using -ive clock cycle. 11) D - Latch using positive enable. 12) D - Latch using negative enable. 13) T - Latch using positive enable. 14) T - Latch using negative enable. 15) S-R - Flip-Flop using +ive clock cycle. 16) S-R - Flip-Flop using -ive clock cycle. 17) J-K - Flip-Flop using +ive clock cycle. 18) J-K - Flip-Flop using -ive clock cycle. 19) 8:1 MUX 20) 16:1 MUX 21) 1:8 DEMUX 22) 1:16 DEMUX 23) 8:3 Encoder 24) 3:8 Decoder 25) 4:2 Encoder 26) 2:4 Decoder 27) Conversion of D to T Flip Flop function 28) Conversion of T to D Flip Flop function 29) Conversion of J-K to T Flip Flop function 30) Conversion of T to J-K Flip Flop function 31) Conversion of S-R to T Flip Flop function 32) Conversion of J-K to D Flip Flop function 33) Conversion of S-R to D Flip Flop function 34) Conversion of Binary to BCD converter. 35) Conversion BCD to Excess3. 36) Conversion Excess-3 to BCD code converter. 37) Conversion Binary to Gray Code converter. 38) Conversion Gray to Binary Converter. 39) Conversion BCD to Gray code converter. 40) Design a logic XOR gate using NAND gates only 41) Design a logic XNOR gate using NAND gates only 42) Design logic XOR gate using NOR gates only 43) Design logic XNOR gate using NOR gates only 44) 2 - bit Magnitude Comparator 45) 4 - bit Universal Shift Register (Behaviour Only) 46) 4 - bit Synchronous Counter (Behaviour Only) 47) 2 to 1 Multiplexer with Three-State Buffer (Dataflow only) 48) Traffic light controller for 4-way traffic. 49) Traffic light controller for 2-way traffic. 50) 4 - bit Pipeline parallel adder. 51) 2 - bit Pipeline parallel adder. 52) 8 - bit Multiplier

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[write the Program for the truth table] (UDP) 53) Realize the circuit using NAND gates: F(A,B,C,D) = (0,2,6,11,13,14) 54) Realize the circuit using NAND gates: F(A,B,C,D) = (0,1,2,3,4,6,12) 55) Realize the circuit using NOR gates: F(w,x,y,z) = (1,3,5,7,11,15) 56) Realize the circuit using NOR gates: F(w,x,y,z) = (0,2,4,6,7) 57) Realize the circuit: f = wxy+yz+wyz+xyz 58) Realize the circuit: g = (w+x+y+z)(x+y+z)(w+y+z) 59) Draw the logic diagram of the digital circuit for the following specifications and check the output in the FPGA board. module circuit(A,B,C,D,F); input A,B,C,D; output F; wire w,x,y,z,a,d; and (x,B,C,d); and (y,a,C); and (w,z,B); or (z,y,A); or (F,x,w); not(a,A); not(d,D); endmodule 60) Real Time Clock

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