VINAY MARUTI MELGIRI 2352 Champion Court, Raleigh, NC 27606 Email: vinay.melgiri@gmail.

com Ph: (919) 348-5094 OBJECTIVE: Seeking an internship opportunity for summer 2012 in the fields of Computer Architecture, ASIC Design/Verification. EDUCATION North Carolina State University, Raleigh, North Carolina. Current GPA: 3.8/4.0 Master of Science in Electrical and Computer Engineering Anticipated -Dec 2012 Relevant Coursework: Computer Design and Technology (Computer Architecture), Architecture of Parallel Computers, ASIC Design, Embedded Systems Design, Computer Networks and Wireless Networks. BVB College of Engineering, Hubli, India Aggregate: 76.3% Bachelor of Engineering in Electronics and Communications Engineering July 2009 Relevant Coursework: Computer Organization, Embedded systems, Digital signal processing, Logic Design, Analog Electronics, Digital VLSI design. WORK EXPERIENCE FREEDM Systems Center, NCSU Research and Laboratory Assistant Interfacing power electronics boards to DSP processor. FPGA programming of DSP processor (general purpose DSP TMS 320c6713B). Soldering of power electronics circuit PCBs. Robert Bosch Engineering and Business Solutions Ltd (RBEI) Embedded Engineer Implemented partial device driver for temperature sensor. Configurations of EEPROM, hardware pins, ADC, PWM. Developed multi packet frames in CAN protocol. Tasks on J1939 services implementation. Development of interfacing software for engine functionalities and engine management systems. TECHNICAL SKILLS Programming Languages: C, C++, x86 Assembly language, OpenMP. Scripting: C, Perl, Shell Scripting. HDL: Verilog, VHDL. EDA Tools: Xilinx ISE, Modelsim, ORCAD, CadSoft Eagle, Cadence Virtuoso, HSPICE, PSPICE. ACADEMIC PROJECTS Design and implementation of a packet forwarding engine in Verilog (In progress): Design and implementation of a packet forwarding engine in Verilog making use of fast address lookup technique while achieving minimum area. Multi Level Cache Simulator: Development of a Cache Simulator (with L-1, L-2 and Victim Caches) in C. Analysis ofmiss rates, average access times and EDP. Hardware Branch Predictor Simulator: Implemented a branch predictor simulator in C and modeled Bimodal, G-share and Hybrid branch predictors. Dynamic Instruction Scheduling: Implemented the Tomasulo's algorithm for Out of order (OOO) instruction execution. Integrated this simulator with the Instruction Cache to model the fetch from the cache. Implementation of Cache Coherency Protocols: Implementation of MSI, MESI and MOESI Coherence Protocols in C++ fora multiprocessor system.Modified the MOESI protocol to reduce the On-Chip Bandwidth usage by 60%. GUI based Wireless Blood Pressure Monitoring System using MSP430: Determined the optimum algorithm for acquisitionof BP values. Developed the interfacing software. Designed the PCB layout. (http://www.ti.com/ww/in/newsletter/UniTI_newsletter_V2_issue_3.pdf) HONORS AND ACTIVITIES Won 2nd place in Jack Kilby design and Debugging Contest at national level technical fest PLEIADES-2009. Participated in a workshop on Embedded software development on Beagleboard at IISC, Bangalore.

Dec 2011 - Present

Oct 2009 - May 2011