SARDAR RAJA COLLEGE OF ENGINEERING, ALANGULAM DEPARTMENT OF ELECTRONICS AND COMMUNICATION M.

E (APPLIED ELECTROINCS) SUBJECT NAME: ADVANCED DIGITAL SYSTEM DESIGN SUBJECT CODE: AP9212 YEAR/SEM: 1/1

UNIT 1 PART A 1. What is the difference between flowchart and ASM chart? 2. Distinguish between mealy and moore models.
3.

What do you mean by sequential circuit? Explain with the help of the block diagram.

4. Comparison between combinational and sequential circuits. 5. Mention the two types of synchronous sequential machine with example. 6. Compare Algorithmic state machine and finite state machine. 7. Draw the block diagram of a synchronous clocked sequential circuit.
8.

Show that the characteristic equation for the complement output of a JK flip flop is Q1(t+1) =J1Q1 + KQ

9. What are rules applied for the state reduction?

10. A

sequential network has an input x and output y and z. yz represents a

2bit binary number equal to the number that have been received an inputs. The network resets when the total number of 1s received is 3. Find a moore state graph for the network.

11.What is the use if ASM charts?

UNIT 1 PART B

1.

Construct a ASM block that has 3 input variables (A, B, C), 4 outputs (w,x,y,z) and 2 exit paths. For this block, output Z is always 1, and w is 1 if A and B are both 1. If c=1 and A=0, y=1 and exit path 1 is taken. If C=0 or A=1, X=1 and exit path 2 is taken.

2. Design a counter that counts pulses an line w and displays the count in the sequence. 0,2,1,3,0,2. Use D flip flop in your circuit. 3. Design a count with the following repeated binary sequence: 0,1,2,3,4,5,6. Use JK flip flop. 4. A sequential circuit has are flip flop Q two input x and y, and one output S. It consists of a full adder circuit connected to a D flip flop. Derive the state table and state diagram of the sequential circuit. What do you this circuit resoresent? 5. Using S R flip flop, design a parallel counter which counts in the sequence 000, 111, 110, 001, 010, 000. 6. Develop a block diagram and an ASM chart for a digital circuit that multiples two binary numbers by the repeated addition method.

UNIT -2 PART A

1. Define Hazards. 2. What is critical race and non critical race? 3. Explain state reduction procedure to generate reduced flow table from a primitive flow table. 4. Differentiate static and Dynamic Hazard. 5. Define fundamental mode operation of asynchronous sequential circuit. 6. Prove that dynamic hazard do not happen in two level AND OR circuit. 7. What are the advantages and disadvantages of are hot method assignments? 8. What are the situations the synchrmous networks unsuitable? 9. Write the types of Hazards? 10.Briefly explain about transition table in ASC? 11.Write short notes an static Hazard? 12.Write short notes an dynamic Hazard? 13.Write short notes an essential Hazard? 14.What is lock out condition? How it is avoided.

UNIT -2 PART - B 1. Explain static, dynamic and essential Hazards in digital circuit. Give Hazard free realization for the following Boolean function f (A, B, C, D) = m (2, 8, 5, 7, 10, 14) 2. Design an asynchronous sequential circuit with two Inputs x and y and with one output Z. Whenever y is 1. Input x is transferred to Z. When y is 0, the output does not change for any change in x. 3. An Asynchranous sequential circuit is described by the following excitation and output unction Y = x1 x2 + (x1+x2) y Z=Y i. ii. iii. Draw the logic diagram of the circuit Derive the transition table and output map. Describe the behavior of the circuit

4. Explain the Design procedure using stage table reduction method. 5. Find a circuit that has no static hazard and implements the Boolean function. F (A, B, C, D) + (0, 2, 6, 7, 8, 12) 6. The Boolean functions for the inputs of an SR latch are S= R= Obtain the circuit diagram using a minimum number of NAND gates.

UNIT - 3

PART - A

1. When a path is said to be sensitized? Define a tree like circuit. 2. What is D algorithm? 3. What are the advantages of using Boolean difference method over bath sensitization method? 4. What is the need for DFT in testing? 5. Define Reconvergent fan out? 6. Explain IDD Q test 7. Explain D calculus 8. What is s a o and s a i? 9. What is path sensitization method. 10.What is Fault table method?

UNIT - 3 PART B

1. Find a minimal complete test set for detecting all distinguishable single faults in the irredundant circuit shown below by the fault table method. x1 a x2 b3 x c d e x+ 4 z

2. Construct a complete test set of the circuit shown below by sensitizing its four paths. x1 x3 x2

3. Explain in detail about Built in self test method of testing digital circuits. 4. Discuss about the path sensitization and D algorithm for test vector generation 5. Determine the test vector for the logic circuit Z = (BC) 1 + B1 A which has a reconvergent fan out problem. 6. Find the all the (Input and output) faults of the following expression using fault table F1 = ab + aie 7. Find a minimum set of set of test that win test all single stuck at o and stuck at fault in the following expression. F = (abc + def + ghi) For each test, specify which faults are tested for s - a - 0 and s - a 1

UNIT - 4 PART - A

1. Draw the basic ROM structure. 2. Comparison between PROM, PLA and PAL. 3. Draw the block diagram of PLA. 4. Draw the logic construction of 64 x 4 ROM. 5. Explain the method of implementing logic circuit in PLA. 6. Explain the method of implementing logic circuit in PAL. 7. Explain the method of implementing logic circuit in FPGA. 8. Difference between synchronous sequential circuit and asynchronous sequential circuit. 9. Compare combinational and sequential circuit.

UNIT - 4 PART - B

1. Draw and Explain X1 LINX 4000 series FPGA. 2. Implementation the following Boolean functions using PAL. W (A, B, C, D) = m (0, 2, 6, 7, 8, 9, 12, 13) X (A, B, C, D) = m (0, 2, 6, 7, 8, 9, 12, 13, 14) Y (A, B, C, D) = m (2, 3, 8, 9, 10, 12, 13,) Z (A, B, C, D) = m ( 1, 3, 4, 6, 9, 12, 14)

3. Design a BCD to excess 3 code convertors and implement using suitable PLA. 4. Realize the function gives using a PLA with 6 inputs, 4 outputs and 10 AND gates. F1 (A, B, C, D, E, F,) = m (0, 1, 7, 8, 9, 10, 11, 15, 19, 23, 27, 31, 32, 35, 39, 40, 41, 47, 63) F2 (A, B, C, D, E, F,) = m (8, 9, 10, 11, 12, 14, 21, 25, 27, 40, 41, 42, 43, 44, 46, 57, 59) 5. Draw a PLA circuit in implement the functions. F1 = A1B + AC1 + A1 BC1 F2 = (AB + AC + BC) 1 6. Draw and explain the architecture of xilinx FPGA. 7. Explain the architecture of PLA. 8. Implement the following functions in FPGA. F1 (A, B, C, D, E) = (0, 5, 7, 20, 23, 25, 31)

F2 (W, X, Y, Z) = (2, 4, 8, 11, 13, 15)

UNIT 5 PART A 1. What is the role of test bench in HDL language? 2. How do you declare two dimensional array in VADL? 3. List the VHDL operators with suitable examples. 4. Differentiate signals and variables in VHDL programming. 5. Develop a behavioral model of the two to one line multiplener.
6.

What is the value of E in the following HDL block, assuming that RA = 1? RA = RA-1; If (RA = 0) E = 1; else E = 0

7. Develop a structural model of the two to one line multiplexer. 8. Develop a behavior model of the half adder. 9. Develop a behavior model of the full adder. 10.Difference between mux and decoder. 11.Comparison between serial adder and parallel adder. 12.What are the advantages using package? 13.Write short notes an concurrent VHDL? 14.What are the different types of test bench in VHDL for simulating a module.

UNIT 5 PART B 1. Write a VHDL program for 8 bit counter using D flip flop. 2. Write a VHDL program for 4 bit ripple carry adder using structural description? (Use basic gates AND, OR, XOR . etc) and also write test bench program. 3. Explain the concurrent and sequential statements in VHDL programming each with syntax and example. 4. Write the VHDL code for the following specification: i. ii. A counter that has a count sequence 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2,. 4 bit shift register with a control knob, K. if K = 1 then the register shifts data right and if K = 0 the register shifts the data left.

5. Write the HDL behavioral and structural descriptions of a Four bit register with parallel load and asynchronous clear. 6. Using a case statement, develop a behavioral model of one 8 - 4 - 2 - 1 to BCD code converter.