NDSU

Lead Compensator Design Using Root Locus

ECE 461

Lead Compensator Design Using Root Locus Techniques

Objectives:
To be able to Design a lead compensator to speed up the closed-loop system Provide a circuit to implement compensators

Background:
Assume a feedback system of the following form:
UR Y K
Compensator "prefilter"

G
Plant "filter"

A lead compensator is a prefilter of the form:

K(s) = k s+a s+b

b>a

The idea behind a lead compensator is as follows. Given a system, G(s), you have a corresponding root locus plot. The root locus plot tells you how fast you can make the system using gain compensation (see the previous lecture notes). If you could shift the root locus left, you could get a faster closed-loop system. Typically, there is a (stable) pole which is causing you problems: it pushes the root locus plot to the right, limiting the response of the system. If you could cancel this stable pole and move it further left (faster), the root locus plot would shift left. This lets you speed up the system.

Example: Design a lead compensator that results in a damping ratio of 0.5 for the following system:
20 G(s) = s(s+2)(s+5)

Step 1: Pick the form of K(s): The pole at -2 is causing problems and pushes the root locus to the right. If you could cancel this pole and move it out ot -20, you'd have a better system. So, let
s+2 K(s) = k s+20

This results in the open-loop system being

JSG

rev October 5, 2007

NDSU

Lead Compensator Design Using Root Locus

ECE 461

20(s+2)k 20k GK = s(s+2)(s+5)(s+20) s(s+5)(s+20)

Once the form of K(s) is specified, the selection of 'k' is just like before: Step 2: Sketch the root locus of the compensated system

Step 3: Pick a point on the root locus which satisfies the design criteria: The point on the root locus plot which intersects the 0.5 damping ratio line is

s = 2.000 + j3.4641
Step 4: Find k to place the closed-loop poles here:

(GK) s=2+j3.4641 = 1 k = 16.80

Step 5: Complete K(s)
s+2 K(s) = 16.80 s+20

Step 6: Describe how the closed-loop system will respond: Ts =2 seconds (if was 5.60 seconds using only gain compensation) No error for a step input (it's still a type-1 system)

K v = (sGK) s=0 = 3.360 (it was 1.1370 with gain compensation)

JSG

rev October 5, 2007

NDSU

Lead Compensator Design Using Root Locus

ECE 461

Note that the lead compensator sped up the system and reduced the stead-state error.

Step 7: Design a circuit to implement K(s):

C R1

R2

Let R1 = 1M
R At s , K(s) = 16.80 = R 1 . R 3 = 59.5k
3

At s 0, K(s) = 1.68 =

R1 R 2 +R 3

. R 2 = 535.7k
2

1 The zero tells you where C starts to short out R2: R C = 2 . C = 0.9333F

Problem: Design a lead compensator to speed up the system

336 G(s) = s(s+5)(s+20)

which results in a damping ratio of 0.5. (note: this is the same as adding a second lead compensator to speed up the system from before. You might do this if a settling time of 2 seconds was too slow).

Solution: Step 1: Pick the form of K(s): The pole at -5 is causing problems and pushes the root locus to the right. If you could cancel this pole and move it out to -50, you'd have a better system. So, let
s+5 K(s) = k s+50

This results in the open-loop system being

336k GK = s(s+20)(s+50)

Once the form of K(s) is specified, the selection of 'k' is just like before: Step 2: Sketch the root locus of the compensated system

JSG

rev October 5, 2007

NDSU

Lead Compensator Design Using Root Locus

ECE 461

Step 3: Pick a point on the root locus which satisfies the design criteria: The point on the root locus plot which intersects the 0.5 damping ratio line is

s = 7.1429 + j12.3718
Step 4: Find k to place the closed-loop poles here:

(GK) s=7.1429+j12.3718 = 1 k = 33.84

Step 5: Complete K(s)
s+5 K(s) = 33.84 s+50

Step 6: Describe how the closed-loop system will respond: Ts =0.56 seconds (if was 2 seconds previously) No error for a step input (it's still a type-1 system)

K v = 11.37 (it was 3.36)

Again, the lead compensator sped up the system and reduced the stead-state error.

JSG

rev October 5, 2007

NDSU

Lead Compensator Design Using Root Locus

ECE 461

Step 7: Design a circuit to implement K(s):

C R1

R2

Let R1 = 1M
R At s , K(s) = 33.84 = R 1 . R 3 = 29.6k
3

At s 0 , K(s) = 3.384 =

R1 R 2 +R 3

. R 2 = 266k
2

1 The zero tells you where C starts to short out R2: R C = 5 . C = 0.7519F

JSG

rev October 5, 2007