PULSE

EEWeb

Issue 52 June 26, 2012

EEWeb.com

Beth Cooper

NASA Glenn Research Center

Electrical Engineering Community

EEWeb
Electrical Engineering Community
Contact Us For Advertising Opportunities

advertising@eeweb.com www.eeweb.com/advertising

1.800.574.2791

TA B L E O F C O N T E N T S
Beth Cooper
NASA GLENN RESEARCH CENTER
Interview with Beth Cooper - NASA Internal Agency Hearing Conservation Consultant

4 9 12 14 20 26 29
Visit www.eeweb.com

TABLE OF CONTENTS

The Development of NASA Auditory Demonstrations Laboratory for Testing of Hearing Protection Devices
BY JEFF SCHMITT, BETH COOPER AND DAVID NELSON

Featured Products Why Cant Johnny Design? Part 1

BY TOM LEE WITH QUANSER
Examining the teaching methods of the modern day engineering curriculum and the challenges that engineering students face in the industry.

TDR: Reading the Tea Leaves

BY MIKE STEINBERGER WITH SISOFT
A review of the basic techniques for interpreting time domain reflectometry -- an essential technique for analyzing measured S parameters.

Your Clocks, My Layout

BY BILLIE JOHNSON WITH ON SEMICONDUCTOR
A clock tree synthesis primer that is key to understanding how to tackle advanced clocking requirements and strategies

RTZ - Return to Zero Comic

EEWeb | Electrical Engineering Community

INTERVIEW

Co per
Beth
How did you get into engineering and when did you start? I became involved in engineering through acousticsthe science of sound. When I was a child, I guess you could say that I had some musical talent. I was able to pick out melodies on the piano at a young age, and I taught myself to play several musical instruments. As I got older, I would write harmonies for tunes that I learned in school or camp. This interest propelled me into an involvement in music, and that was how I spent most of my time in high school. The focus of many school projects was the science of music studying how it was produced and why people perceived music the way they did. I was especially interested in the relationships between sounds, which is one aspect of the discipline of music theory. When I started to apply to colleges I very nearly became a music theory major. It wasnt until the very last minute that I realized that there was a name for what I really liked, which was the physics of musicintervals, tones, and those kinds of things. The technical field that encompasses all of that is acoustics. So, to find a college, I did what, today, would be an Internet searchI went to the libraryand found that there were four schools in the country that offered undergraduate programs in acoustics, one of them being the University of Hartford. The program there was a Bachelor of Science in Engineering (B.S.E.) program in Acoustics and Music. Students in this program took most of the same coursework as a music performance major at the conservatory, Hartt College of Music, as well as the core coursework of an engineering major. It sounded like the perfect program for me, so thats what I did. For the first two years of my college education I was a double major in music and acoustics. I eventually switched my major to mechanical engineering, only because the B.S.E. program at that time was not accredited, and I didnt want to have any concerns about the validity of my degree while job hunting later. But I still took all the same courses over and

FEATURED INTERVIEW

NASA Glenn Research Internal Agency Hearing Conservation Consultant

above what was required for my B.S.M.E. degree, so I also earned the equivalent of a B.S.E. in Music and Acoustics. From there I went on to Penn State because it had the most acclaimed program in the country that awarded graduate degrees in acoustics. The program was very broad: it covered everything from underwater acoustics to speech science and audiology. I had hoped to study musical acoustics, but I needed to focus on an area where there was ample funding for assistantships. I modified my academic approach to emphasize speech science and speech processing, which was probably about as close as I could get to musical acoustics. The connection is really human perception, which links speech and hearing sciences to musical acoustics. So its not hard to imagine the link between that and being a hearing conservationist, which is what I am now. Where did you first go to work after you graduated? I worked in private industry for about

EEWeb | Electrical Engineering Community

Visit www.eeweb.com

INTERVIEW
four years, but it wasnt what I really wanted to do, since my ambition was always to work for the government in a research capacity. It took a while to get an acoustics position at NASA, but as soon as I heard there was an opening at Glenn Research Center in Cleveland, thats where I went. Ive worked here for nearly my entire professional careerabout 25 years. Can you tell us about what you do at NASA? Since Ive been at NASA Ive had four major assignments, each lasting from about five to seven years. My first assignment was on a team doing research on the noise produced by jet nozzles from aircraft exhaust engines. The program included both analytical and experimental research; the work I was doing specifically involved testing scale models of exhaust nozzles in wind tunnels and other laboratories. As a typical researcher in a wind tunnel, you have a fairly cyclic work routine. You take data, analyze the data, then write a paper and go to a conference to present your work. But because I had a slightly different interest area than most of the other people in my group, I was asked if I would take a look at a community noise problem that had developed with one of our test facilities, where researchers were doing aircraft engine component testing in an open parking lot. Obviously, it was generating a lot of noise, and since the testing was being done during third shift to save money on power, some residents of the nearby communities had begun to regularly call and complain. It had become a pretty significant community noise issue that was threatening the success of the research program, and so my boss said, We know that human perception of sound is one of your interests, so will you take a look at what we can do to solve this problem? One thing led to another, the noise from reverberating inside the dome; this allows the space to be used for noise emission measurements on various aircraft components. After leading the acoustical design and managing the construction of this facility, I realized that I didnt want to go back to being a researcher. I really enjoyed facility design and noise control, and I had, at that point, developed a bit of a reputation as a noise control person, leading me to take on other smaller noise control-related tasks. Eventually, I knew I wanted to continue working on noise control projects, which inspired me to find my next home in the Health and Safety organization. During my interview for that position, the person interviewing mewho would eventually become my bosssaid, We would love to have you work on noise control, but its really just one element of a hearing conservation program and needs to be approached that way. Would you like to manage the hearing conservation program? So I did that from about 1994 to 1999, establishing the hearing conservation program here at NASA Glenn Research Center. It ended up being a very high-quality program, and I think that is partly because there was a significant emphasis on noise control, which typically gets neglected in the context of a classical program. As part of that assignment, I implemented an aggressive campaign of noise control solutions for our test facilities and infrastructure buildings. I also developed a number of novel programs that NASA has since

FEATURED INTERVIEW

Over the span of my career, I have come to be acknowledged as NASAs noise person, and now my responsibility is to advise our senior environmental health officer and the occupational health personnel at our field centers about noise exposure issues, particularly related to noise control and hearing conservation program policies.
and we ended up building a geodesic-dome-shaped enclosure that severely reduced the noise that could be heard in the surrounding community. The facility also has an anechoic interior lining that keeps

EEWeb | Electrical Engineering Community

Visit www.eeweb.com

INTERVIEW
adopted on an agency-wide basis. By 1999 the Glenn hearing conservation program was mature and had developed a lot of momentum, so I started looking for a new challenge. Just like in my previous assignment, I realized that one capability we needed, but didnt have, was an anechoic chamber dedicated to performing smallscale testing of equipment destined for the International Space Station. All flight hardware is required to go through a series of qualification tests. One of those tests verifies that the equipment doesnt make too much noise, with the goal of preventing hearing loss as well as ensuring a comfortable working environment for the astronauts. Payload developers here at NASA Glenn were always looking for quiet places where they could take the required noise measurements on their science payloads to get them qualified for flight. It was pretty clear that we needed a proper test facility to do that, so I proposed to the engineering organization that I come and work for them and help build one. It took about a year to find funding to build the chamber, but another year later, we opened a commercially viable state-of-the-art anechoic test laboratory that was specifically designed to accommodate a couple of major projects that were planned for the International Space Station. I led the facility design and managed the construction project and then became the manager of the lab. The lab provided acoustic emissions testing services, but we also developed and provided other related services, like low-noise design consulting and education for payload developers on how to design low-noise flight hardware. This acoustic emissions testing laboratory later earned accreditation by the National Voluntary Laboratory Accreditation Program for the tests we performed; we also became the only laboratory accredited for the specific test required for acoustic emissions verification of large flight racks for the International Space Station. Over the span of my career, I have come to be acknowledged as NASAs noise person, and now my responsibility is to advise our senior environmental health officer and the occupational health personnel at our field centers about noise exposure issues, particularly related to noise control and hearing conservation program policies. My fourth major assignmentthe work that Im primarily involved in right nowis focused on developing programs and resources for helping employees identify and purchase equipment that is inherently quiet. This approach also has a component that requires our in-house designers to design equipment and systems that are quiet. It makes good economic sense to avoid being in a situation where you are spending money to fix pre-existing noise problems while purchasing and building new equipment that may produce the very same problems. Noise emissions should be considered along with other criteria when youre purchasing or designing equipment. This is the essence of a Buy-Quiet program, and NASAs is leading the way in the United States. Do you have any tips for electronics hardware designers regarding noise? Electronic components dont usually contribute much noise themselves.

FEATURED INTERVIEW

EEWeb | Electrical Engineering Community

Visit www.eeweb.com

INTERVIEW
But if you have to provide cooling or ventilation for a piece of equipment youre designing, you should think about those requirements at the earliest possible stage of the design process to avoid creating unnecessary noise that then requires the addition of noise control treatments that will consume space and may create other problems for your design. Often, the worst noise problems are the result of airflow issues. Anything that restricts airflow or causes very sharp turns or bends in the airflow path is going to cause noise. This noise is very hard to get rid of after the fact, but it can be largely prevented if the challenge is addressed early enough in the design. Another piece of advice for designers is to be very explicit and intentional in demanding low-noise-emission products from manufacturers. NASA has developed a tool for Buy Quiet Purchasing called the Buy Quiet Roadmap. Basically, the Roadmap is an online process that helps end users identify an appropriate noise emission criterion for a particular item to be purchased and then to evaluate the total long-term cost of different manufacturers products that may differ in both cost and noise emission. The heart of the Roadmap is a calculation that quantifies the total long-term cost of occupational exposure to various noise levels. Its the only tool of its kind, and it has been commended by the Occupational Safety and Health Administration (OSHA) and the National Institute for Occupational Safety and Health (NIOSH) as well as international regulatory agencies, and it has been adopted by a number of organizations in the private sector. The Roadmap, as well as a number of other free and publicly available NASA resources that support hearing loss prevention, can be accessed here. I am a strong advocate of Buy Quiet Purchasing, and I encourage people to use this resource. What are some of the tools and approaches that you use when diagnosing noise problems? Its important to look at the both the frequency spectrum and the temporal characteristics of the sound, not just the volume (how loud the sound is), because the quality of the sound is very important to human perception, especially when it comes to providing a work environment that will be comfortable and foster productivity. NASAs noise emission and noise exposure limits are based on volume, but even if we satisfy those requirements, there can still be tones, hissing, rumbling or intermittent events that attract attention and cause discomfort and annoyance. A piece of equipment can produce an acceptable volume of sound, but if the spectrum has a significant high or low frequency component or one or more tones, it will likely be perceived as annoying or distracting. For this reason, you have to look at the entire spectrum as well as how it varies with time. This approach, which considers the sound quality, is more comprehensive and considers human factors that are not accommodated by the classical approach that addresses only the volume of the noise emission.

FEATURED INTERVIEW

EEWeb
Electrical Engineering Community

Join Today
www.eeweb.com/register
EEWeb | Electrical Engineering Community Visit www.eeweb.com

Avago Technologies Optocoupler Solutions

2 Times Faster, 50% Smaller, True Rail-to-Rail Output Voltage IGBT Gate Drives
in IGBT Gate Drive technology solutions IGBT/MOSFET Gate Drive introduces our Next Generation series!

Applications Avago Technologies, an industry leader

Benefits
Suitable for wide range of IGBT class for different market applications High output peak current for fast and efficient IGBT operation Rail-to-rail output voltage for reliable IGBT operation Lower system power budget Suitable for bootstrap power supply operation Reduce dead time and improve system efficiency Prevent erroneous driving of IGBT in noisy environment 40%-50% smaller than DIP package for space and cost savings To request a free evaluation board go to:

AC and Brushless Based on BCDMOS technology Avago can DC Motor Drives deliver higher peak output current, better railRenewable Energy Inverters Industrial Inverters Switching Power Supplies
to-rail output voltage performance and faster speed than previous generation products. The increased drive and speed along with the very high CMR (common mode rejection) and isolation voltage will enable you to build more efficient and reliable motor drive and power conversion systems. In addition the SO6 package which is up to 50% smaller than conventional DIP packages facilitates smaller more compact design.

www.avagotech.com/optocouplers

The Development of NASA Auditory Demonstrations Laboratory for Testing of Hearing Protection Devices
Editors Note: The following article is a synthesis of two separate papers written by members of the ADL development team and arranged by an EEWeb editor [1] [2]. Each paper can be accessed in the References section. Development of REAT Facility The development of the REAT test facility began in the fall of 2007. The primary goals of this project were to design

his article will outline the design of NASAs Auditory Demonstration Laboratory (ADL) for performing Real Ear Attenuation at Threshold (REAT) measurements to meet industry standards for the Noise Reduction Rating (NRR) of personal hearing protective devices. The calculation of an NRR implies highly specific test requirements for the conditions in the room in which the test is conducted, the signal generation equipment and the processing of normal hearing subjects. This article will also profile the development of NASAs REATMaster software as well as its key features that will aid in signal generation and data acquisition for all REAT testing facilities in which the system is employed.

Figure 1: NASA GRC Auditory Demonstration Laboratory control room with NASA REATMaster and Stimulus Presentation Sound System Rack (left) and Auditory Demonstrations Rack (right).

EEWeb | Electrical Engineering Community

Visit www.eeweb.com

PROJECT
The site for the ADL was chosen in the basement of a building with ideal conditions for conducting low-noise acoustic measurementsconcrete walls, a roof cap and heavy steel doors. A pre-fabricated ETS-Lindgren steel reverberant test chamber was installed in the basement laboratory to ensure a diffuse sound field environment. Both the test chamber and isolation within the basement provided optimal sound isolation levels at relevant test frequencies with the addition of several massive silencer units to reduce external effects on the testing. With the establishment of an isolated and secure ADL chamber came the need for the proper sound system to perform the signal generation tests. The sound system would need to create diffuse field sound pressure levels to allow REAT testing and provide stable gain and high slew rate output throughout. With these specifications, it would also need to operate quietly when operated at full gain while at the same time attenuating any systemgenerated noises. For the ADL, we implemented a threechannel system, utilizing ElectroVoiceT251 horn loaded loudspeakers that are driven by a Bryston 6BSST power amplifier. This amplifier delivers 300 watts per channel, more than 110 dB of signal to noise ratio and has a fixed gain input setting that facilitates system calibration. This system also employs a high-power 30 dB L-pad load box attenuator that achieves the desired low background noise levels needed for testing. If very high sound levels are needed, the L-pad attenuator can be removed. For the signal generation and data acquisition technology in the ADL, we selected the National Instruments PXI platform. We used two NI PXI-4461 dual-input, dualoutput, 24-bit digital dynamic signal acquisition (DSA) and generation modules, which provided three channels of signal generation and uncorrelated outputs needed to drive the sound system, and one to four input channels for sound pressure level monitoring and measurement. For detection of subject response, via a variety of response switch options, we used a National Instruments PXI6220 digital I/O board with a custom response switch interface. NASA REATMaster Software The NASA REATMaster software was developed by Nelson Acoustics to provide the ADL with a software application that would conduct calibrated real ear attenuation at threshold (REAT) measurements using the

FEATURED PROJECT

Figure 2: Interior View of NASA GRC Auditory Demonstrations Laboratory REAT Test chamber, showing diffusing panel, intercom speaker system and subject instruction video display.

Figure 3: The fabric panels in the ADL test chamber are removed from the test chamber when it is used for REAT testing. The fabric panels add the absorption needed to make the chamber convertible for use in presenting auditory demonstrations using the secondary audio sound system.

an acoustic test chamber and signal generation system for REAT testing in accordance with industry standards. In order that the human test subject receive accurate data from signal generations, the laboratory needed to have very low background noise levels to accommodate the hearing of a normal hearing subject. At the same time, it needed to be equipped with a sound system capable of generating spacecraft launch-level sound fields to test the performance of the hearing protection technology.

EEWeb | Electrical Engineering Community

Visit www.eeweb.com

10

PROJECT
National Instruments hardware. National Instruments LabView is the programming language used in the signal generation, user interface, system calibration and test automation software. REATMaster allows flexible configuration of system hardware for one to four channels of signal generation and provides system calibration tools that allow for both level and frequency calibration of each channel. It has a manual operating mode that supports system function verification, calibration and subject training, yet also has an automated thresholdseeking feature. All of the audio files produced by signal generations are in WAV format, and all of the threshold data can be exported to Microsoft Excel spreadsheets for post-process analysis. On completion of the test chamber and equipment installation and software development phases of the project, the entire system was calibrated and qualified per the requirements outlined in ANSI S12.6. Using a GRAS 40AQ random incidence microphone and the analog inputs on the National Instruments Digital Signal Analysis boards, the Nelson Acoustics Trident acoustic measurement application was used to conduct the level calibration and frequency equalization of the sound system. The diffuse sound field properties of the chamber were evaluated for sound pressure level uniformity and directionality at the location of the subjects head. ANSI S12.6 outlines a measurement procedure and criteria for these parameters, with the intent being the creation of a very uniform and highly omni-directional sound field in the region surrounding the subjects head so as to minimize the measurement uncertainty associated with the hearing protector attenuation as a result of uncertainties in the measurement presented to the subject. The NASA GRC ADL REAT and hearing protector test systems have been successfully designed, installed, and qualified to the ANSI S12.6 test method for measuring the real-ear attenuation of hearing protectors. The NASA REATMaster software development project resulted in a software tool that the ADL and other qualified hearing protection laboratories can employ using industry standard computer-based digital signal generation and data acquisition hardware. The system is currently being used at NASA GRC, the National Institute for Occupational Safety and Health (NIOSH), the U.S. Army Aeromedical Research Laboratory, and several commercial hearing protector evaluation laboratories in the US and internationally. References [1] Jeff Schmitt, Beth Cooper and David Nelson. The Development of NASA Auditory Demonstrations Laboratory for Measurement of Real Ear Attenuation of Hearing Protection Devices. NOISE-CON 2010, 1921/04/2010. <http://buyquietroadmap.com/wp-content/ uploads/2010/08/NASA_ADL_Hearing_Protector_Lab_ Schmitt_NoiseCon_10.pdf> [2] Jeff Schmitt. NASA Auditory Demonstration Laboratory Uses LabVIEW and PXI to Test Hearing Protection Devices. . National Instruments, n.d. Web. <http://sine.ni.com/cs/app/doc/p/id/cs-12552>

FEATURED PROJECT

EEWeb
Electrical Engineering Community

Join Today
www.eeweb.com/register
EEWeb | Electrical Engineering Community Visit www.eeweb.com

11

F E AT U R E D P R O D U C T S
New Super Junction MOSFETs
Renesas Electronics Corporation (TSE: 6723), a premier supplier of advanced semiconductor solutions, today announced the availability of three new super-junction metal-oxide-semiconductor field-effecttransistors (Super Junction MOSFETs) (Note 1) featuring figure of merit: on-state resistance x gate change in a 600 V power semiconductor device suitable for high-speed motor drives, DC-DC converters, and DC-AC inverter applications. This ultra low on-state resistance and low gate charge combination benchmark, combined with the fast body diode feature, allow the new RJL60S5DPP RJL60S5DPK and RJL60S5DPE , devices to contribute to improved power efficiency in home appliance motor drives, such as for air conditioners, that employ high-speed motors with inverterized control. For more information, please click here.

FEATURED PRODUCTS

Multilayer Ceramic Capacitors with High Q

Vishay Intertechnology, Inc. introduced a new series of surface-mount multilayer ceramic chip capacitors (MLCCs) offering high selfresonance, a high Q factor of 2000, and a low dissipation factor of 0.05 % for operation in high-frequency commercial applications. With their low dissipation factor, devices in the VJ HIFREQ series are optimized for filter and matching networks, and amplifier and DC blocking circuits. The MLCCs reduce signal loss and energy consumption in power amplifier modules, VoIP networks, cellular base stations, GPS systems, and satellite, WiFi (802.11), and WiMAX (802.16) wireless communication. For more information, please click here.

Aerospace Grade Contactors

KILOVAC CAP202 Series contactors from TE Connectivity (TE) are two-pole, single-throw devices capable of handling 350 A per pole voltage range of 12 to 900 Vdc. The contactors are designed for flexible application in high-voltage dc converter systems, test equipment, power distribution, and power motion control. Because the main contacts are not polarity sensitive, bidirectional switching is enabled. In addition, the devices are not position sensitive and can be mounted in any orientation. Up to four optional single-pole, double-throw auxiliary switch outputs support 2 A at 30 Vdc or 5 mA at 6 V for signals. For more information, please click here.

EEWeb | Electrical Engineering Community

Visit www.eeweb.com

12

EEWeb
Electrical Engineering Community
Contact Us For Advertising Opportunities

1.800.574.2791
advertising@eeweb.com
www.eeweb.com/advertising

T E C H N I C A L A R T ITomL E C Lee
Chief Education Officer

Why Cant Johnny Design?

Part 1:
Challenges in Modern Engineering Education

TECHNICAL ARTICLE

hese are interesting times for the engineering profession. On the surface, there are signs of a real engineering Renaissance. Technological magic seems to generate ever-more impressive gadgets, our cars are achieving near miraculous efficiency at affordable prices for the consumer, and modern engineering disciplines like biomedical engineering are offering new hope to countless people who would have been functionally marginalized in decades past. So why are engineering educators so grumpy these days?
EEWeb | Electrical Engineering Community Visit www.eeweb.com

14

TECHNICAL ARTICLE
TECHNICAL ARTICLE

Figure 1: Engineering deans gather in Beijing to explore avenues to transform the undergraduate curriculum

No, there is no scientific study that has tracked a grumpiness index among our professors, but in recent years, there definitely seems to be some sense of angst among the academic community. Recently, at a conference of Innovation Centers for Engineering Education (ICEE) on Jeju Island in Korea, Korean professors gathered as part of a regular sequence of meetings among a network of 60 Korean engineering universities. These universities were charged by the national government to close the gap that exists between Korean engineering programs and the needs of Korean industry. Today, it is widely believed that Korean industry can legitimately claim the

hard-fought title of the next Japan. Certainly on the consumer side, the products of the Korean electronics and automotive industries like Samsung and Hyundai, by any measure, command brand respect approaching, if not equaling, legendary Japanese brands such as Sony and Toyota. The Korean ICEE initiative is significant in that it is a focused, wellfunded initiative by an engineering community that is targeting the future driven by engineering creativity and innovation rather than manufacturing quality and aggressive labor costs. The sessions at this conference focused not so much on graduating more

engineers to meet increasing demands; it tackled the more challenging, big-picture, questions on what qualities the engineers of tomorrow should embody and how the academic community can deliver the appropriate training. ICEE is currently concluding its first five-year mandate from the national government of Korea indicating that funding will be renewed, if not increased. Grand Challenges of Modern Engineering The Korean ICEE experience is a case study in a regional response to the larger issue of the readiness of engineering

EEWeb | Electrical Engineering Community

Visit www.eeweb.com

15

TECHNICAL ARTICLE
graduates. The most ambitious statement of the significance of engineering requirements of the future is best articulated by the so-called Grand Challenges for Engineering. In 2008, the National Academy of Engineering in the United States presented fourteen major technological issues that vex humankind and encouraged the global engineering community to use these as a framework for assessing education, research, policy, and industrial strategies. The grand challenges are: make solar energy economical, provide energy from fusion, develop carbon sequestration methods, manage the nitrogen cycle, provide access to clean water, restore and improve urban infrastructure, advance health informatics, engineer better medicines, reverse-engineer the brain, prevent nuclear terror, secure cyberspace, enhance virtual reality, advance personalized learning, and engineer the tools of scientific discovery. For many in the academic community, these challenges have precisely articulated the significance of the work of modern engineers but unfortunately, it also highlights how difficult it will be to prepare our students to tackle these immense challenges. The current engineering curriculum, delivered by the great majority of institutions worldwide, had its genesis in the mid-twentieth century. Largely motivated by then urgent requirements of the so-called Space Race and its darker flipside, the Cold War, a large number of engineers had to be trained to meet the needs. The response from the academic community was a curriculum that one might consider to be linear start with mathematical and scientific foundations in the early years, progress to application courses in the middle years, then cap it off with a rigorous thesis or senior project. Additionally, the tradition of separating students into welldefined engineering disciplines (electrical, mechanical, chemical, civil, etc.) became entrenched. Although one cannot deny that this approach was effective in that the needs of society were largely met, it left this generation with lingering memories of being completely lost for four or more years and eventually seeing the light once they began experiencing the real world. The mismatch for the modern context often sites two very significant issues. First, as anyone that graduated from engineering programs during this period, is the simple reality of keeping students motivated through the very intensive and often abstract, theory-heavy gauntlet of the first years of the undergraduate program. Many of us asked, What is the significance of this calculus theorem proof in the real world? as we struggled through the process. In some sense, this is the easier problem as many successful techniques have emerged within the past few decades that have attempted to introduce more applications, hands-on labs and case studies to help soften the blow. The trickier issue is the latter the disconnect between the traditional structure of the engineering disciplines and the emerging complexities of modern engineering systems. With the pace of innovation and the increasing sophistication of products and infrastructure, many consider the techniques represented by the traditional curriculum out-ofdate. Modern engineering teams are typically cross-functional with contributions from a variety of specializations. This included technical and non-technical specializations, including business and human factors. The shortening project time-lines also demand greater project parallelization and cross-functional tasks that simply do not map cleanly to the disciplines. Simply put, engineers need to know more and do more, all with less time and resources. Technologically, such pressures have triggered highly innovative techniques often facilitated by modern information and digital technology. A clear testament to this trend is the academic migration of the traditional departments of Electrical Engineering (EE) to the more contemporary hybrid departments of Electrical and Computer Engineering (ECE). In another important corner of the engineering world, many departments of Mechanical Engineering (ME) are starting to express themselves as Mechanical and Mechatronic Engineering (MME). This sort of trend is one of the modern responses of the academic community; creating new departments to accommodate new techniques. Is this sufficient? The reality is: this will generate a relatively small specialized group of engineers skilled in even more

TECHNICAL ARTICLE

EEWeb | Electrical Engineering Community

Visit www.eeweb.com

16

TECHNICAL ARTICLE
specialized and narrow fields. It also leaves the vast majority of our students in the framework of the traditional disciplines. A very practical example of the deficiency in this approach becomes clear in a very familiar context: modern cars. A Practical Example: The Green Car Virtually all consumer vehicles produced today are electronically fuel-injected. More precisely, they are typically computer-controlled, deploying the same semiconductor technology we use in our general purpose computers. The electronic control unit (ECU) manages the fuel injection and ignition timing and other key parameters that influence the burning and energy release of the engine. For many cars, there will also be some computer control through the drivetrain (e.g. traction control). Within the rapid development cycles of todays auto industry, it becomes essential for the engineering team to work with the system in its totality. In the case of the engine, you will need to consider mechanical, chemical, and electrical characteristics as a minimum. You will also need computing knowledge, as the engines are computer-controlled. From a workflow perspective, new techniques such as hardware in the loop testing (HIL), offer a rapid, highly accurate and cost-effective way of testing the performance of control systems for engines or any other computer-controlled subsytem. This is a way of testing key components without having to physically prototype the entire system only to find a critical design flaw. This type of sophisticated simulation and control systems design will demand a system-level approach that blends techniques and knowledge from many of the specialized disciplines. Extrapolating further to green vehicle design, the same problems become greatly amplified for hybrid electric vehicles (HEV), fully electric (EV), and fuel-cell powered vehicles. For these applications, chemical engineering knowledge becomes increasingly important as battery design and alternative fuels become the big variables. The Renaissance Engineer The professors at the Korean conference expressed keen interest in techniques that introduce such multidisciplinary and system-level approaches to an engineering education. It may seem simple enough to begin merging select techniques from other disciplines into programs, but the actual implementation is substantially more difficult. The curriculum legacy is entangled within a large complex system of organizations and suborganizations with bureaucratic structures and decision-making processes that ensures academic freedom but hinders coordinated transformation. Furthermore, the recent focus on the research function of the engineering university also needs to be tempered to allow greater creativity and energy to revitalize the teaching function. The Korean context was used to highlight the level of commitment and vision required to educate the modern Renaissance engineer. This particular group would be the first to admit that they have only taken a baby step. But that first step is literally a doozy. Korea is a nation of fifty million people for whom the engineering community has literally lifted the population out of mass poverty within a generation. For this country, the revitalization of the engineering community is an issue of national priority and government, industry, and academic institutions seem to be in-sync to implement the changes. They are not alone, however. At another recent conference in Asia, approximately three hundred deans of engineering and other senior engineering education administrators met in Beijing at the 2011 Global Engineering Deans Conference presented by the International Federation of Engineering Education (IFEES). In the audience were significant contingents from North American institutions who are also anxious to learn from their global peers and trigger positive action in their respective juristictions. Throughout North America and elsewhere, a generation of children have embraced robotics as a hobby and even an obsession. These same children also lose sleep at night wondering whether their world will provide sufficient food, clean water, and livable environments when they take the helm. In many ways, the scene is fundamentally different from the concerns of Western nations on whether we are training enough engineers to compete against emerging economic superpowers. The demands on the engineering community are becoming deeply personal and we witness an empowered generation ready to take on the challenges

TECHNICAL ARTICLE

EEWeb | Electrical Engineering Community

Visit www.eeweb.com

17

TECHNICAL ARTICLE
but they can only succeed if our generation can structure our institutions and methods to guide them wisely. Part two of this article will explore specific techniques and case studies on education innovation and key trends that are aimed at the revitalization of the engineering curriculum. About the Author Dr. Lee has been an active contributor in the global engineering and control systems community for over twenty years. As Chief Education Officer at Quanser, a leader in realtime control and mechatronics solutions for education, research, and industry, Dr. Lee develops and implements the companys strategy for enriching and increasing the educational effectiveness of technology in the modern engineering education context. Prior to his appointment at Quanser, Dr. Lee was Vice President of Applications Engineering at Maplesoft, creators of the renowned Maple mathematical software system. In that capacity, he helped the company transform the mathematical technology to a complete engineering modeling and simulation solution. He also serves as an Adjunct Professor of Systems Design Engineering at the University of Waterloo, noted for its leadership in engineering, computer science, and mathematics. Dr. Lee earned his Ph.D. in Mechanical Engineering at the University of Waterloo, and his M.A.Sc. and B.A.Sc. in Systems Design Engineering at the University of Waterloo. He has published numerous papers and is a frequent invited speaker in the areas of engineering education, engineering modeling and simulation, and engineering computation.

TECHNICAL ARTICLE

EEWeb
Electrical Engineering Community

Join Today
www.eeweb.com/register
EEWeb | Electrical Engineering Community Visit www.eeweb.com

18

Get the Datasheet and Order Samples

http://www.intersil.com

Rad Hard and SEE Hard 12A Synchronous Buck Regulator with Multi-Phase Current Sharing
ISL70002SEH
The ISL70002SEH is a radiation hardened and SEE hardened high efficiency monolithic synchronous buck regulator with integrated MOSFETs. This single chip power solution operates over an input voltage range of 3V to 5.5V and provides a tightly regulated output voltage that is externally adjustable from 0.8V to ~85% of the input voltage. Output load current capacity is 12A for TJ +150C. Two ISL70002SEH devices configured to current share can provide 19A total output current, assuming 27% worst-case current share accuracy. The ISL70002SEH utilizes peak current-mode control with integrated error amp compensation and pin selectable slope compensation. Switching frequency is also pin selectable to either 1MHz or 500kHz. Two ISL70002SEH devices can be synchronized 180 out-of-phase to reduce input RMS ripple current. High integration makes the ISL70002SEH an ideal choice to power small form factor applications. Two devices can be synchronized to provide a complete power solution for large scale digital ICs, like field programmable gate arrays (FPGAs), that require separate core and I/O voltages.

Features
DLA SMD#5962-12202 12A Output Current for a Single Device (at TJ = +150C) 19A Output Current for Two Paralleled Devices 1MHz or 500kHz Switching Frequency 3V to 5.5V Supply Voltage Range 1% Ref. Voltage (Line, Load, Temp. & Rad.) Pre-Biased Load Compatible Redundancy/Junction Isolation: Exceptional SET Performance Excellent Transient Response High Efficiency > 90% Two ISL70002SEH Synchronization, Inverted-Phase Comparator Input for Enable and Power-Good Adjustable Analog Soft-Start Input Undervoltage, Output Undervoltage and Adjustable Output Overcurrent Protection QML Qualified per MIL-PRF-38535 Full Mil-Temp Range Operation (-55C to +125C) Radiation Environment - High Dose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 krad(Si) - ELDRS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 krad(Si)* *Level guaranteed by characterization; EH version is production tested to 50 krad(Si). SEE Hardness - SEL and SEB LETTH . . . . . . . . . . . . . . . . . . 86.4MeV/mg/cm2

Applications
FPGA, CPLD, DSP, CPU Core and I/O Voltages Low-Voltage, High-Density Distributed Power Systems

- SEFI LETTH. . . . . . . . . . . . . . . . . . . . . . . . . . . . 43MeV/mg/cm2 - SET LETTH . . . . . . . . . . . . . . . . . . . . . . . . . . 86.4MeV/mg/cm2

90

25 20 15 10 5

CH1 MASTER LX + 20V

EFFICIENCY (%)

85

AMPLITUDE (V)

CH2 SLAVE LX + 15V CH3 VOUT x 10 CH4 SYNC

80

75

0 70 0 -6 1 2 3 4 5 6 7 8 LOAD CURRENT (A) 9 10 11 12 -4 -2 0 2 4 6 TIME (s) 8 10 12 14

FIGURE 1. EFFICIENCY 5V INPUT TO 2.5V OUTPUT, TA = +25C

April 5, 2012 FN8264.1

FIGURE 2. 2-PHASE SET PERFORMANCE at 86.4MeV/mg/cm2

Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2012 All Rights Reserved. All other trademarks mentioned are the property of their respective owners.

TECHNICAL ARTICLE

TDR: Leaves Reading the Tea

Lead

TECHNICAL ARTICLE

Mich

Arch

ael S
itect,

Seria

teinb
l Cha

nnel

erge

Prod u

cts

Time domain reflectometry (TDR) is an essential microwave measurement technique and also an essential technique for analyzing measured S parameters. However, extracting as much information as possible from a TDR trace can resemble the work of a fortune teller. There is a lot of information that escapes the casual observer but is readily apparent if one knows what to look for. This article reviews the basic techniques for interpreting TDRs and then adds a couple of simple techniques that are not as well known.

goal is to determine the magnitude and location of the transmission line discontinuities that are in the actual circuit, independent of what any model might predict. TDR data can also be generated for models, and thats useful for comparison to measured data. Figure 1 and Figure 2 are examples of TDR data computed from measured S parameters. Each figure shows a time domain waveform which approximates the reflection coefficient as a function of time (and therefore distance). The two figures show TDR data looking from opposite ends of the same interconnect network. As will be explained in the following sections, the individual elements such as vias, traces, and connectors are clearly visible in the TDR trace. Some of these features are labeled in the figures.

What Happens Where

The goal of time domain reflectometry (TDR) is to correlate the electrical behavior of a transmission line circuit with its physical features. Once one understands which physical features have the most significant effect on electrical behavior, its a lot easier to improve the design. TDR is almost always associated with measured dataeither the TDR data is measured directly or else its computed from measured S parameters. Either way, the

How TDR Data is Measured

Time domain reflectometry measures the voltage step response at the input to the device under test. The source impedance is typically a standard reference impedance such as 50 ohms single ended or 100 ohms differential.

EEWeb | Electrical Engineering Community

Visit www.eeweb.com

20

TECHNICAL ARTICLE
TECHNICAL ARTICLE
1200.0

AC Coupling Cap

Connectors

1100.0

Volts (mV)

1000.0

Vias
900.0

Package Ball
0.0 2.0

Line Card Trace

4.0

Backplane Trace
6.0

Line Card Trace

8.0 10.0 12.0 14.0

Time (ns)

Figure 1: Example TDR derived from measured S parameter data

1200.0

Connectors

1100.0

Volts (mV)

1000.0

Vias
900.0

Package Ball
0.0 2.0

Line Card Backplane Trace Trace

4.0 6.0

Line Card Trace

8.0 10.0 12.0 14.0

Time (ns)

Figure 2: Example TDR looking at the same path from the opposite direction

For actual physical measurements, there is usually a length of transmission line needed to connect the device under test to the measurement circuit. As will be seen later, this length of transmission line also plays a role in calculating a TDR from measured S parameters. When performing TDR on an interconnect network, the common practice is to terminate the network with the same impedance as the source. The single ended version of this setup is shown in Figure 3. The idea is that when the rising edge of the voltage step stimulus encounters any change in the impedance of the transmission path, it generates a reflected edge that propagates back toward the stimulus source. When this reflected edge arrives at the input to the interconnect network, it gets added to the voltage at this node. There is a delay between the time the stimulus edge first passed the input to the interconnect network and the time that

the reflected edge arrived at the same circuit node; and this delay indicates the position of the discontinuity that generated the reflected edge. To interpret TDR results with any degree of clarity, one must understand the three approximations on which the concept of TDR is based: 1. The impedance of the transmission path is approximately constant. 2. The transmission path is approximately lossless. 3. The propagation velocity is approximately constant. In most applications, none of these approximations is very good. They are usually good at the beginning of the transmission path, but then gradually break down; and the rate at which these approximations break down should drive the way one interprets the results.

EEWeb | Electrical Engineering Community

Visit www.eeweb.com

21

TECHNICAL ARTICLE
Z0 Z0 + Step Stimulus + Measure Step Response Interconnect Network Z0

infinite step response amplitude; it results in a doubling of the step response amplitude. Therefore the amplitude scale of a TDR waveform is really incident wave plus a reflection coefficient between 0 and 2 rather than a linear impedance scale.

TECHNICAL ARTICLE

Figure 3: Time domain reflectometry measurement of interconnect network

Nonetheless, these approximations are good enough to obtain some useful information. If one assumes that the three simplifying approximations are valid, then for a transmission path with varying impedance , the reflection coefficient for a short length --- of that path is:

b. If there are multiple discontinuities in the transmission path, then the step response edge reflected by a disontinuity which is further from the measurement point will be reflected by the nearer discontinuities and then reflected again by the further discontinuity, resulting in multiple reflections arriving at the measurement point. 2. Transmission Loss As the step response edge propagates along the transmission path, it encounters loss, especially at higher frequencies. This loss smooths out the edge that is incident on discontinuities which are further from the measurement point. The step response edge that is reflected also gets smoothed out on its way back to the measurement point. Therefore features which are further from the measurement point become less distinct. For example, the features on the right hand side of Figure 1 and Figure 2 are much less distinct than those on the left hand side, even though the features on the left hand side of one figure are exactly those of the right hand side in the other figure. 3. Propagation Velocity Variations If the propagation velocity changes, for example because the transmission medium changes from PC board to cable, then the translation from time to distance will be distorted accordingly.

Taking the limit as and applying the approximation of constant impedance,

Applying the second and third approximations (low loss and constant velocity) to the calculation of the impulse response at the driving end, and assuming that the propagation velocity is y,

One can then get the step response (that which is actually measured) by integrating with respect to time. The result is:

In other words, the amplitude of the step response at a particular time is approximately proportional to the impedance at some corresponding distance along the transmission path. This is the desired result. As each of the approximations breaks down, however, the step response exhibits additional artifacts. 1. Impedance Variations a. As the impedance variations become more and more extreme, the impedance scale in the TDR waveform becomes distorted. For example, an open circuit (essentially infinite impedance) does not result in an

Interpreting the TDR Trace

Figure 4 shows a view of the example TDR in Figure 1 that has been plotted on an impedance scale and expanded to show some detail at the beginning of the TDR trace.

Measurement/calculation setup
The first two nanoseconds of the TDR trace show some details about how the TDR was calculated, or how the equivalent trace would be measured in the lab. Since the original S parameter data was supplied to

EEWeb | Electrical Engineering Community

Visit www.eeweb.com

22

TECHNICAL ARTICLE
70.0
x1: (2.269n) x2: (2.346n) dx: 0.077n

Connector

65.0

AC Coupling Cap
y1: (51.740) y2: (265.720) dy: 13.980

60.0

x1: (3.742n) x2: (3.814n) dx: 0.072n

the beginning of the measured trace. At this particular position on this particular trace, there happens to be an AC coupling cap. Therefore, the discontinuity is most probably due to the AC coupling cap. Similarly, after the AC coupling cap there is 1.37nS of delay to the next significant discontinuity, an abrupt reduction in the apparent impedance. The position of this discontinuity is approximately 1.37nS/2/150pS = 4.57 trace length from the AC coupling cap. This corresponds to the connector via at the edge of the board. Therefore, the structure on the right hand side of Figure 4 is most probably the connector with its vias. To produce the labels in Figure 1, this process was continued along the entire TDR trace.

TECHNICAL ARTICLE

Ohms

55.0

Line Card Trace

50.0

45.0

x1: (2.019n) x2: (2.303n) dx: 0.284n

x1: (2.360n) x2: (3.730n) dx: 1.370n

y1: (52.530) y2: (49.570) dy: -2.952

Vias

40.0 0.0 1.0 2.0 3.0 4.0

Time (ns)

Figure 4: Example TDR expanded and shown using imedance scale

20GHz, there is an initial delay of 17pS corresponding to the rise time of the measurement stimulus. This 17pS is also the rise time/resolution quoted in the data sheet for at least one 20GHz bandwidth sampling oscilloscope that is used to measure TDR. Also, the measurement setup shown in Figure 3 includes a transmission line inserted in the measurement circuit between the measurement point and the device under test. For the calculations shown here, the delay of that transmission is 1nS, thus injecting a 2nS round trip delay in the measurement. This calculation technique was suggested to me by Donald Telian. Note that although the reflections due to an ideal transmission line should be zero, there appear to be nonzero reflections in the first 2nS of the TDR trace. These apparent reflections are actually numerical artifacts due to the fact that the S parameter data was limited to 20GHz whereas the real circuit has a nonzero response beyond 20GHz. If these numerical artifacts are not included in the integration of the TDR as a step response, the TDR is offset vertically by the integral of these numerical artifacts. Identifying Features and Trace Lengths There is an abrupt increase in impedance approximately 280pS after the beginning of the circuit under test. Since 280pS is the round trip delay, this discontinuity occurs after the stimulus has traveled 140pS on the line card. Assuming that the line card dielectric is a relatively high quality dielectric with a dielectric constant of 3.2, the speed of propagation is 150 pS/inch. Therefore, this discontinuity occurs at approximately 0.92 from

Lumped Elements
Short, clearly defined discontinuities such as the AC coupling cap in Figure 4 can be approximated as lumped circuit elements: either series inductors when the discontinuity impedance is higher or shunt capacitors when the discontinuity impedance is lower. Consider, for example, that the AC coupling capacitor increases the apparent transmission line impedance by about 14 for a round trip delay of 77pS in the TDR trace, or 38.5pS on the PC board. This is enough information to estimate the series inductance of the AC coupling cap. From [1], the impedance of a transmission line as a function of its propagation velocity v, its inductance per unit length l and it capacitance per unit length c is

Consider also that the time delay due to a propagation across a distance d is

The total excess inductance is therefore

For the AC coupling cap in Figure 4, this comes out to a series inductance of 0.54nH, which is about right for a surface mount capacitor. For capacitive discontinuities, the calculation must be performed using the reciprocal of the characteristic

EEWeb | Electrical Engineering Community

Visit www.eeweb.com

23

TECHNICAL ARTICLE
impedance. That is, Therefore from Figure 5, the series resistance of that particular interconnect network is approximately 3. For another view of the measurement of interconnect network behavior at low frequencies, see [2].

TECHNICAL ARTICLE

For example, the via in Figure 4 increases the conductance of the transmission line from 1/52.5 Semens to 1/49.6 Semens, for an increase of 0.00114 Semens. One half of the round trip delay of 72pS in the TDR trace is 36pS, so the excess capacitance of the via is approximately 41fF.

References
[1] Matthei, Young and Jones, Microwave Filters, Impedance Matching Networks, and Coupling Structures, section 5.02, equation 5.02-5, page 164, McGraw-Hill, copyright 1964. [2]http://realtimewith.com/pages/r twvprofile. cgi?rtwvcatid=13&rtwvid=1691

Steady State Values

It is often observed that the steady state value of a TDR
70.0

65.0

60.0

About the Author

Michael Steinberger, Ph.D., is responsible for leading SiSofts ongoing tool development effort for the design and analysis of serial links in the 5-30 Gbps range. Dr. Steinberger has over 30 years experience in the design and analysis of very high speed electronic circuits. Dr. Steinberger began his career at Hughes Aircraft designing microwave circuits. He then moved to Bell Labs, where he designed microwave systems that helped AT&T move from analog to digital long-distance transmission. He was instrumental in the development of high speed digital backplanes used throughout Lucents transmission product line. Prior to joining SiSoft, Dr. Steinberger led a group of over 20 design engineers at Cray Inc. responsible for SerDes design, high speed channel analysis, PCB design and custom RAM design.

Ohms

55.0

50.0
y1: (50.0) y2: (53.010) dy: 3.012

45.0

40.0 0.0 2.0 4.0 6.0 8.0 10.0 12.0 14.0

Time (ns)

Figure 5: Example TDR with series resistance shown

trace is higher than the initial stimulus amplitude. This is apparent in Figure 1 and Figure 2, and is illustrated again using an impedance scale in Figure 5. This feature of the TDR trace is not a numerical artiface; its a fundamental behavior of the interconnect network and a useful piece of information. Consider that when the TDR trace (as a step response) settles to a long term value, the equivalent circuit is
Z0 R

Step Stimulus

Measure Step Response

Interconnect Network

Z0

Figure 6: Steady state measurement of interconnect network

That is, at steady state, the only relevant circuit elements are the resistances in the circuit. For most interconnect networks (those with negligible DC leakage), the resistances are the source resistance, the load resistance, and the series resistance of the interconnect network.

EEWeb | Electrical Engineering Community

Visit www.eeweb.com

24

TECHNICAL ARTICLE
TECHNICAL ARTICLE

Run 10's of 1,000's of Simulation Cases to Spot System-Level Trends.

EEWeb
Electrical Engineering Community
Contact Us For Advertising Opportunities

1.800.574.2791
advertising@eeweb.com
www.eeweb.com/advertising
EEWeb | Electrical Engineering Community Visit www.eeweb.com

25

TECHNICAL ARTICLE
Billie Johnson

TECHNICAL ARTICLE

Physical Design Engineer

Your Clocks, My Layout

Introduction In digital circuit design, a clock signal is one that oscillates between a high and a low state and directs a circuits performance. Logic may toggle on the rising edge, falling edge or both edges in an application. With thousands of instances running off of a given clock domain, it is necessary to insert a tree of buffering to adequately drive the logic. Clock trees often have delay, skew, minimum power, and signal integrity requirements that the layout engineer must meet. Arguably clock descriptions and diagrams are the most critical information that must be communicated when a circuit is transferred from a front-end designer to the back-end layout engineer. Hours, days, and even weeks of design work has been lost over the years due to miscommunications, misunderstandings, and needs for complete re-synthesis involving clock trees. Before layout, ideal clocks are used for synthesis and timing constraints. Clock definition constraints may appear on top-level pads or pins of a block; on the output of a macro such as a delay-locked loop (DLL) or phase-locked loop (PLL); or as a generated clock on a dividing register. These clock definitions may or may not be where the layout engineer needs to define clock roots to attain optimal latencies, balancing and skew across various modes of operation. A high level of information exchange between the front end and layout along with an understanding of what layout will do with that information will greatly improve the CTS process of the physical design flow. Design Tips for Successful CTS Some of the following tips have been circling around the industry for quite a while, but based on experience over the last few years, they are worth repeating.

EEWeb | Electrical Engineering Community

Visit www.eeweb.com

26

TECHNICAL ARTICLE
Establish a naming convention for clock muxes or instances that you know will be a start point for a clock tree. This provides a nice sanity check for layout because it is easy to search and count in a layout database based on strings. Use medium- to high-strength drivers for clock root instances. This allows the clock tree to get off to the right start. Do not use the highest drive strength available in your library, however, because it is useful to be able to upsize later in the design if issues are uncovered with signal integrity (SI) analysis or on-chip variation (OCV) analysis. Make certain that clock divide registers and their sync registers are purposely driven by muxing logic if they are to run in a separate test mode. This allows the capability to add delay on the input side of the mux for a test mode without pushing out all of the other registers clocked by the generated clock in functional mode. Figure 1 shows two register clock divide registers. Without additional muxing logic, a functional clock will most likely not work for a test mode. The divide-by registers wont be balanced with any of the registers downstream. The fewer registers in the green domain would likely lead to a much faster clock than in that of the purple domain. Figure 2 illustrates a muxing scheme that would allow for each clump of downstream registers and the divide-bys to have a minimized clock through one input of a mux AND a balanced one through the other. Insert a reset-specific driver if necessary. Sometimes a couple of registers will be used to synchronize a reset. It may not be necessary for those registers to be balanced to all of the other ones also driven by that clock. In Figure 3, without a focused strategy, software will try to balance the blue registers after the gating logic with each of the pink registers contained in the reset synchronizing logic. This scenario can be easily handled in the layout if they are split from the rest of the registers with their own exclusive driver.
10 S Q 11

TECHNICAL ARTICLE

500

Figure 1

10 S Q 11

10 S Q 11

10 S Q 11

10 S Q 11

50

Figure 2

Rst_out

Clock Root

Figure 3

Clock Root #2 excluded from CTS of #1

Rst_out

Clock Figure 4 demonstrates how a place-holder or excludingRoot #1 buffer can be inserted and easily identified in the handoff communication so the layout engineer knows where Figure 4 balancing attempts can diverge.

EEWeb | Electrical Engineering Community

Visit www.eeweb.com

27

TECHNICAL ARTICLE
Provide a better-than-you-think-you-need clock diagram and extensive written description. When front end design is ready to deliver the netlist to layout, they are already widely familiar with the design and clock requirementsor at least they should be. Sometimes initial CTS efforts will uncover that the ideal values used in pre-layout timing constraints are not physically achievable. Problems leading to this can be revealed sooner rather than later if an accurate clock diagram is provided with the netlist handoff along with information about the clocking scheme. An overall diagram or diagrams representing all of the designs clocks including gating logic is ideal. This could be software-generated either with a drawing program or a schematic capture tool. It can even be drawn by hand and saved in a PDF or faxed to the layout engineer. This picture could be worth a thousand words spread over dozens of phone calls and e-mails trying to get the clock formats straight. Since diagrams can get complicated and messy, accompanying written descriptions are needed. This includes explanations of generated clocks, details of any clock gating or muxing patterns, and requirements for skew balancing and latencies. These particulars are necessary for each mode of operation because each mode must be addressed during clock tree insertion. Registers may wind up balanced beautifully for functional mode but miserably unbalanced for test modes if we are not careful. If the clocks utilize a DLL or another macro or if it passes through gating logic, these details are necessary. Macros purposes must be explained. It is possible to synthesize and balance through those types of macros if that is what is desired. As for gating logic, if a scenario exists in which one pin is accessed in one mode, but another pin of the same cell is accessed in another mode the trace tool will identify this as a Reconvergent Clock. Although layout tools can resolve these cases, it may be better to force the tool to look through one pin instead of the other during the clock insertion. clock root insertion points, latency, skew and transition targets, and specifics for gating logic, through-registers, and cross-domain relationships can be ported directly into the CTS tool. The layout engineer will then use their discretion concerning buffer types to use, optimization iterations and requirements for the router like spacing, shielding, and metal layers. Before clock trees are inserted, a trace can be performed to ensure endpoints that are intended to be balanced will be. Gating logic, excluded legs off of a clock root, IO endpoints, and reconvergent instances can also be revealed and assessed. Clock trees can consist of buffering cells only or series of inverters. Most technologies today have special clock buffering and clock inverting cells that have a balanced rise and fall time to help ensure an uncompromised duty cycle. Other requirements like levels in a tree or max fanout of each clock cell can also be incorporated.

TECHNICAL ARTICLE

Conclusion
In addition to everything discussed so far, the layout engineer will likely experiment with clock-gate-aware placements, clock routing guides and floorplan tweaks. Iterations of CTS will often be run with minor modifications for the skew, latency, and transition targets. Trial and error helps achieve the perfect blend. If the front end understands how CTS works, and communicates the clock structure at the onset, then the layout engineer can embark upon the task more proficiently. Time for CTS in the schedule can be spent tuning and improving your clocks rather than simply trying to insert them into my layout. About the Author Billie Johnson is a Physical Design Engineer at ON Semiconductor. Her work experience spans test, design, technical marketing and layout, and she holds a B.S. in Engineering and an MBA from Idaho State University in Pocatello, Idaho. She has participated in numerous K-12 math and engineering outreach programs throughout her career including MATHCOUNTS ,FIRSTLEGO League (FLL) , Wind for Schools and Introduce a Girl to Engineering Day.

CTS Within Industry Tools

Industry software facilitates clock tree synthesis with powerful tools driven by designers specifications and guidelines. Information from the front end pertaining to

EEWeb | Electrical Engineering Community

Visit www.eeweb.com

28

RETURN TO ZERO
RETURN TO ZERO

EEWeb
Electrical Engineering Community

Join Today
EEWeb | Electrical Engineering Community www.eeweb.com/register Visit www.eeweb.com

29