Documenti di Didattica
Documenti di Professioni
Documenti di Cultura
Features
40A, 100V rDS(ON) = 0.055 Single Pulse Avalanche Energy Rated SOA is Power Dissipation Limited Nanosecond Switching Speeds Linear Transfer Characteristics High Input Impedance Related Literature - TB334 Guidelines for Soldering Surface Mount Components to PC Boards
Ordering Information
PART NUMBER IRF150 PACKAGE TO-204AE BRAND IRF150
Symbol
D
Packaging
JEDEC TO-204AE
DRAIN (FLANGE)
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright Intersil Corporation 1999
IRF150
Absolute Maximum Ratings
TC = 25oC, Unless Otherwise Specied IRF150 100 100 40 25 160 20 150 1.2 150 -55 to 150 300 260 UNITS V V A A A V W W/oC mJ oC
oC oC
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDS Drain to Gate Voltage (RGS = 20k) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID TC = 100oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VGS Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .PD Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single Pulse Avalanche Energy Rating (Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .EAS Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg
CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specication is not implied.
NOTE: 1. TJ = 25oC to 125oC. TC = 25oC, Unless Otherwise Specied SYMBOL BVDSS VGS(TH) IDSS ID(ON) IGSS rDS(ON) gfs td(ON) tr td(OFF) tf Qg(TOT) Qgs Qgd CISS COSS CRSS LD Measured between the Contact Screw on the Flange that is Closer to Source and Gate Pins and the Center of Die Measured from the Source Lead, 6mm (0.25in) from the Flange and the Source Bonding Pad Modified MOSFET Symbol Showing the Internal Devices Inductances
D LD G LS S
Electrical Specications
PARAMETER
TEST CONDITIONS VGS = 0V, ID = 250A (Figure 10) VGS = VDS , ID = 250A VDS = Rated BVDSS , VGS = 0V VDS = 0.8 x Rated BVDSS , VGS = 0V, TJ = 125oC VDS > ID(ON) x rDS(ON)MAX , VGS = 10V VGS = 20V VGS = 10V, ID = 20A (Figures 8, 9) VDS > ID(ON) x rDS(ON)MAX , ID = 20A (Figure 12) VDD = 24V, ID 20A, RG = 4.7, RL = 1.2 (Figures 17, 18) MOSFET Switching Times are Essentially Independent of Operating Temperature
UNITS V V A A A nA S ns ns ns ns nC nC nC pF pF pF nH
Drain to Source Breakdown Voltage Gate to Threshold Voltage Zero Gate Voltage Drain Current
On-State Drain Current (Note 2) Gate to Source Leakage Current Drain to Source On Resistance (Note 2) Forward Transconductance (Note 2) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Total Gate Charge (Gate to Source + Gate to Drain) Gate to Source Charge Gate to Drain Miller Charge Input Capacitance Output Capacitance Reverse Transfer Capacitance Internal Drain Inductance
VGS = 10V, ID = 50A, VDS = 0.8 x Rated BVDSS , Ig(REF) = -1.5mA (Figures 14, 19, 20) Gate Charge is Essentially Independent of Operating Temperature VGS = 0V, VDS = 25V, f = 1.0MHz (Figure 11)
LS
12.5
nH
0.8 30
oC/W oC/W
IRF150
Source to Drain Diode Specications
PARAMETER Continuous Source to DrainCurrent Pulse Source to Drain Current (Note 3) SYMBOL ISD ISDM TEST CONDITIONS Modified MOSFET Symbol Showing the Integral Reverse P-N Junction Diode
G D
MIN -
TYP -
MAX 40 160
UNITS A A
Diode Source to Drain Voltage (Note 2) Reverse Recovery Time Reverse Recovery Charge NOTES:
TJ = 25oC, ISD = 40A, VGS = 0V (Figure 13) TJ = 150oC, ISD = 40A, dISD/dt = 100A/s TJ = 25oC, ISD = 5.5A, dISD/dt = 100A/s
600 3.3
2.5 -
V ns C
2. Pulse test: pulse width 300s, duty cycle 2%. 3. Repetitive rating: pulse width limited by Max junction temperature. See Transient Thermal Impedance curve (Figure 3). 4. VDD = 10V, starting TJ = 25oC, L = 170H, RG = 50, Peak IAS = 40A. See Figures 15, 16.
32
24
16
0 0 50 100 150 25 50 75 100 125 150 TC , CASE TEMPERATURE (oC) TC , CASE TEMPERATURE (oC)
1.0 IMPEDANCE (oC/W) 0.5 0.2 0.1 0.1 0.05 0.02 0.01 SINGLE PULSE 0.01 10-5 10-4 10-3 10-2 0.1 PDM t1 t2 t2 NOTES: DUTY FACTOR: D = t1/t2 TJ = PDM x ZJC + TC 1 10
9V VGS = 8V
30
7V
20
6V
10
5V 4V
20
2.2
1.8
1.4
1.0
0.06
VGS = 20V
0.6
0.02
40
160
0.2 -60
-40
-20
20
40
60
80
100
120
140
NOTE: Heating effect of 2s is minimal. FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT
4000 VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS CDS + CGD
3200
1.05
0.95
0.85
0.75 -40
-20
20
40
60
80
100
120
140
160
10
20
30
40
50
20 ISD, SOURCE TO DRAIN CURRENT (A) 80s PULSE TEST gfs, TRANSCONDUCTANCE (S) 16 TJ = -55oC TJ = 25oC 12 TJ = 125oC
2 102
TJ = 150oC 10 TJ = 25oC
10
40
50
20 VGS , GATE TO SOURCE VOLTAGE (V) ID = 40A FOR TEST CIRCUIT, SEE FIGURE 19 15 VDS = 20V VDS = 50V 10 VDS = 80V
0V
IAS 0.01
0 tAV
90%
RG DUT
VDD 0
10% 90%
10%
50%
CURRENT REGULATOR
VDS (ISOLATED SUPPLY) VDD SAME TYPE AS DUT Qg(TOT) Qgd Qgs D VDS VGS
12V BATTERY
0.2F
50k 0.3F
DUT 0
IRF150
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certication.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
This datasheet has been downloaded from: www.DatasheetCatalog.com Datasheets for electronic components.