ECE322 Lab 11

Experiment 11 MOSFET Logic Circuits

Fall 2002 Holland

Goal: Obtain the transfer characteristic of MOS inverters and study the characteristics of some MOS logic circuits. 1 1.1

Characteristics of the NMOS Inverter

NMOS Inverter with Ohmic Load

1. Connect the NMOS inverter circuit with an ohmic load as shown in Fig. 1. Use an NMOS transistor from the MOS transistor array CD 4007 (Fig. 6). Make sure Pin 7 is connected to ground and Pin 14 connected to 5V. 2. Apply a low-frequency (100Hz) triangular voltage with a peak-to-peak voltage of 0 to 5V, (adjust offset) to the input of the inverter. 3. Using the X-Y mode of the oscilloscope, observe and sketch the transfer characteristic of the inverter. Adjust the frequency to avoid any hysteresis effect. 4. Measure all voltage levels and in particular the voltages corresponding to logic 1and 0. If necessary, use the waveforms in the X-t mode. 5. Calculate the values of VOH, VOL, VIL, and VIH of the gate. 6. Calculate the noise margins NMH and NML.

Figure 1 NMOS Inverter with R load

1.2

NMOS Inverter with Constant-current Load

1. Connect the inverter circuit as shown in Fig. 2. The connection of gate and drain together forces the load transistor Q2 to operate in the constant current region. 2. Apply a low-frequency (100Hz) triangular voltage with a peak-to-peak voltage of 0 to 5V, (adjust offset) to the input of the inverter. 3. Using the X-Y mode of the oscilloscope, observe and sketch the transfer characteristic of the inverter. Adjust the frequency to avoid any hysteresis effect. 4. Measure all voltage levels and in particular the voltages corresponding to logic 1and 0. If necessary, use the waveforms in the X-t mode. 5. Calculate the values of VOH, VOL, VIL, and VIH of the gate. 6. Calculate the noise margins NMH and NML. C:\Rod\NDSU\EE322\Lab11\ECE322lab11.doc 1 of 4

ECE322 Lab 11

Experiment 11 MOSFET Logic Circuits

Fall 2002 Holland

Figure 2 NMOS Inverter with CC load

CMOS Inverter

1. Connect the CMOS inverter circuit as shown in Fig. 3. 2. Apply a low-frequency (100Hz) triangular voltage with a peak to peak voltage of 0 to 5V, (adjust offset) to the input of the inverter. 3. Using the X-Y mode of the oscilloscope, observe and sketch the transfer characteristic of the inverter. Adjust the frequency to avoid any hysteresis effect. 4. Measure all voltage levels and in particular the voltages corresponding to logic 1and 0. If necessary, use the waveforms in the X-t mode. 5. Under Step 4, observe and sketch the waveform of the current drawn by the gate. This can be done by adding a very small resistance between the source of Q1 and the supply ground. The voltage across this resistance is proportional to the drain current. 6. Calculate the values of VOH, VOL, VIL, and VIH of the gate. 7. Calculate the noise margins NMH and NML.

Figure 3 CMOS inverter

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ECE322 Lab 11

Experiment 11 MOSFET Logic Circuits

Fall 2002 Holland

3
3.1

CMOS Logic
NAND Gate

1. Selecting MOSFETs from the CD 4007 array, connect the circuit of the CMOS NAND circuit as shown in Fig. 4. 2. Verify the truth table for the logic circuit. Also check the condition of all four transistors. Indicate whether each device is ON (Ohmic) or ON (Constant Current) or OFF. 3. Tie both the inputs together and obtain the transfer characteristic. 4. Measure the voltage levels for logic 1 and logic 0. 5. Sketch the transfer characteristic. 6. Calculate the values of NMH and NML. 7. Comment on the power dissipated by the CMOS gate.

Figure 4 CMOS NAND gate

3.2

NOR Gate

1. Connect the circuit of the two-input NOR gate as shown in Fig. 5. 2. Verify the truth table for the logic circuit. Also check the condition of all four transistors. Indicate whether each device is ON (Ohmic) or ON (Constant Current) or OFF. 3. Tie both the inputs together and obtain the transfer characteristic. 4. Measure the voltage levels for logic 1 and logic 0. 5. Sketch the transfer characteristic. 6. Calculate the values of NMH and NML. 7. Comment on the power dissipated by the CMOS gate.

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ECE322 Lab 11

Experiment 11 MOSFET Logic Circuits

Fall 2002 Holland

Figure 5 CMOS NOR gate

Figure 6 Layout diagram of CD 4007

Note: Make sure Pin 7 is connected to the lowest potential (Ground) and Pin 14 is connected to the highest potential (VDD) for any circuit built using this IC.

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