Sense Amplifier for SRAM

Professor : Der-Chen Huang

SoC Lab

Outline
SRAM Structure Sense Amplifier Introduction
Voltage-mode Current-mode

Traditional Voltage-Mode Sense Amplifier Current-Mode Sense Amplifier

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Elementary SRAM Structure

Write Read
R/W Row Decoder Input Register Pre-charge Circuit

Write Circuit

Data_In

Address Register

WL

Memory Cell Array

IE

Address

Column Decoder SAen

Ysel

Select Circuit Sense Amplifier

OE
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Output Buffer

Data_Out

SRAM 6T Cell
SRAM 6T Cell structure

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SRAM 6T Cell
Read operation
1st step ___
BL & BL = 1 Word line = 1
X=0 =1

2nd step
BL = 0
=0 =1

Y=1

=1

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SRAM 6T Cell
Write operation
=1

X=0

Y=1

X=1

Y=0

=1

=0

=1

=0

(a) Before write

(b) After write

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Sensing Amplifier Design Objective and Classification

Design Objective[3]
Minimum sense delay Required amplification Minimum power consumption Restricted layout area High reliability and tolerance

Classification[1][3]
Circuit Types Differential Nondifferential
SoC Lab

Operation Mode Voltage-mode Current-mode

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Bit-line Model[1]
Vdd Bit-line load

R Vo

Memory Cell Bit-line

Ii

RB

RL

io

Memory Cell Model

RC-line

Bit-line RC Model

Sense Amplifier Model

To Sense Amplifier

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Bit-line Model
R R R R Vo RB C C C C Ii RL io

Memory Cell Model

Bit-line RC Model

Sense Amplifier Model

Ii is the output current of the driving source, i.e. memory cell. RB is the output resistance of the bit-line load in parallel with the drain resistance of the access transistor, which is the output device of the memory cell. The infinite RC ladder structure represents the interconnect line. The total resistance and capacitance of the line is given by RT and CT. The output of the line is terminated by resistor RL.
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Bit-line Model
R R R R Vo RB C C C C Ii RL io

Memory Cell Model

Bit-line RC Model

Sense Amplifier Model

RC delay
RT RB + + RL RTCT RL 3 t = + RBCT RB + RT + RL RB + RT + RL 2
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Delay for Voltage-Mode

For voltage-mode signals, RL is infinite and the output signal is the open-circuit voltage Vo. RC delay
RT + RL RB + RTCT RL 3 t = + RBCT 2 RB + RT + RL RB + RT + RL

RTCT 2 RB tv = 1 + 2 RT
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Delay for Current-Mode

For current-mode signals, RL is ideally zero and the output signal is the short-circuit current io. RC delay
0 RT 0 + RL RB + RTCT RL 3 t = 0 + RBCT 0 2 RB + RT + RL RB + RT + RL

RT RB + RTCT 3 ti = 2 RB + RT
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Example
Eample from [1], when
RB = 2500 RT=250 CT=2pf

Voltage-mode
tv = 5.25ns

Current-mode
ti = 0.235ns
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Traditional Voltage-mode Sense Amplifier

Traditional Difference Amplifier[3] Full Complementary Positive-Feedback Sense Amplifier[2][3] Enhanced Positive Feedback Sense Amplifier [4]
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Traditional Voltage-mode Sense Amplifier

Traditional Difference Amplifier
Current mirror
I MP1 = I MP 2 1 ' W kn 2 L MP1 1 ' W = kn (Vgs Vt )2 2 L MP 2
W L = MP 2 W L MP1
MP1 & MP2 have the same Vgs (Vgs Vt )2

IMP1

IMP2 0

I MP 2 I MP1

1= =0 1=

SE = 1 , Sense mode SE = 0 , Standby mode

SoC Lab

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Traditional Voltage-mode Sense Amplifier

Full Complementary Positive Feedback Sense Amplifier
BL __ BL

1=

=0

Vo (t ) = Vo (0) ie
SE = 1 , Sense mode SE = 0 , Standby mode
SoC Lab

( gmR 1) t RC

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Traditional Voltage-mode Sense Amplifier

Enhanced Positive Feedback Sense Amplifier
Decouple device: avoid the effect of the bit-line capacitance

SE = 1 , Sense mode SE = 0 , Standby mode

SoC Lab

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Current-mode Sense Amplifier

Clamped Bit-Line Sense Amplifier[5][6] Simple Four Transistor Sense Amplifier[1] Hybrid Current Sense Amplifier[8][9] New Hybrid Current Sense Amplifier[10] Modified CSA[11]

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Current-mode Sense Amplifier

Clamped Bit-Line Sense Amplifier
PRE = 1 , Pre-charge SA = 1 , Sense
Positive Feedback Circuit

The PRE signal drives high to turn on M7 & M8, which works to equalize the output node to the same voltage level.

Vgs1

Vgs2 I2

I1

M5 & M6 are biased in the linear region and provide a low-impedance clamp between the bit line and the ground.
SoC Lab

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Current-mode Sense Amplifier

Clamped Bit-Line Sense Amplifier

Advantages
The input nodes of the sense amplifier are low-impedance current sensitive nodes, the voltage swing of the highly capacitance bit lines change small. The output nodes of the sense amplifier are no longer loaded with the bit-line capacitance and the sense amplifier is able to respond very rapidly. M1 ~ M4 works as a cross-coupled latch, its positive feedback effect can improve the driving ability of output nodes. Even the small input difference can be detected and the output can drive to full supply swing.
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Current-mode Sense Amplifier

Simple Four Transistor Sense Amplifier
At the begin, Ysel are pulled down to gnd. Because DL near to ground level, T1~T4 will work in saturation region.

I+i I i
The gate-source voltage of T1 will be equal to that of T3, since their currents are equal, their size are equal, and both transistors are in saturation. V1+V2 +

I+i O I+i+ic V1
-

i+ic

I+i
V1+V2 The gate-source voltage of T2 will be equal to that of T4, since their currents are equal, their size are equal, and both transistors are in saturation.

V2
-

ic

V-1

V2
-

ic

I
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Current-mode Sense Amplifier

Simple Four Transistor Sense Amplifier

Advantages
In many cases it can fit in the column pitch, avoiding the need for column-select devices, thus again reducing propagation delay. There exists a virtual short circuit across the bit lines, therefore the potential of the bit lines will be equal independent of the current distribution. The sensing delay is unaffected by the bit-line capacitance since no differential capacitor discharging is required to sense the cell data. Discharge current ic from the bit-line capacitors, effectively precharging the sense amplifier.

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Current-mode Sense Amplifier

Simple Four Transistor Sense Amplifier
I5 = I4 + I6 Because current mirror effect, I3 > I4, so I5 > I4.

I5

Ysel = 0 , Sense mode Ysel = 1 , Standby mode

Because I1 > I2, so I3 > I4

I6

I3 I1 I4

Current mirror

Current Conveyor

I2

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Current-mode Sense Amplifier

Hybrid Current Sense Amplifier

Positive Feedback Circuit

Current Conveyor

I1 I2

Vgs3

Vgs4

Biased in the linear region and provide a low-impedanc.

SoC Lab

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Current-mode Sense Amplifier

New Hybrid Current Sense Amplifier
Overcome the pattern-dependent problem of the conventional current conveyor. In conventional current conveyor, after each read operation, the nodes RXP and RXN get floated and there will exist a residual differential voltage between them. The pattern-dependent problem occurs when the same logic value is sequentially read out several times from the same column.

CBLSA

Current Conveyor
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Current-mode Sense Amplifier

S.M. Wangs Sense Amplifier
In standby state, pull the bitlines close to the ground level N7 & N8 are turned off to avoid DC current flows in the sense amplifier. N3 & N4 are Circuit Positive Feedback turned on to pull down the drains of the N5 & N6 to low-level.

Sensing state Standby state SEN = 0 1 SENB = 1 0

Vgs5

Vgs6

I1 I2

Biased in the linear region and provide a low-impedance.

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Reference
[1] E. Sccvinck, P. J. van Beers, and H. Ontrop, Current-Mode Techniques for HighSpeed VLSI Circuits with Application to Current Sense Amplifier for CMOS SRAMs, IEEE Journal of Solid-State Circuits Vol.26 No.4 pp.525-536 April 1991. [2] T. P. Haraszti, High Performance CMOS Sense Amplifiers, United States Patent No. 4,169,233, Sep. 1979. [3] Tegze P. Haraszti, CMOS Memory Circuits, Kluwer Academic Publishers, 2000. [4] V.Kristovski and Y. L. Pogrbeny, New Sense Amplifier for Small-Swing CMOS Logic Circuit, IEEE Trans, On Circuit and Systems, vol. 47, p.p. 573~576, June 2000. [5] Blalock, T.N. and Jaeger, R.C.,A High-speed Clamped Bit-line Current-mode Sense Amplifier, IEEE J. Solid-State Circuits, vol. 26, no. 4, pp542-548, April 1991. [6] Blalock, T.N. and Jaeger, R.C., A subnanosecond clamped-bit-line sense amplifier for 1T dynamic RAMs, Proceedings of VLSI Technology, Systems, and Applications, pp82-86, May 1991.
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Reference (cont.)
[7] Chrisanthopoulos, A., Moisiadis, Y., Tsiatouhas, Y. and Arapoyanni, A., Comparative study of different current mode sense amplifiers in submicron CMOS technology, IEE Pro. Circuits, Devices and Systems, vol. 149, no. 3, pp154-158, June 2002. [8] P.Y. Chee, P.C. Liu, L. Siek, A high-speed current-mode sense-amplifier for CMOS SRAM's, Proceedings of 35th Midwest Symposium on Circuit and System, vol. 1, pp620-622, Aug. 1992. [9] P.Y. Chee, P.C. Liu, L. Siek, High-speed hybrid current-mode sense amplifier for CMOS SRAMs, ELECTRONICS LETTERS, vol. 28, no. 9, April 1992. [10] Jinn-Shyan Wang, Hong-Yu Lee, A new current-mode sense amplifier for lowvoltage low-power SRAM design, Eleventh Annual IEEE International Proceeding of ASIC, pp.163-167, Sep. 1998. [11] S.M. Wang and C. Y. Wu, Full current-mode techniques for high-speed CMOS SRAMs, IEEE International Symposium on Circuit and Systems, vol. 4, pp.IV580IV582, May 2002.
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