International Journal of Electronics and Computer Science Engineering Available Online at www.ijecse.

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977

ISSN- 2277-1956

A Voltage Controlled Oscillator using Ring Structure in CMOS Technology

Mrs. Devendra Rani , Prof. Sanjeev M. Ranjan Department .of Electronics & Telecommunication. Affiliated by CSVTU, Bhilai. Disha Institute of Management & Technology, Raipur (C.G.), India d.rani.devangan@gmail.com Abstract: Voltage-Controlled Ring Oscillators are crucial components in many wireless communication systems. The goal of this project is to design a high speed and lower power consumption, a voltage controlled oscillator (VCO), based on ring oscillators in 250nm CMOS technology, which provides a frequency of 2.4GHz. This CMOS based VCO is used for high speed wireless communication applications. A design of VCO includes delay cell, bias circuitry, and tuning circuitry using Tanner 13.0v software. I. INTRODUCTION Voltage-Controlled Oscillator or VCO is an electronic oscillator designed to be controlled in oscillation frequency by a voltage input. The frequency of oscillation is varied by the applied DC voltage. A voltage controlled oscillator (VCO) is one of the important basic building blocks in analog and digital circuits as like in PLL (phase lock loop). The Complementary-Metal-Oxide-Semiconductor (CMOS) is the most popular technology for the modern integrated circuit design and fabrication. Based on this technology, a VCO can be implemented by the LC resonant or Ring structure. In LC resonant structure the cost of chip area and the complexity of the fabrication process are increased and not suitable for a design wide tuning band VCO. The phase noise performance dependency on the quality factor of on-chip spiral inductors. In this paper a ring based VCO is design which has Small chip area, low power consumption and Suitable for wide tuning band VCO. A ring VCO is designed with cross-coupled PMOS transistors to improve phase noise characteristics. The aim of this project is to design a Voltage controlled oscillator in 250nm with lower power consumption. For circuit simulation we set the supply voltage up to 2.5V, and the power consumption up to 5mw.Although the prospect of application of ring oscillators is promising, they will not gain the popularity without improving the phase noise performance. Yet, it is inevitable to increase the power dissipation to reduce phase noise using conventional ring oscillators. The aim of this is to explore a structure of ring oscillators to solve this problem. In order to overcome this trade-off and reduce phase noise without increasing power dissipation, ring oscillators with stacked structure are used and presented. Different phase noise models and design implications for each model are studied as well. The theoretic analysis and simulations illustrated in this thesis show that a phase noise reduction of 3 dbc/Hz can be achieved with lower power dissipation. An oscillators working at 2.4ghz is designed with a 250 nm CMOS technology Ring based Voltage controlled oscillator has two types as [1]. A. Single-End Signal Ring VCO:

Figure 1: Single-End Signal Ring VCO

D1 to Dn represents the delay cells, which provide the gain and phase shift. They construct a close loop by cascading all stages.

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Mrs. Devendra Rani and Prof. Sanjeev M. Ranjan

B. -Differential Loop Ring VCO:

Figure 2:3 stage differential ring VCO

The differential ring oscillator is widely used, since it has a differential output to reject common-mode noise, power supply noise and so on. In this VCO a differential type is used. As from figure2, if it has N stage than N stage ring oscillator realized using differential cells (which have complementary output).A source coupled pair (SCL) inverter will be a typical implementation. Assume that at time t0 the output of stage 1 changes to logic 1.when this logic 1 propagates to the end, it creates a logic 1 at the Nth stage, which, when feedback to the input of the first stage, creates a logic 0 in the first stage output. When this logic 0 is propagating through the chain, it toggles the output of stage 1 trigger next stage. It takes two passes through the chain to complete a period. Denoting tp as the propagation delay through each stage, then period T=2Ntp.for a single ended output cell, N has to be odd, but for a differential cell N can be odd/even, to start an oscillation.

Figure3. Fundamental Frequency

Phase noise: The ideal VCO will provide only one pure sinusoidal wave, but in reality, the periodic signal from the VCO would contain other frequency signals that can be random or not. As figure: 3 shows [2]

Figure 4: phase noise

From slow Slow-slewing Saturated Delay Cell, we assume that the noise is dominated by thermal noise in transistor M1 and M2. II. DESIGN CONSIDERATION A. Delay cells: There are many features that differentiate the delay cell used in ring oscillator. The most important is slew time that determines the overall phase noise performance. There are three categories of delay cell. [5]First is fast-

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979 A Voltage Controlled Oscillator using Ring Structure in CMOS Technology

slewing saturated delay cell. This delay cell has fast rise and fall time. It also performs full switching and therefore belongs to the saturated class of delay cell. The second type of delay cell is a slow slewing saturated delay cell. Here the inverter consists of a source of a source coupled pair (SCP) and hence this is a current based inverter. It is called slow slewing because it has a longer gate delay. The third type of delay cell is non saturated delay cell. This is also a voltage inverter based delay cell. In this delay cell some transistors are never on/off as a result output waveform never reach Vdd or ground, which is why this type of delay cell is called non saturated. In this paper a slow slewing saturated delay cell is used which is shown in figure 4[3] The overall architecture consisting of the bias circuitry, delay cell and a tuning circuit

Figure 5: Slow-slewing Saturated Delay Cell [3]

III. CMOS 250NM PARAMETERS TABLE-1

Vt k Cox PMOS -0.43 V -111.9 A/ Cox= = NMOS 0.64V -26.5 A/

A. Design of Delay cell: Following the steps from section 8.4.2 of VLSI for Wireless Communications written by Professor Bosco Leung, we chose N = 3 to minimize the number of components used. We will design the VCO to consume 5mW. Using the formula for power specification, [5] Power = N x Ibias x Vdd = 3 x Ibias x 2.5V = 5mW, We obtain Ibias = 0.666mA The equivalent resistance for M3 is given by,

Now, we can determine the size ratio (W/L)3 of M3.since M3 is to be biased in triode, we use the triode equation:

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IJECSE,Volume1,Number3
Mrs. Devendra Rani and Prof. Sanjeev M. Ranjan

VGS3 must be high to bias M3 in deep triode, hence, an initial value of | | = 2V is chosen. When M3 is biased at the midpoint of the VDS3 vs. ID3 curve, |VDS3| = Vswing/2 =0.75V. Substituting all values in the above equation, we obtain (W/L)3 = (5113.25nm/250nm) The frequency of the VCO depends on the width of the source coupled pair, M1 and M2 of the delay cell. In general, , Where tp=RCl ln2 Cl is the loading capacitance, its value depends on the size of the source coupled pair in the current delay cell, the size of the SC pair in the next delay cell, and the size of the triode biased PMOS, M3. =0.04PF Cl Cgs(M1) = Hence, (W1/L1) = (32.116m/250nm) = Cgs (M1) (assumption) =

Figure 6: Delay Cell schematic

B. Design of Bias circuitry: A replica bias scheme is implemented to maintain a constant Vswing. Although the design of a replica bias is more complicated than a constant bias scheme, the use of a replica bias allows the VCO to be less susceptible to process variations, noise on the power supply, and temperature variations. This is accomplished by designing PBIAS to fluctuate correspondingly with Id of M3, and NBIAS to fluctuate correspondingly with Ibias. In other words, a replica bias ensures the voltage drop across M3 and M4, and the voltage drop across the current source to remain at a constant, despite fluctuations in Itail. Since the VCO is designed to operate at a high frequency within a narrow frequency range, a replica bias is essential for a robust design. Since a low voltage rail of 1V is used, we are unable to design a cascoded NMOS current source in the delay cell. Hence, we have only used one NMOS to create a current source. The approximations and hand calculations used in designing the bias circuitry are as follows: Referring to Figure 8.18 of VLSI for Wireless Communications, and applying a simple KVL in the bias circuitry, we obtain Vdd Vgs9- Vgs14 = RIbias/2 Since we know M3 must be in deep triode, we set Vgs9 = 1.6V much larger than Vgs14=0.8V, which is just enough to turn M14 on. Hence, R = 9609.60 Vov9 = Vgs9 Vtp = 1.6v-0.43V=1.17V

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981 A Voltage Controlled Oscillator using Ring Structure in CMOS Technology

Vov14 = Vgs14 Vtn = 0.8V-0.64V=0.16V=Vov6 M14, M9, and M6 must be in saturation. Hence, we can use the following formulas to determine the size of all three transistors.

The calculated sizes are (W/L)14 = (29.06um/250nm), (W/L)9= (2.29um/250nm), and (W/L)6 = (54.65um/250nm). Note that the sizes of M14 and M6 are especially large in order to keep both transistors in saturation with a low Vgs of 0.8V. Hence, the PBIAS = Vdd Vgs9 = 2.5V 1.6V = 0.9V and NBIAS = Vgs14 = 0.8V.

Figure 7: Bias circuitry schematic

C .Design of tuning circuitry: We chose Vtune_max = 1V and Vtune_min = 0V for ease of use. The corresponding gain of the VCO is given by

-516MHz/V The size of M7 and M8 can be determined by the following relation = Hence, Itune_max =78.355A/V 1V = 78.355A Since Itune_bias must be larger than Itune_max, we set Itune_bias = 82A. Finally, to determine the size of M7 and M8,

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IJECSE,Volume1,Number3
Mrs. Devendra Rani and Prof. Sanjeev M. Ranjan

(W/L)7=0.0976 = (706.33nm/250nm) However, the minimum width allowed for 250nm technology is 0.3um. Hence, we will scale W7 up by a factor of 10, and adjust the gain of the current mirror M11 to M12 to obtain the correct Itune_bias. Since M7 and M8 were scaled by a factor of 10, we must scale Itune_bias also by a factor of 10, and design 10(W/L)11= (W/L)11 to obtain the appropriate Itune. The size of the PMOS current source of the tuning circuit is obtained by:

Where Itune_bias = 10 x 82A = 820A, |Vgs| = |PBIAS-Vdd| = |0.9V 2.5V| = 1.6V. Therefore, (W/L)Ptune_bias = (11.302um /250nm). For M11 and M12, we arbitrarily choose (W/L)11 = 0.3m and (W/L)12 = 3.0m.

Figure 8: Tuning circuitry schematic

IV. CIRCUIT IMPLEMENTATION However, we made significant modifications based on parametric simulation results. The modifications made and the actual implementation of the VCO is discussed in this section of the report.. According to the previous section, the VCO is composed of three delay cells, a bias block, and a tuning block.

Tuningng Biasin g

Figure 9- 3 Delay cell with bias and tuning block

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983 A Voltage Controlled Oscillator using Ring Structure in CMOS Technology

V.

SIMULATION OUTPUT

Figure 10 shows the single ended Vout+ and Vout- waveform of VCOwhich produces the frequency of range 1.884GHz to 2.4GHz. The frequency of oscillation and the performance of the tuning circuit was thoroughly described

Figure 10: Single-Ended swing of VCO output

V. CONCLUSION The design of our Voltage Controlled Oscillator (VCO) was implemented using a three stage ring oscillator. A slow-slewing saturated topology was used for all three delay cells of the ring oscillator. From circuit simulations, the oscillating voltage swing is close to 2V. The output frequency varies from 1.884GHz to 2.4GHz by adjusting the tuning voltage from 0.6-1.0V.Therefore; we have met or exceeded all project specifications. VI. REFERENCES
[1]. Design of low-voltage wide tuning range cmos multipass voltage-controlled ring oscillator by jie ren, dalhousie university halifax, nova scotia march 2011 [2]. Jitter in Phase-Locked Loops by John McNeill, Worcester Polytechnic Institute [3]. Leung, Bosco, VLSI for Wireless Communication Prentice Hall, 2002. [4]. Paper of Han-Woong Son A Fully Integrated Fractional-N Frequency Synthesizer for Wireless communications . Georgia Institute of Technology April 2004 [5]. Design of ring oscillator based VCOwritten by George Lee, Professor Leung March 29, 2005 [6]. B. Razavi, Monolithic Phase-locked Loops and Clock Recovery Circuits: Theory and Design, IEEE Press, 1996 [7]. B. Razavi, RF Microelectronics, Upper Saddle River, NJ (USA): Prentice Hall, 1998. [8]. DESIGN OF CMOS RING OSCILLATORS WITH REDUCED PHASE NOISE by JIAWEI REN. University of Guelph, 2010 [9]. T. Lee, The design of CMOS radio-frequency integrated circuits. Cambridge University Press, 1998. [10]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 31, NO. 3, MARCH 1996 331 A Study of Phase Noise in CMOS Oscillators Behzad Razavi, Member, IEEE.

ISSN 2277-1956/V1N3-977-983