Regras de Projeto AMS CMOS 0.35

Austria Mikro Systeme International AG
Schlo Premsttten A-8141Unterpremsttten Austria Tel (++43) 3136-500 Fax (++43) 3136-52501 Fax (++43) 3136-53650 Email rules@amsint.com
0.35 m CMOS Design Rules

7 Digit Document #: 9931032 Revision #: 2.0
Document control Controlled Copy #
Strictly Controlled

Version History
Version 1.0 = Rev. N/C 2.0 1. Change version control (A -> 2.0) 2. Guideline: Ratio of POLY1 area to die area 3. Changed Minimum pad pitch Description
Process Family
This document is valid for the following twin-tub 0.35 m processes: process name CSA CSD CSF CSI
)
no. of mask layers 13 14 14 15
CMOS core module x x x x
poly capacitor module x
5 Volt option
x x x
p-substrate, triple metal, single poly, 3.3 Volt
Related Documents
0.35 m CMOS Process Parameters: Doc. 9933016 ESD Design Rules: Doc. 9931020 Standard Family Cells: Doc. 9931021 Assembly Related Design Rules: Doc. 9981005
Note
All data represent drawn dimensions. Graphical illustrations are not to scale.
Support
Technical questions on design rules should be directed to the following department: Process Characterization: e-mail: rules@amsint.com fax: (*43) 3136 500 491 phone: (*43) 3136 500 618
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0.35 m CMOS Design Rules Table of Contents

1. 2. 3. 4. Denitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Process Layer Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Structure Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1. 4.2. 4.3. 4.4. 4.5. 4.6. 4.7. 4.8. 4.9. NDIFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PDIFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MIDOX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4 6 7 8 8 8 9
POLY1, GATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 POLY2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 CONT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 MET1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 VIA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 MET2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.10. VIA2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.11. MET3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5. Element Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.1. 5.2. 5.3. 5.4. 5.5. 5.6. 5.7. 6. NMOS, PMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 NMOSM, PMOSM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 CPOLY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 RPOLY2, RNWELL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 NMOSH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 VERT10, LAT2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 SUBDIODE, WELLDIODE, NWD . . . . . . . . . . . . . . . . . . . . . . . . 23
Periphery Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.1. 6.2. 6.3. PAD Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 CORNER Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 SCRIBE Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7. 8.
Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Recommended Layout Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
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0.35 m CMOS Design Rules 1. Denitions

Mask Layers
NTUB DIFF FIMP MIDOX POLY1 POLY2 NPLUS PPLUS CONT MET1 M1HOLE VIA MET2 M2HOLE VIA2 MET3 M3HOLE PAD Note: WN DF IF XM P1 P2 IN IP CT M1 M1 VI M2 M2 V2 M3 M3 PA := := := := := := := := := := := := := := := := := := n-tub layer diffusion layer n-eld implant layer mid gate oxide layer (VGATE 3:3V olt) poly1 layer poly2 layer n+implant layer p+implant layer contact layer (connects MET1 to DIFF, POLY1, POLY2) metal1 layer metal1 slot (metal1 = MET1 and not M1HOLE) via1 layer (connects MET2 to MET1) metal2 layer metal2 slot (metal2 = MET2 and not M2HOLE) via2 layer (connects MET3 to MET2) metal3 layer metal3 slot (metal3 = MET3 and not M3HOLE) pad layer
The 2-character symbols are used for short rule names.
Denition Layers
These layers are not used in chip production. They are necessary for design tools, e.g. design rule check. CAPDEF := DIFCUT := DIODE := PO1CUT := PO2CUT := RESDEF := RESTRM := SFCDEF := ZENER := denes sandwich capacitors excludes DIFF from device extraction marks protection diodes for device extraction excludes dummy POLY1 from device extraction excludes dummy POLY2 from device extraction resistor denition layer resistor terminal layer excludes SFC from checks and automatic layer generation excludes Zener diodes from checks and automatic layer generation
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Structures
DIFFCON DIFFM NDIFF (DN) NDIFFCON PADVIA1 PADVIA2 PDIFF (DP) PDIFFCON POLY1CON POLY2CON PSUB SCRIBE SCRIBECUT SFC WIDE_MET1 WIDE_MET2 WIDE_MET3 := := := := := := := := := := := := := := := := := diffusion contact (CONT & DIFF) diffusion for 5 volt operation (DIFF & MIDOX) n+diffusion (DIFF & NPLUS) n+diffusion contact (CONT & NDIFF) VIA underneath PAD (VIA & PAD) VIA2 underneath PAD (VIA2 & PAD) p+diffusion (DIFF & PPLUS) p+diffusion contact (CONT & PDIFF) poly1 contact (CONT & POLY1) poly2 contact (CONT & POLY2) p-substrate scribe line border (Peripheral bus + scribe edge, example in SFC) scribe line border cut (example in SFC) standard family cells MET1 width and length 10 m MET2 width and length 10 m MET3 width and length 10 m
Elements
CORNER := CPOLY := LAT2 := SUBDIODE := NMOS := NMOSM := NMOSH := NWD := WELLDIODE := PMOS := PMOSM := RDIFFP3 := RNWELL := RPOLY2 := VERT10 := corner cell with slotted metal busses poly1-poly2 capacitor (POLY1 & POLY2) lateral PNP transistor (2 m x 2 m emitter) parasitic n+p- diode (NDIFF & PSUB & DIODE) n-channel MOSFET n-channel MOSFET with mid gate oxide high voltage n-channel MOSFET parasitic n-p- diode (NTUB & PSUB & DIODE) parasitic p+n- diode (PDIFF & NTUB & DIODE) p-channel MOSFET p-channel MOSFET with mid gate oxide p+diffusion resistor in periphery cells (PDIFF & RESDEF) n-tub resistor (NTUB & RESDEF) poly2 resistor (POLY2 & RESDEF) vertical PNP transistor (10 m x 10 m emitter)
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Geometric Relations
A width A spacing to B A notch A enclosure of B A extension of B A overlap of B Note: WnA SnAB SnAA EnAB EnAB OnAB := := := := := := distance inside_A - inside_A distance outside_A - outside_B (different polygons) distance outside_A - outside_A (same polygon) distance inside_A - outside_B (A contains B) distance inside_A - outside_B (A may intersect B) distance inside_A - inside_B
The abbreviations are intended for short design rule names.

width spacing A notch A B
overlap
overlap
A enclosure of B
A extension of B
A extension of B not violated B enclosure of A violated
2. General Requirements
RUL001 RUL002 RUL003 Grid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.05 m Corners . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 , 135 Data extrema including SCRIBE. . . . . . . . . . . . . . . . . . . . . . . . . . integral multiple of 5 m
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0.35 m CMOS Design Rules 3. Process Layer Overview

Note: Width and spacing are minimum values in m.
rule# yWN yIF yDF yXM yP1 yIN yIP yP2 yCT yM1 yVI yM2 yV2 yM3 yPA
GDS# width spacing / notch N1y W1y S1yy Mask Layers NTUB 5 2.0 3.0 FIMP 8 DIFF 10 0.5 0.6 MIDOX 14 0.6 0.6 POLY1 20 0.3 0.6 NPLUS 23 0.6 0.6 PPLUS 24 0.6 0.6 POLY2 30 0.7 0.5 CONT 34 0.4 0.5 MET1 35 0.4 0.6 VIA 36 0.5 0.5 MET2 37 0.5 0.6 VIA2 38 0.5 0.5 MET3 39 0.5 0.7 PAD 40 15.0 15.0 M1HOLE 57 M2HOLE 58 M3HOLE 61 Denition Layers SFCDEF 42 ZENER 43 DIFCUT 44 PO1CUT 45 PO2CUT 46 DIODE 47 RESDEF 49 RESTRM 50 CAPDEF 55
layer
generation
drawn =NTUB (except SFC) drawn drawn drawn drawn drawn drawn drawn drawn drawn drawn drawn drawn drawn MET1 slots MET2 slots MET3 slots SFC Zener diodes non-standard DIFF non-standard POLY1 non-standard POLY2 parasitic diodes resistors resistor terminals sandwich capacitors
e.g.: MET1 width = W1M1, MET1 spacing = S1M1M1.
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0.35 m CMOS Design Rules 4. Structure Rules

4.1. NDIFF S1INIP E1INDF S1DFIP Overlap of NPLUS and PPLUS is not allowed (except ZENER)
BAD1DF DIFF without NPLUS or PPLUS is not allowed (except ZENER) Minimum NPLUS extension of DIFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 m Minimum DIFF spacing to PPLUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 m
S1DNWN Minimum NDIFF spacing to NTUB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 m E1WNDN Minimum NTUB enclosure of NDIFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.2 m
E1WNDN E1INDF NPLUS NDIFF NPLUS NDIFF PPLUS
NTUB
S1DNWN
S1DFIP
4.2. PDIFF E1IPDF S1DFIN Minimum PPLUS extension of DIFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 m Minimum DIFF spacing to NPLUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 m
S1DPWN Minimum PDIFF spacing to NTUB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.4 m E1WNDP Minimum NTUB enclosure of PDIFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 m BAD2DF NDIFF and butting PDIFF must be connected with MET1
E1IPDF PPLUS PDIFF NPLUS
NTUB PPLUS S2DFDF NPLUS
S1DFIN E1WNDP PDIFF NDIFF S1DPWN MET1
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4.3. MIDOX
E1XMDF Minimum MIDOX enclosure of DIFFM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.6 m S1DFXM Minimum MIDOX spacing to DIFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.6 m S2DFDF Minimum DIFFM spacing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0 m
S2DFDF MIDOX
111 1111 000 1111 0000 111 0000 000

mid oxide mid oxide E1XMDF S1DFXM
DIFFM
DIFFM
DIFF POLY1
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4.4. POLY1, GATE S2P1P1
Minimum GATE spacing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.7 m
S1DFP1 Minimum POLY1 spacing to DIFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 m E1P1DF Minimum POLY1 extension of GATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.4 m E1DFP1 Minimum DIFF extension of GATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.7 m E1DNP1 Minimum NDIFF extension of GATE when butted to PDIFF . . . . . . . . . . . . . . . . 0.6 m E1DPP1 Minimum PDIFF extension of GATE when butted to NDIFF . . . . . . . . . . . . . . . . 0.6 m R1P1 Maximum ratio of POLY1 area to touched GATE area . . . . . . . . . . . . . . . . . . . . . . . . 100
Note: POLY1 structures collect electric charge during ion-etching which can be a hazard for associated GATE oxide.
A(POLY1) A(GATE) POLY1 POLY1 S1DFP1 GATE E1P1DF S2P1P1 E1DFP1
R1P1
POLY1 GATE
POLY1 GATE PDIFF
DIFF
NDIFF
E1DNP1
E1DPP1
PDIFF
NDIFF
4.5. POLY2 BAD1P2 POLY2 is not allowed over DIFF S1DFP2 Minimum POLY2 spacing to DIFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 m S1P1P2 Minimum POLY1 spacing to POLY2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.7 m
111 000 111 000

DIFF
POLY2
POLY1
S1DFP2
S1P1P2
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4.6. CONT BAD1CT CONT without MET1 is not allowed BAD2CT CONT without DIFF or POLY1 or POLY2 is not allowed BAD3CT POLY1CON is not allowed over DIFF W2CT
Fixed CONT size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.4 m x 0.4 m
E1M1CT Minimum MET1 enclosure of CONT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.1 m E1DFCT Minimum DIFF enclosure of CONT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 m E1P1CT Minimum POLY1 enclosure of CONT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.2 m E1P2CT Minimum POLY2 enclosure of CONT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.6 m S1CTP1 Minimum DIFFCON spacing to GATE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.4 m S1CTDP Minimum NDIFFCON spacing to PDIFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.4 m S1CTDN Minimum PDIFFCON spacing to NDIFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.4 m
Note: Butting CONTs are not allowed.
S1CTDF Minimum POLY1CON spacing to DIFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.4 m S1CTP2 Minimum POLY1CON spacing to POLY2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 m
S1CTDF E1DFCT S1CTP1 E1P2CT
CONT W2CT E1M1CT MET1 POLY1 NDIFF S1CTDP E1P1CT POLY2 S1CTP2 POLY1
S1CTDN PDIFF
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4.7. MET1
S2M1M1 Minimum MET1 spacing to WIDE_MET1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0 m
MET1
WIDE_MET1 >10 m >10 m
S2M1M1
R1M1 R2M1
Minimum ratio of MET1 area to die area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 % Maximum ratio of MET1 area to connected GATE and CPOLY area . . . . . . . . . . 100
Note: MET1 structures collect electric charge during ion-etching which can be a hazard for associated GATE and CPOLY oxide. Only MET1 without DIFFCONs must be considered. MET1 connected to GATE or CPOLY via MET2 and shorted CPOLY does not contribute.
11 00 11 00 11 00
DIFF A
11111 00000 11111 00000 00000 11111

CPOLY C MET1 POLY1 MET1 VIA1 MET1
POLY1
CPOLY E POLY1 MET2
CONT
DIFFCON
11 00 11 00
DIFF
POLY1
MET1 F DIFF R2M1:area(B+D) / area(A+C+E) F and G do not contribute
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20 m 300 m
BAD1M1 Insert slots in MET1

Note:
Insert M1HOLEs in direction of current ow. Standard cells do not contain M1HOLEs.
W2M1 W3M1
Minimum M1HOLE width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0 m Minimum M1HOLE length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.0 m
S3M1M1 Minimum M1HOLE spacing on MET1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.0 m E1M1M1 Minimum MET1 enclosure of M1HOLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.0 m
MET1 M1HOLE
M1HOLE
W2M1
M1HOLE
M1HOLE E1M1M1
W3M1
S3M1M1
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4.8. VIA BAD1VI BAD2VI BAD3VI W2VI E1M1VI E1M2VI E2M1VI VIA without MET1 is not allowed VIA without MET2 is not allowed VIA over GATE is not allowed
Fixed VIA size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 m x 0.5 m Minimum MET1 enclosure of VIA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.2 m Minimum MET2 enclosure of VIA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.1 m Minimum WIDE_MET1 enclosure of VIA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.6 m
MET1 E1M2VI MET2
MET1
WIDE_MET1
VIA
E2M1VI
MET2 VIA W2VI E1M1VI
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4.9. MET2
MET2
S2M2M2
BAD1M2 Stacking MET2, MET1, POLY2, POLY1 is not allowed S1M2M1 Minimum MET2 spacing to MET1 over CPOLY . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 m S1M1M2 Minimum MET1 spacing to MET2 over CPOLY . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 m
MET2 MET1 MET2 MET1
CPOLY POLY1 S1M2M1 S1M1M2
R1M2 R2M2
Note: MET2 structures collect electric charge during ion-etching which can be a hazard for associated GATE and CPOLY oxide. Only MET2 without DIFFCONs must be considered. MET2 connected to GATE or CPOLY via MET3 and shorted CPOLY does not contribute.
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20 m 300 m

Note:
W2M2 W3M2
MET2 M2HOLE
M2HOLE
W2M2
M2HOLE
M2HOLE E1M2M2
W3M2
S3M2M2
4.10. VIA2 BAD1V2 VIA2 without MET2 is not allowed BAD2V2 VIA2 without MET3 is not allowed W2V2 Fixed VIA2 size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 m x 0.5 m E1M2V2 Minimum MET2 enclosure of VIA2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.2 m E1M3V2 Minimum MET3 enclosure of VIA2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.1 m E2M2V2 Minimum WIDE_MET2 enclosure of VIA2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.6 m
MET2 E1M3V2 MET3
MET2
WIDE_MET2
VIA2
E2M2V2
MET3 VIA2 W2V2 E1M2V2
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4.11. MET3
MET3
S2M3M3
R1M3 R2M3
Note: MET3 structures collect electric charge during ion-etching which can be a hazard for associated GATE and CPOLY oxide. Only MET3 without DIFFCONs must be considered. MET3 connected to shorted GATE or CPOLY does not contribute.

Note:
20 m 300 m
W2M3 W3M3
MET3 M3HOLE
M3HOLE
W2M3
M3HOLE
M3HOLE E1M3M3
W3M3
S3M3M3
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0.35 m CMOS Design Rules 5. Element Rules

5.1. NMOS, PMOS W2P1 W2DF
Minimum GATE length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 m Minimum GATE width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.6 m
POLY1
GATE DIFF
W2DF
W2P1
5.2. NMOSM, PMOSM W3P1 W3DF Minimum GATE length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 m Minimum GATE width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.6 m
POLY1 MIDOX GATE DIFF W3DF
W3P1
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5.3. CPOLY BAD1IN BAD1IP W2P2 S2P2P2 E1P1P2 S1INP2 S1IPP2 CPOLY is not allowed over NPLUS CPOLY is not allowed over PPLUS
Minimum CPOLY width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.8 m Minimum CPOLY spacing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.8 m Minimum POLY1 enclosure of POLY2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0 m Minimum NPLUS spacing to CPOLY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.0 m Minimum PPLUS spacing to CPOLY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0 m
S1INP2, S1IPP2
POLY1 NPLUS POLY2 CPOLY POLY2 CPOLY PPLUS
W2P2
S2P2P2
E1P1P2
Note:
See chapter 8. for recommended layout structure of CPOLY. Precision capacitor matching is improved with non-minimum POLY2 width and spacing.
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Rev. 2.0
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5.4. RPOLY2, RNWELL BAD2IN BAD2IP S2INP2 S2IPP2 RUL004
Note:
RPOLY2 is not allowed over NPLUS RPOLY2 is not allowed over PPLUS Minimum NPLUS spacing to RPOLY2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 m Minimum PPLUS spacing to RPOLY2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 m Fixed RESTRM enclosure of RESDEF edge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.1 m
Note: RESDEF and RESTRM are necessary for all resistors.
Recommended minimum number of squares. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .L/W 5
RESTRM POLY2 W 1
RESDEF
NPLUS
PPLUS S2INP2, S2IPP2
3 L
5 RUL004
RUL004
Note:
Use the following effective number of squares for resistance calculation of corners:
1/2 1
1 90
1 135
1/3 1
Note:
See chapter 8. for recommended layout structure of poly resistors.
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Rev. 2.0
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5.5. NMOSH
BULK FOX PDIFF FOX NDIFF CHANNEL SOURCE GATE DRAIN-EDGE-FOX FOX NDIFF DRAIN-WELL DRAIN FOX
PSUB
PDIFF
NDIFF WIDTH MIDOX POLY1 LENGTH
NDIFF
NTUB
Note:
The layout of NMOSH is predened and available on request. Only WIDTH may be changed.
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Rev. 2.0
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5.6. VERT10, LAT2
VERT10
COLLECTOR FOX PDIFF FOX NDIFF BASE FOX PDIFF NTUB - BASE EMITTER FOX NDIFF BASE COLLECTOR FOX PDIFF FOX
PSUB - COLLECTOR
LAT2
COLLECTOR BASE FOX PDIFF FOX NDIFF FOX PDIFF PDIFF PDIFF COLLECTOR BASE FOX NDIFF FOX PDIFF FOX EMITTER GATE GATE
NTUB - BASE
PSUB - PARASITIC COLLECTOR
Note:
The layouts of VERT10 and LAT2 are predened and available on request. They must not be changed.
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Rev. 2.0
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5.7. SUBDIODE, WELLDIODE, NWD
SUBDIODE
DIODE NDIFF
WELLDIODE
NTUB DIODE PDIFF DIODE
NWD
NTUB
PSUB
Note:
SUBDIODE, WELLDIODE, NWD are only intended for the simulation of reverse leakage currents and junction capacitances in periphery cells. It is not recommended to use these diodes as active circuit elements.
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0.35 m CMOS Design Rules 6. Periphery Rules

ESD Related Rules: See Doc. 9931020.
6.1. PAD Rules BAD1PA PAD is not allowed over DIFF BAD2PA PAD is not allowed over POLY1 BAD3PA PAD is not allowed over POLY2 BAD3V2 PADVIA2 over PADVIA1 is not allowed W2PA Bond PAD size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85.0 m x 85.0 m
Note: Test PAD size 60 m x 60 m. Probe PAD size 15 m x 15 m. Bond pads and test pads must have a minimum pitch of 100 m. The following rules are only valid for bond pads.
E1M1PA Minimum MET1 enclosure of PAD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.0 m E1M2PA Minimum MET2 enclosure of PAD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.0 m E1M3PA Minimum MET3 enclosure of PAD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.0 m E3M1VI E3M2VI Minimum MET1 enclosure of PADVIA1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0 m Minimum MET2 enclosure of PADVIA1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0 m
E3M2V2 Minimum MET2 enclosure of PADVIA2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0 m E3M3V2 Minimum MET3 enclosure of PADVIA2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0 m S2VIVI S2V2V2 S1VIV2 S1P1PA S1P2PA Minimum PADVIA1 spacing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.8 m Minimum PADVIA2 spacing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.8 m Minimum PADVIA2 spacing to PADVIA1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 m Minimum PAD spacing to POLY1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.0 m Minimum PAD spacing to POLY2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.0 m
S1DFPA Minimum PAD spacing to DIFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.0 m
S1M1PA Minimum PAD spacing to MET1 (different net) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.0 m S1M2PA Minimum PAD spacing to MET2 (different net) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.0 m S1M3PA Minimum PAD spacing to MET3 (different net) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.0 m R1VIPA R1V2PA Minimum ratio of PADVIA1 area to PAD area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 % Minimum ratio of PADVIA2 area to PAD area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 %
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W2PA E1M1PA E1M2PA E1M3PA E3M1VI E3M2VI E3M2V2 E3M3V2 S1M2PA MET2 S1M1PA MET1 VIA VIA2 MET3 PAD S1P1PA POLY1 S1P2PA POLY2 VIA / VIA2 CONT S1DFPA DIFF
MET1 / MET2 / MET3 R1VIPA R1V2PA VIA VIA2 S2V2V2 VIA2 VIA S2VIVI VIA VIA
S1M3PA
S1VIV2
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Rev. 2.0
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6.2. CORNER Rules RUL005 RUL006 RUL007 CORNER must be used for die sizes 4mm 4mm.
Note: This prevents cracks in corners of the die during thermal stress.
Insert a continous 2 m wide slot in 20 m wide MET. Draw MET and slots at 45.
MET1 MET2 MET3 RUL006
O C ER N R
RUL007
die corner
Note:
The layout of CORNER is predened and available on request.
Doc. 9931032
Rev. 2.0
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6.3. SCRIBE Rules
SCRIBE is a Standard Family Cell enclosing the design data. The inner edge of SCRIBE is butted to the data extrema of the design. The SFC SCRIBE must be included in all designs without modication. The SFC SCRIBECUT shows how to cut SCRIBE in mixed signal designs with separated supplies.
RUL008
Data extrema excluding SCRIBE . . . . . . . . . . . . . . . . . . . . . . . . integral multiple of 5 m

Note: Follows from rule RUL003 and SCRIBE width of 35.0 m.
DESIGN_DATA
(0,0)
35 m
SCRIBE
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Rev. 2.0
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0.35 m CMOS Design Rules 7. Guidelines

7.1 7.2
Connect NTUB with as much DIFFCON area as possible. Maximum DIFFCON spacing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 m Where area permits non-minimum geometries should be used.
Note: This is particularly applicable to structures where the layout allows modications without degrading circuit performance or increasing the overall size.
7.3
Minimum ratio of POLY1 area to die area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 %
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Rev. 2.0
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0.35 m CMOS Design Rules 8. Recommended Layout Structures
Precision Resistors
guardring dummy structures with PO1CUT
1 Runit
1 x Runit
1 x Runit 1 Runit
matched bends
3 x Runit
3 Runit
1 x Runit
4 x Runit 1 Runit 4 Runit
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Rev. 2.0
29 of 30

Precision Capacitors
guard ring unit cap 135 degree corners
equal area/perimeter ratio for non-unit cap
dummy structures with PO2CUT
Cunit
1.4 Cunit
Doc. 9931032
Rev. 2.0
30 of 30
0.35 m CMOS Design Rules Austria Mikro Systeme Spec. ENG - 51A Rev. 1.0

Schlo Premsttten A-8141Unterpremsttten Austria Tel (++43) 3136-500 Fax (++43) 3136-52501 Fax (++43) 3136-53650 Email rules@amsint.com
0.35 m CMOS Design Rules Attachment

7 Digit Document #: 9931032 Revision #: 2.0
Page 1 / 2
Release Date 28.07.00 00:00:00
0.35 m CMOS Design Rules Austria Mikro Systeme Spec. ENG - 51A Rev. 1.0
Attachment to 7. Guidelines
7.4 Precision analog NMOS, PMOS, NMOSM, PMOSM should not be covered with MET1 or MET2. If this is not possible MET1 and MET2 covering of matching transistors should be identical. Minimum channel length for critical analog NMOS transistors . . . . . . . . . . . . . . 0.6 m Minimum channel length for critical analog NMOSM transistors . . . . . . . . . . . . 1.0 m
Note: Critical analog NMOS and NMOSM transistors are: 1. Transistors biased at (V th < VGS < VDS /2, VDS = VDSmax ). Low temperature applications are especially critical. 2. Transistors used in circuits sensitive to Vth shift.
7.5
Page 2 / 2
Release Date 28.07.00 00:00:00

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0.35 m CMOS Design Rules

Document control Controlled Copy #

0.35 m CMOS Design Rules

Austria Mikro Systeme International AG

no. of mask layers 13 14 14 15

CMOS core module x x x x

poly capacitor module x

p-substrate, triple metal, single poly, 3.3 Volt

0.35 m CMOS Design Rules Table of Contents

Austria Mikro Systeme International AG

Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Recommended Layout Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

0.35 m CMOS Design Rules 1. Denitions

Austria Mikro Systeme International AG

The 2-character symbols are used for short rule names.

0.35 m CMOS Design Rules

Austria Mikro Systeme International AG

0.35 m CMOS Design Rules

Austria Mikro Systeme International AG

The abbreviations are intended for short design rule names.

A extension of B not violated B enclosure of A violated

0.35 m CMOS Design Rules 3. Process Layer Overview

Austria Mikro Systeme International AG

e.g.: MET1 width = W1M1, MET1 spacing = S1M1M1.

0.35 m CMOS Design Rules 4. Structure Rules

Austria Mikro Systeme International AG

NTUB PPLUS S2DFDF NPLUS

S1DFIN E1WNDP PDIFF NDIFF S1DPWN MET1

0.35 m CMOS Design Rules

Austria Mikro Systeme International AG

111 1111 000 1111 0000 111 0000 000

0.35 m CMOS Design Rules

Austria Mikro Systeme International AG

Minimum GATE spacing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.7 m

POLY1 GATE PDIFF

111 000 111 000

0.35 m CMOS Design Rules

Austria Mikro Systeme International AG

Fixed CONT size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.4 m x 0.4 m

0.35 m CMOS Design Rules

Austria Mikro Systeme International AG

S2M1M1 Minimum MET1 spacing to WIDE_MET1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0 m

WIDE_MET1 >10 m >10 m

11111 00000 11111 00000 00000 11111

CPOLY E POLY1 MET2

MET1 F DIFF R2M1:area(B+D) / area(A+C+E) F and G do not contribute

0.35 m CMOS Design Rules

Austria Mikro Systeme International AG

BAD1M1 Insert slots in MET1

Minimum M1HOLE width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0 m Minimum M1HOLE length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.0 m

0.35 m CMOS Design Rules

Austria Mikro Systeme International AG

MET1 E1M2VI MET2

MET2 VIA W2VI E1M1VI

0.35 m CMOS Design Rules

Austria Mikro Systeme International AG

S2M2M2 Minimum MET2 spacing to WIDE_MET2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 m

WIDE_MET2 >10 m >10 m

CPOLY POLY1 S1M2M1 S1M1M2

0.35 m CMOS Design Rules

Austria Mikro Systeme International AG

BAD2M2 Insert slots in MET2

Minimum M2HOLE width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 m Minimum M2HOLE length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.0 m

Recommended minimum number of squares. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .L/W 5