November 2,1999

AN4102 C-TV Flyback Type SMPS with SPS

Jeong-Yul Yun

Abstract
Until now, most of the power supply for electronic products were the switching mode power supply. As a product that combined the control IC and the MOSFET, both used in the switching mode power supply, into one package, the SPS attempts to include the maximum number of external components to reduce the surrounding components as much as possible. It also strengthened its protection function. The SPS is available in all SMPS from small power supplies such as the charger to large power equipments such as adapters, printers, PCs and monitors. Especially, the SPS (KA3S series) (herein called SPS) described in this note is especially appropriate for the quasi resonant power supply used mostly in color TVs and is being sold through recent production. The SPS is classifed according to the voltage and current rating of the equipped MOSFET. The 5 types in the KA3S series, 800V (6A, 8A) and 650V (7A, 9A, 12A), developed to present are based on these ratings. Generally, the yback or forward method power supply used most widely in general electronic products employ the xed frequency hard switching method. For monitors and other TV-like displays, this noise directly affects the display quality. This why the quasi resonant yback switching is required. The quasi resonant-type operation is appropriate for TVs, monitors, VCR-like displays and related products because it greatly reduces the switching noise from dv/dt by using the snubber capacitor added between the MOSFET drain and source to extend the switch's turn off time. Furthermore, this method reduces switching loss by turning on the SPS when the voltage across is minimum or zero. The switching frequency of the SPS for TV is determined according the external SYNC circuit through SPS #5 pin, S/S (SYNC & SOFT START). According input AC line voltage and load conditions, the frequency is made to vary through the SYNC circuit; this minimizes the display noise. If the voltage of the SPS #5 pin has not reached Vsyth (typ. 6.4V), then, it switches at the internally set 20kHz frequency. Recently, TV manufacturers are worrying about having to meet the regulation on stand-by power consumption (i.e. Energy star in U.S.A.) The SPS executes the Burst Mode operation in which the SPS switching for a xed interval and stops and repeats this type of intermittent switching to reduce the switching loss which, in turn, reduces the standby power. This Burst Mode opertion can be implemented to satisfy the standby power regulation without having to add many components.The BURST MODE operation is vital to minimizing the switching loss in the standby state. To reduce the EMI generated during switching, the SPS is designed with much lower switching speed than that which drives the general MOSFET. It is designed to have a switching speed which disregards the IC input voltage, VCC.

Rev C, November 1999

In this perspective, not only is the SPS for the TV well-suited for making a low cost, high performance power supply but also, using few components, to satisfy the standby power consumption regulation.

1. Important Characteristics
Current Mode Control Quasi-Resonant Operation, Minimum Voltage Switching Low EMI emmision Substitutable for FREE VOLTAGE Power Input Auto Restart after Shutdown Optimum Gate Driver Design Low Standby Power Consumption (BURST MODE OPERATION) Various Protection Circuits Overvoltage protection Overload Protection Thermal shutdown Overcurrent Protection

2. Why the general yback method is inappropriate for the TV power supply
In the general yback power supply, resonance is mainly generated between the transformer primary inductance and the capacitance, which exists between MOSFET drain-source, after the MOSFET turns off. The instant the MOSFET primary switch turns on, the high voltage charged in the drain-source capacitor temporarily discharges, generating a large current spike. In the ideal case, the drain-source maximum and minimum voltages are as follows: Vdsmax = Vdc+(Np/Ns)*Vo Vdsmin = Vdc-(Np/Ns)*Vo Np: Number of transformer primary turns Ns: Number of transformer secondary turns Vo: Output Voltage Vdc: Voltage of the rectied AC line (DC link capacitor voltage) When the MOSFET turns on, a very complex waveform appears and will be affected by the transformer leakage inductance, MOSFET drain-source capacitance and reverse recovery current of the secondary diode etc. If it turns on at a very high voltage, a very large current spike, generated as the drain-source capacitor discharges, produces noise. The quasi resonance operation executes minimum or zero voltage switching to reduce this noise.

Rev C, November 1999

3. Application Circuit Diagram of TV-use SPS (Figure 17)

The power supply circuit for TV with the KA3S SERIES is composed of the rectier, which recties the active power supply line, transformer, start-up circuit, SYNC circuit and feedback circuit. Its secondary side is the same that of the general yback circuit. Unlike the general yback and forward power supply which uses the RCD snubber circuit the power supply circuit with the KA3S series SPS uses the capacitor between the drain and source as the snubber circuit. TVs have many secondary side output voltages, but 125V used for horizontal deection and 15V low voltage used as power to sound or other signal processing ICs are the two basic ones. The feedback voltage (FB) is peak MOSFET drain current. Namely, if the FB voltage increases so does the SPS duty; the secondary side receives more energy which increases the output voltage. When the FB voltage decreases, the reverse occurs. Two resistors in Figure 15 (VR1+R11, R12) are connected between the output voltage and GND. The resistance of the resistors should be adjusted such that the REF pin equals 2.495V (TYP) when the output voltage divide is performed. The results of actual testing show that about 300k resistor between the output voltage and the REF PIN and few kW resistor between the REF PIN and GND is appropriate for TV. The capacitor and resistor C10, R8 between the KA431 Q1 cathode and REF pin are selected based on the entire system response, but, on the whole, it is best to use a few nf capacitors and few hundreds kW resistors to make the product of these constants 5-10 times 3k * Cfb. As reference, the constants of the 20 inch C-TV demo board circuit are attached at the end of this note.
Icc [mA] Iop STOP START UP

Power On Reset Range

Ist 6V 10V 15V

Vcc Vz [V]

Figure 1. Start-Up Operation If the Vdc voltage divided by resistance of the start-up resistor results in current larger than the SPS start-up current, then, this start-up resistor is selected. Two start-up resistors are used to reduce the Set failure due to the error of resistor breakdown voltage and to reduce the Set failure related to the Surge. Furthermore, it is best to use two small capacity resistors connected in series. In SPS initial start-up operation, the start-up current, owing from the Vdc and through the resistor, charges the VCC capacitor. If the VCC voltage becomes greater than the start-up voltage of 15V, the SPS starts switching the internal MOSFET. Once the MOSFET starts to switch, the current in the SPS control IC abruptly increases to 12mA, which makes it difcult to operate with just the current owing through the start-up resistor is difcult. Therefore, after start-up, the transformer VCC windings supply most of the SPS consumption power. If the VCC power capacitor becomes too large, the start-up time is longer; therefore, an appropriate size capacitor (in operating is 22~47F in operation) is be set. Figure 1 describes this operation. At start-up, the VCC only needs to be maintained at 10V. However, the VCC must be set (about 16~20V) such that OVP (min. VCC voltage above 23V) does not operate in the transient state.
Rev C, November 1999

4. Quasi Resonant Circuit Operation

The TV power source circuit has two modes. The rst mode is the standby state, and the other is the normal operation state. When switching starts, the SYNC winding voltage of the VCC, similar in shape to the drain-source voltage, charges the SYNC circuit capacitor. As a result, the S/S voltage (#5 pin) greatly increases during yback time. When this S/S PIN (#5 pin) voltage exceeds the SYNC reference voltage (6.4V) and the decreases, the SPS starts. By controlling the SYNC circuit time constants, Vds becomes minimum turning on the switch, thus, reduce the current spike and switching loss. The snubber capacitor can reduce the snubber voltage spike due to the leakage inductance and this reduces the EMI. If the snubber capacitor is too large, the switching loss increases and the standby consumption power increases, but, if too small, the increasing switching noise at turn-off becomes a problem. Though the power supply would be better explained through an equivalent circuit, which considered all the output terminals of the TV power supply, it will be explained assuming having one output for it is that way, in principle. Each part of its operation according to time is examined.
VGS

VDS1

VDS

ID

Vcb

VSS Imp Im

ICR

ID2 t0 t1 t2 t3 t4 t4 t5

Figure 2. Quasi resonant waveform(Vi>Vr)

Rev C, November 1999

A: MODE I (t0 ~ t1)

Figure 3 shows the equivalent circuit when the SPS is off.
ID2 ILm + VLm + Vi IDS + VDS ID1 ICR VD2 D2 + ICO CO Lm n : 1 IO + VO -

D1

CR

Figure 3. Equivalent Circuit at MOSFET Turn-Off At t0 the MOSFET drain current is compared in the IC internal current sense comparator and the MOSFET turns off. The MOSFET gate driver terminal in the SPS is set such that its turn-on and turn-off drive characteristics do not generate noise on the display. When the MOSFET turns off, the energy stored in transformer magnetic inductance increases the equivalent output capacitor(Coss) voltage of Vds and the snubber capacitor voltage between the drain-source. Because the equivalent output capacitor (Coss) of the MOSFET is much smaller than the snubber capacitor, most of the charging current ows to the snubber capacitor. Until Vds voltage reaches the sum of the DC input voltage (Vi) and primary side winding voltage (Vr:nVo) from to the secondary side voltage at (t1), the energy stored in the transformer magnetic inductance is not supplied to the secondary side during this interval because the secondary side diode is not on. The Vds1 in Figure 2 is Vds1 = Vi + Vr (Vr = n(Vo+Vd), n: Np:Ns, Vd:diode voltage drop) The Vds voltage consists of the rectied voltage of the input voltage and converted output voltage (nVo), where n is the turn ratio. The nVO is how the primary side perceives VO. Here, the rectied input voltage, Vi, is the DC voltage having twice the AC line frequency and the secondary side voltage is almost a xed DC voltage. For this reason, the Vi voltage includes twice the ripple of the AC line frequency. During the switching period, however, Vds is assumed to be most DC voltage. The turn-off time from t0 to t1 is related to the equation below. t (t0~t1) = (Coss+Cr)*Vds1/Ids_peak (Ids_peak: drain-source current at turn-off)

Rev C, November 1999

B: MODE II (t1 ~ t2)

Figure 4 shows the equivalent circuit when the diode (D2) turns on. When Vds voltage reaches Vds1 at t1, the equivalent circuit Figure 4 is formed, while the diode connected to the secondary side transformer winding turns on. The energy stored in the transformer is delivered to the output terminal electrolytic capacitor (CO) and to the load during the time current ows (until ~t3) due to the on diode in the secondary side rectier terminal. The diode current begins to reduce linearly from the yback moment but ows until it becomes zero at a slope proportional to the output voltage and turn ratio (n). During this interval, current does not ow in the primary side. If this interval time, t1 to t2, is actually calculated, it can be obtained from the equation below. L m I ds_peak n ------------------------------ = V O + V D2 t 2 L m L mp n t 2 = -----------------------V O + V D2 LMS: Transformer secondary side inductance. Furthermore, the VCC winding deliver energy to the VCC capacitor. Lets look at the circuit connected to SPS #5 pin the SYNC circuit. This circuit mainly determines when the switch should turn on in the next period. When the drain-source voltage (Vds) becomes minimum, the internal MOSFET turns on. The VCC winding voltage waveform has the Vds voltage waveform and changes to (+) and (-) averaging to zero. The VCC winding voltage waveform is determined according to the transformer turn ratio. As the SYNC circuit connected to #5 half-wave recties the VCC winding voltage using diode (IN4148), #5 pin voltage increases linearly when the secondary diode turns on and drops when the diode turns off. The moment this voltage passes the IC SYNC circuit threshold voltage (Vsync:Typ 6.4V) as it drops, the internal comparator operates to turn the SPS on again. The circuit below shows the charging path when the sync pin voltage increases because of a turned-on diode. In circuit 5, the larger the R3 and C2, the lower the voltage rising slope. The magnitude of the nal voltage after the increase is determined by the ratio of R2 and equivalent resistance of R3//Rss (Rss connected to the internal 5V). The SYNC voltage is limited to 8.4V in the IC internal circuit. The following equation calculates this voltage. V cb R 3 R SS + 5R 2 R 3 SYNC H = ------------------------------------------------------------R 2 R 3 + R 3 R SS + R SS R

Rev C, November 1999

ID2 ILm + VLm + Vi IDS + VDS ID1 ICR + VD2

D2 ICO CO

IO + VO -

Lm n : 1

D1

CR

Figure 4. Equivalent Circuit when the Secondary side Diode Turns On

V cbR 3 R S S + 5R 2 R 3 YN C H = --------------------------------------------------------------R 2 R 3 + R 3 R S S + R SS R
5V SPS Rss 50

5 1N4148 + R2 C2 R3 D4 Vcb

Figure 5. Charging Circuit when the Secondary side Diode Turns On The resistor and capacitor related to this circuit should be designed carefully such that Sync voltage does not exceed Vsyth in the standby state but rises to about 8V during normal operation and that minimum voltage (Vds) switching is veried in normal operation. R1 and R2s resistances of about few tens k~100k do not present any problems in testing. A capacitor of lower than about few hundreds pF satises the above conditions. In this case, the Vds voltage can be divided mainly into two parts. It is the sum of the primary side input voltage (Vin) and nVO . The applied transformer primary side voltage n (turn ratio) times the output voltage (VO) when the diode has turned on. Therefore, if there is no leakage inductance, Vds becomes Vin+nVO .

Rev C, November 1999

C: MODE III (t2 ~ t4): Resonance Interval

At t2, the diode current becomes zero and turns off because of the applied reverse voltage. The secondary side voltage does not affect primary MOSFET voltage any more and, from this point, the charged energy between the output equivalent capacitor (Coss) and the snubber capacitor (Cr) starts to resonate through the primary transformer inductor (Lm). This resonant circuit is composed only of the DC voltage source (Vin), inductor (Lm) and capacitance (Crs:Coss//Cr). The resonance voltage and current shape in this case have cosine and sine waveforms, respectively. After passing t3, the inductor voltage polarity reverses, making the current increase. Between passing t3 and reaching t4, the Vlm polarity is + and Vds voltage becomes lower than Vin. As Vlm increases, the capacitor voltage Vds gradually reduces and its minimum value can be divided into three cases.
5V SPS 50 Rss 5 Sync

C2

R3

Figure 6. Discharging Circuit at Resonance

(1) Vi =Vr(nVo)
In the resonance circuit, the maximum positive (+) inductor voltage (Vlm) is nVO (i.e Vr) and Vds voltage is Vin minus inductor voltage. In this case, minimum Vds is Vin-nVO . Because nVO equals Vin, the minimum is zero. The moment Vds voltage reaches the minimum value, the #5 pin voltage crosses Vsyth through the external SYNC circuit and the SPS internal MOSFET turns on again. Zero voltage switching occurs; MOSFET turn-on loss becomes zero; and noise due to the current spike at turn-on is not generated. t3 = L m C rs C rs = C oss + C r The resonance interval, Dt3(t2~t4) applicable to half of the LC resonance period is calculated by the equation above. As shown by the equation above, the resonance interval is proportional to the transformer inductance and resonance capacitor (Crs), the sum of the MOSFET output capacitor and snubber capacitor. After resonance begins, the VCC line voltage stops charging the SYNC circuit capacitor, which starts discharging through the external resistor, R#3 and SPS internal resistor, Rss. Vsync is calculated by the equation below. The SYNC equivalent circuit of this case is shown below.

Rev C, November 1999

V sync (t) = V sync h e

R 3 + R SS -------------------------- t R3R SS C 2

----- 5 R3 R3 + ------------------------ 1 e R 3 + R SS

R3

In the SYNC circuit, the time it takes for Vsync to reduce from Vsyth_h to Vsyth (typ.6.4V) should be set to half the resonance period, calculated above. If the transformer inductor value changes or snubber capacitor value is changed, this time setting must be veried.
VGS

VDS1

VDS

ID

Vcb

VSS

ICR t0 t1 t2 t3 t4 t4 t5

Figure 7. Waveform of Each Component

(2) Vi < Vr (nVo)

In the resonance circuit type, the maximum positive inductor voltage (Vlm) is the nVO and Vds is the difference of Vin and inductor voltage. In this case, the minimum Vds is Vin-nVO. Because Vin<nVO, the minimum Vds value becomes negative, however, for a MOSFET, the internal diode between the drain-source turns on as soon as the voltage becomes negative (more precisely, internal diode turn-on voltage: -0.7V), making the resonance current ows through the internal diode. Of course, the MOSFET turn-on loss becomes zero because of zero voltage switching; and the noise resulting from the current spike at turn-on is not generated.

Rev C, November 1999

VGS

VDS1

VDS Current of turned on internal diode ID

Vcb

VSS

ICR t0 t1 t2 t3 t4 t4 t5

Figure 8. Waveform of Each Component (Vi<Vr)

ID2 ILm + VD2

D2 + ICO CO

IO + VO -

VLm + Vi -

Lm n : 1

IDS + VDS

ID1

ICR

D1

CR

Figure 9. Circuit at Internal Diode Turn-on (Vi<Vr)

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10

(3) Vi > Vr(nVo)

If Vi becomes greater than nVO, the minimum Vds voltage is Vin-Vr. The charged snubber capacitor discharged as SPS turns on. Vds_min=Vi-Vr (Vr:nVo) As reviewed in the above three cases, because the MOSFET was made to turn on at either zero or minimum, it generates less noise than the hard switching method. At turn-off, the snubber capacitor much larger that the MOSFET output equivalent capacitor (Coss) reduces the Vds rising slope, which reduces the noise generation. If the input voltage is varies, the power supply will operate through the above three modes. If the AC line input voltage is low, it will operate through mode (1) or (2) and, if high, through mode (3). Figure 9 shows the circuit with a turned-on internal diode when (Vi<Vr).

D: MODE IV (t4 ~ t5): MOSFET Turn-on Interval

In this interval, the MOSFET turns on and current ows. The equivalent circuit in this interval is shown above. Input voltage (Vi) is applied to the transformer inductor (Lm) and MOSFET's current increases at a linearly. The DC input voltage makes this current's slope equal to (Vi/Lm). The energy stored in the transformer internal inductor is proportional to this current. This energy is 0.5*Lm* Ipk2 and is supplied to the secondary side when the MOSFET turns off. Because the energy in the inductor is proportional to the square of the current magnitude, the bigger the output load, the higher the inductor current. The lower the input voltage and larger the feedback voltage (i.e., the larger the load), the longer the MOSFET turn-on interval, Dt4. The higher the input voltage and lower the output load, the higher the switching frequency becomes.

E. Operation in the STAND BY MODE

The standby mode where the TV is off and it receives only input from the remote control will be reviewed. The output load in the standby mode is very small. In this mode, the MOSFET turn-on time is very short and, thus, the time required to charge the SYNC circuit voltage is also short and the input voltage of the SPSs SYNC pin cannot reach Vsyth. In this case, it is designed to switch at the SPS internal oscillation frequency (TYP20kHz). Using this method in the standby state greatly reduces the switching loss but is limited when trying to satisfy the recent consumption power regulation of the standby state. Currently, using a auxiliary-power supply or changing the other secondary circuits has become common in trying to meet this requirement, but these methods have imposed the C-TV manufacturers because of their additional costs and components. The SPS application satisfying this regulation applies the BURST MODE, which will be explained in the last pages of this note. Although the design values are difcult to develop as equations through the SPS method, it can be derived in general form because the parameters of each component have been determined. This method is a well-suited for meeting the standby state consumption power regulation without adding many components. A graph of the characteristics of the SPS DEMO BOARD that used 100W input power and KA3S0680R is attached below this page. Then, the BURST MODE operation is explained. Finally, an actual circuit applied with BURST MODE and a PART LIST are attached.
Rev C, November 1999

11

ID2 ILm + VD2

D2 + ICO CO

IO + VO -

VLm + Vi -

Lm n : 1

IDS + VDS

ID1

ICR

D1

CR

Figure 10. Circuit at MOSFET Turn-on

MOSFETDrain current vs ac line voltage MOSFET drain current ID (A) 3.5 3 2.5 2 1.5 1 0.5 0 80 130 180 230 280 ac line voltage Vac (V) ID

Figure 11. Change in the maximum MOSFET current value

Swiching frequency vs line voltage 80 Switching frequency kHz 70 60 50 40 30 20 10 0 80 130 180 230 280 Freq

ac line voltage Vac (V)

Figure 12. Change in the Switching Frequency

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12

Temprature vs ac line voltage 60 Temprature (degree) 50 40 30 20 10 0 80 130 180 230 280 ac line voltage Vac (V) Ttrans: transformer temperature Tsps: SPS case temperature Ths: temperature of the heatsink mounted with SPS Ttrans Tsps Ths

Figure 13. Input voltage vs. Each Components Temperature Change

SPS
Vfb

1 C9

3S0680R
3 Sync 5 Vss + + 2

Vcc

Figure 14. SPS DEMO BOARD

Rev C, November 1999

13

D1 SYNC PIN R1 VCC Winding R2 7.5V C1 5.6V R3

Figure 15. Sync Circuit Charging

5. Burst Mode Operation

A. Introduction
Recently, many countries and regulations are requiring the Stand-By Power to be lower than a set wattage. Although various other method including the auxiliary power supply have been adopted by Set manufacturers, the SPS with the Burst Mode Operation can be chosen to effectively meet this regulation. Burst Mode Operation can raise the stand-by efciency of the QRC type SMPS to above 50% only that the SPS must add a few components.

B. Operation
1). Sync Circuit Charging (Figure 15.) When SPS turns off and the current ybacks to the secondary side, C1 charges to the Zener voltage of 7.5V through R1 as D1, connected to the Vcc winding, turns on. The charging time is a function of R1, R2 and C1.(FIG.15) 2). Sync Circuit Discharge (Figure 16.) Even though the discharge path is through both R2 and R3 (as shown in the diagram), most of the current ows through R3 if C1's voltage is above 5.6V. (R2>>R3) C1 and R3 determines the timing to detect the minimum Vds voltage in the KS3S series application. An appropriate R2 value has been set to execute Soft Start and Burst Mode Operations. The SPS, equipped with the feedback offset (stops the switching when feedback pin voltage becomes lower than about 0.3V and makes the Burst Mode Operation possible), stops the switching when the feedback level is low as it is in the Stand-By Mode. In this case, C1 and R2 are in such a way as to make the Sync Pin voltage fall to about 0V. The SPS switching stops until the output voltage falls to certain value and, then, executes soft start (i.e., the Burst Mode Operation) again.Depending on feedback dynamics and output load, the cycle of this operation can change.
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14

SYNC PIN R1 R3

R2 7.5V C1 5.6V

Figure 16. Sync Circuit Discharging The Sync timing can be truned by appropriately controlling C1 and R2//R3 to eliminate R3 and 5.6V Zener, but this requires using within -1% staturated devices, which happen to be inappropriate for production.

C. Parameters Setting
Devices cannot be set simply through calculations. Though most are set through testing, the values can be set easily by following the steps, below. R2 is set experimentally to about 600~800 but inversely proportional to the Stand-By Load. R1 is increased usually to an appropriate value such that the device is int destroyed at output short or abnormal conditions. However, it is set to match the winding ratio in order to clamp the sync pin voltage to 7.5V near the end of yback. As C1 becomes larger, the sync timing error, from the deviation of the IC internal sync reference, increases. If C1 becomes smaller, the sync pin voltage becomes less than the feedback pin voltage in normal operation mode due to the lowering switching frequency from the load increase and all this can cause a shutdown. An appropriate R3 should be set according to Lm and snubber capacitor to tune the sync timing.

Rev C, November 1999

15

R6

FUSE + BD C5 C14 BEAD1

Vo: 125V Vo: 12V

SPS
Vfb

1 C9

D6 C12

+ C13

3S0680RF
3 Sync 5 Vss R1 C2 R3 ZD2 ZD1 D4 2 C11 BEAD1 D5 C8 C7 R2 + +

Vcc D2 R4

R5

Vx + C4 VR1 D3 R9 +

OPT1 C3 R10 R7 R11

C10

R8

Q1

C6

R12

Figure 17. SPS application circuit with Burst Mode

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16

Transformer Specipication 1 14 6 2 NP2 NP1 NS3 5T 6 NP3 NS2 NS1 13 5 4 3 2 1

12

11

10

8 1; 4T (0.55 *2): 12 : 4 13 (NS1) 3 (NP1)

2; 31T (0.5 ) PRIMARY INDUCTANCE: LP=600uH (NP1+NP2) 10% Core: FERRITE Core EER3543 (SAM-HWA CO.LTD) 3; 4; 5; 6;

18T (0.4 *2): 32T (0.5 ) :

9 10 (NS2) 3 1 (NP2)

18T (0.4 *2): 10 6T (0.4 ) : 6

11 (NS3) 7 (NP3)

Figure 17. SPS application circuit with Burst Mode

Rev C, November 1999

17

PART LIST
Part R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 VR1 C1 C2 C3 Value 33 120 (1W) 680 28k (1W) 28k (1W) NTC (4.9) 1.6k 300k short 1k 210k (1%) 4.9k(1%) 20k 224 (250V) (b) 683 (50V) (c) 223 (50V) (f): D2 D3 IN4004 IN4937 Part C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 Value 47uF (50V) (e) 220uF (400V) (e) 220pF (25V) (f) 1000uF (25V) (e) 1000uF (25V) (e) 222 (800V) (f) 102 (100V) (f) 561 (2kV) (f) 47uF (200V) (e) 100uF (200V) (e) 561 (kV) (f) OPT Q1 F1 T2 ZD1 ZD2 PC817 KA431AZ LINE FILTER (6mH) on/off switch (5A, 270V) 7.5V 5.6V Part D4 D5 D6 BRIDGE DIODE FUSE BEAD1 BEAD2 Value 1N4148 1R5GU41 RU20A D2SB (270V, 4A) 4A, 250Vac 2uH 100uH (1A)

Recommended TORQUE for screwing TO3PF-5L pakage type SPS is 7~8kg.cm/N.

SPS LINE UP TABLE & POWER INPUT FOR C-TV

MARKING KA3S0680RF KA3S0880RF KA3S0765RF KA3S0965RF KA3S1265RF PKG TO3PF-5L TO3PF-5L TO3PF-5L TO3PF-5L TO3PF-5L SPL Possible NOW NOW NOW NOW NOW Mass Production Supply Possible NOW NOW NOW NOW NOW Pin (FREE) Pin (220V) 110W 140W 100W 150W 190W 140W 170W 140W 180W 250W

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References
[1] Transformer and Inductor Design Handbook, 2nd Edition, Colonel Wm. T. McLyman, Marcel Dekker, Inc., 1988. [2] Filter Inductor and Flyback Transformer Design for Switching Power Supplies, Lloyd H. Dixon, Jr., Unitrode Switching Regulated Power Supply Design Seminar Manual, Unitrode Corporation. 1988. [3] Flyback converter design using SPS, S.T.IM, SPS Application note, Fairchild Electronics

Author
Jeong-Yul Yun is an application engineer in Power Device Division, Fairchild Electronics Co., LTD. Tel. 82-32-680-1275 Fax. 82-32-680-1317 E-mail. yunhuh@fairchildsemi.co.kr

Rev C, November 1999

19

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Full Production

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