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Title Figure Page

1. Domain & level representation of VHDL 2. Direct form FIR Filter 3. Cascaded form FIR Filter 4. lattice form FIR Filter 5. Basic FIR Filter 6. 27 Tap FIR Filter 7. RTL Systematic of Multiplier 8. Multiplier Output 9. RTL Systematic of MAC 10. MAC Output 11. RTL Systematic of FIR

1 2.1 2.2 2.3 3.1 3.2 3.3, 3.4 3.5 3.6, 3.7 3.8 3.9, 3.10, 3.11

11 21 24 24 32 33 40, 41 42 45, 46 47 52, 53 54 56

12. FIR Output






1. Multiplier Output 2. MAC Unit Output 3. FIR Output

3.1 3.2 3.3

41 48 57

Declaration Certificate Acknowledgement List of figure List of Tables Chapter 1 Introduction 1.1 Abstract 1.2 VLSI an Introduction 1.3 VHDL Introduction 1.4 Current Research in India and Abroad Chapter 2 - Mathematical Background 2.1 Introduction to FIR Filters 2.1.1 Advantages of digital filters 2.2 Realization of FIR Filters 2.3 Structures of FIR Filters 2.3.1 Direct Form 2.3.2 Cascaded Form 2.3.3 Lattice Form 2.4 Methods of Designing FIR Filters 2.4.1 Fourier Series Method 2.4.2 Window Technique 2.4.3 Frequency Sampling Method 2.5 Comparisons of various design methods for FIR Filters 2.5.1 Kaiser window 2.5.2 Design specification 2.5.3 Design procedure 2.6 Typical Design requirements

Chapter 3 Design of 27 tap FIR filter

3.1 Design Description

3.2 The design of 27 tap FIR filter. 3.3 Statement of problem. 3.4 How we designed the FIR filter 3.5 Code , RTL systematic and simulation for multiplier 3.6 Code , RTL systematic and simulation for MAC unit. 3.7 Code, RTL systematic and simulation for 27 TAP FIR filter.

Chapter 4 Usefulness and Application Chapter 5 Conclusion and Scope for future extension.

The main aim of this project is VHDL SIMULATION OF FIR FILTER. It involves 27 taps for improving the accuracy of the filter. It is implemented using a popular HDL(Hardware Description Language ) called VHDL(very high speed integrated circuit hardware description language).The filter is implemented through the use of three basic components used for any DSP system implementation Adder, Multiplier and Delay, along with some other components. Filter is one of the most fundamental processing element in any digital processing system (DSP) which is frequency selective. Here the term frequency selective means that the system passes certain frequency components and totally rejects others. Digital filters can be classified into two classes known as FIR (finite impulse response) and IIR (infinite impulse response) filters. Advantage of FIR over IIR is that they are guaranteed to be stable and to have linear phase response. Linear filters are widely used in digital communication system, in spectral analysis and particularly in application where non-linear phase can be tolerated.




VLSI means Very Large Scale Integration. It is an effort to integrate discrete

components circuit in a single silicon base (chip). The integration results in high reliability, low power consumption, less weight, low volume and low cost of products. The growing need for sophistication of application continuously pushes the design as well as manufacturing of electronic components and systems to anew level of complexity. For less complex operation we can design using discrete components (transistors, gate ICs, etc) When we want complex operation to be performed by the electronic system, it is very difficult to design the system using discrete components. The system becomes very bulky, unreliable, and less redundant. Also it takes a lot of time to develop the system. Hence there is need to develop an integrated circuit or a single chip dedicated to a specific task. The chip is referred to as an application specific integrated circuit (ASIC). A single chip has the following advantage over the circuit from discrete components.

1. Size: -

Integrated circuits/chips are much smaller. Both transistors and wires are

shrunk to micrometric (and nowadays to nanometric) sizes.

2. Speed: -

Communication within a chip can occur hundreds of time faster than

communication between chips on a printed circuit board (PCB). This is because of smaller parasitic capacitance.

3. Power Consumption: -

Due to smaller size, logic operation within a chip

consumes less power. These chip level advantage results into a smaller physical size, low power consumption, and reduced cost of the system.

VHDL is an acronym which for VHSIC hardware description language. VHSIC means very high speed integrated circuit. VHDL can wear many hats. It is used for documentation,verification, and synthesis of large digital design. This is actually one of the key feature of VHDL, since the same VHDL code can achieve the all the three of these goals, it can also be used to take three different approach for describing hardware. They are structural, behavioural and data flow. As a standard description VHDL is used as input and output to various simulation, synthesis and layout tools. The language provides the ability to describe the system, networks and components at a very high behavioural level as well as low gate level. It also represents top down methodology and environment. Simulation can be carried out any level from general functional analysis to a very detail gate level waveform analysis. Synthesis is carried out currently only at the register level. Top down design first describes the system at a very high level of abstraction, like a specification. Designers simulate and debug the system at this very high level before refining it into smaller components.

There are following VHDL terms in almost every description, along with some building blocks that are defined in VHDL to mean something different to the average designer.

ENTITY:All designs are expressed in terms of entities. An entity is the most basic building block in a design. The uppermost level of the design is the top-level entity. If the design is hierarchical then the top-level description will have lower level description contained in it. The lower level description will be lower level entity description.

ARCHITECTURE:All entities simulated have an architecture description. The architecture describes the behaviour of the entity. A single entity can have multiple architecture. One architecture might be behavioural another might be structural.

CONFIGURATION:A configuration statement is used to bind component instants to an entity architecture pair. A configuration can be considered like a part list for a design. It describes which behaviour to use for each entity much as a part list describes which part to use in the design.

GENERIC:A generic is VHDL term for a parameter that passes information to an entity for instance , if an entity is gate level model with a rise and fall delay, the values for the rise and fall delays could be passed into the entity with generics.

PROCESS:A process is a basic unit of execution in VHDL. All operations that are performed in simulation of a VHDL description are broken into a single or multiple processes.

DESIGN:VHDL is a fairly general-purpose language, and it doesn't require a simulator on which to run the code. There are a lot of VHDL compilers, which build executable binaries. It can read and write files on the host computer, so a VHDL program can be written that generates another VHDL program to be incorporated in the design being developed. Because of this general purpose nature, it is possible to use VHDL to write a testbench

that verifies the functionality of the design using files on the host computer to define stimuli, interacts with the user, and compares results with those expected. VHDL is a strongly typed language. It is relatively easy for an inexperienced developer to produce code that simulates successfully but that cannot be synthesized into a real device, or is too large to be practical. One particular pitfall is the accidental production of transparent latches rather than D-type flip-flops as storage elements. VHDL is not a case sensitive language. One can design hardware in a VHDL IDE (such as Xilinx or Quartus) to produce the RTL schematic of the desired circuit. After that, the generated schematic can be verified using simulation software (such as ModelSim) which shows the waveforms of inputs and outputs of the circuit after generating the appropriate testbench. To generate an appropriate testbench for a particular circuit or VHDL code, the inputs have to be defined correctly. For example, for clock input, a loop process or an iterative statement is required. The key advantage of VHDL when used for systems design is that it allows the behavior of the required system to be described (modeled) and verified (simulated) before synthesis tools translate the design into real hardware (gates and wires). Another benefit is that VHDL allows the description of a concurrent system (many parts, each with its own sub-behavior, working together at the same time). VHDL is dataflow language, unlike procedural computing languages such as BASIC, C, and assembly code, which all run sequentially, one instruction at a time. A final point is that when a VHDL model is translated into the "gates and wires" that are mapped onto a programmable logic device such as a CPLD or FPGA, then it is the actual hardware being configured, rather than the VHDL code being "executed" as if on some form of a processor chip.



The flow of data through the entity is modelled primarily using concurrent signal assignment statements. The structure of the entity is not explicitly specified but it can be implicitly deduced. Architecture MYARCH of MYENT is begin SUM <= A xor B after 8ns end MYARCH;


The behavior of a component is modeled inside an architecture body of the entity It may be described using a collection of concurrently executing statements A concurrent statement is sensitive to a set of input signals and is executed whenever any of its sensitive signal changes its value A concurrent statement called process statement can contain one or more sequential statements A set of sequential statements can be clubbed together in a subprogram.


Digital circuits consist of components and interconnection between them A component can in turn be composed of sub-components and interconnections A component interacts with other components through pins Component is modeled as entity Component pins are modeled as ports Interconnections between components are modeled as signals. their

Xilinx designs, develops and markets programmable logic products including integrated circuits (ICs), software design tools, predefined system functions delivered as intellectual property (IP) cores, design services, customer training, field engineering and technical support. Xilinx sells both FPGAs and CPLDs programmable logic devices for electronic equipment manufacturers in end markets such as communications, industrial, consumer, automotive and data processing. Xilinxs FPGAs have even been used for the ALICE (A Large Ion Collider Experiment) at the CERN European laboratory on the French-Swiss border to map and disentangle the trajectories of thousands of subatomic particles. The Virtex-II Pro, Virtex-4, Virtex-5, and Virtex-6 FPGA families are particularly focused on system-on-chip (SoC) designers because they include up to two embedded IBM PowerPC cores. They can run a regular embedded OS (such as Linux or vxWorks) and they can implement processor peripherals in programmable logic. Xilinxs IP cores include IP for simple functions (BCD encoders, counters, etc.), for domain specific cores (digital signal processing, FFT and FIR cores) to complex systems (multi-gigabit networking cores, MicroBlaze soft microprocessor, and the compact Picoblaze microcontroller). Xilinx also creates custom cores for a fee. The ISE Design Suite is the central electronic design automation (EDA) product family sold by Xilinx. The ISE Design Suite features include design entry and synthesis supporting Verilog or VHDL, place-and-route (PAR), completed verification and debug using ChipScope Pro tools, and creation of the bit files that are used to configure the chip. Xilinxs Embedded Developers Kit (EDK) supports the embedded PowerPC 405 and 440 cores (in Virtex-II Pro and some Virtex-4 and -5 chips) and the Microblaze core. Xilinxs System Generator for DSP implements DSP designs on Xilinxs FPGAs. A freeware version of its EDA software called ISE WebPACK is used with some of its nonhigh-performance chips. Xilinx is the only (as of 2007) FPGA vendor to distribute a native Linux freeware synthesis toolchain.


1. Go to file and click New Project.

2. Select designing properties for VHDL design and simulation.

3. Click Finish to create New Project.

4. Go to project and New Source to add to a project.

5. Select a VHDL Module to perform a function.

6. Write a code and implement it to obtain waveform.


Xilinx has two main FPGA families: the high-performance Virtex series and the highvolume Spartan series, with a cheaper EasyPath option for ramping to volume production. It also manufactures two CPLD lines, the CoolRunner and the 9500 series. Each model series has been released in multiple generations since its launch. The latest Virtex-6 and Spartan-6 FPGA families are said to consume 50 percent less power, cost 20 percent less, and have up to twice the logic capacity of previous generations of FPGAs.

SPARTAN FAMILY The Spartan series targets applications with a low-power footprint, extreme cost sensitivity and high-volume such as displays, set-top boxes, wireless routers and other applications. The Spartan-6 family is built on a 45-nanometer (nm), 9-metal layer, dualoxide process technology. The Spartan-6 was marketed in 2009 as a low-cost solution for

automotive, wireless communications, flat-panel display and video surveillance applications. The Spartan-3A consumes more than 70-90 percent less power in suspend mode and 4050 percent less for static power compared to standard devices. Also, the integration of dedicated DSP circuitry in the Spartan series has inherent power advantages of approximately 25 percent over competing low-power FPGAs. VIRTEX FAMILY The Virtex series of FPGAs have integrated features such as wired and wireless infrastructure equipment, advanced medical equipment, test and measurement, and defense systems. In addition to FPGA logic, the Virtex series includes embedded fixed function hardware for commonly used functions such as multipliers, memories, serial transceivers and microprocessor cores. The Virtex-6 family is built on a 40-nm process for compute-intensive electronic systems, and the company claims it consumes 15 percent less power and has 15 percent improved performance over competing 40 nm FPGAs. Older-generation devices such as the Virtex, Virtex-II and Virtex-II Pro are also still available, although their functionality is largely superseded by the Virtex-4 and -5 FPGA families. The Virtex-II Pro family was the first to combine PowerPC embedded technology (including single and multiple PowerPC 405 processor cores) and integrated serial transceivers (up to 3.125 Gbit/s in Virtex-II Pro and up to 10.3125 in Virtex-II Pro X). The Virtex-4 series was introduced in 2004 and was manufactured on a 1.2V, 90-nm, tripleoxide process technology. The Virtex-4 family introduced the new Advanced Silicon Modular Block (ASMBL) architecture enabling FPGA platforms with a combination of features to support logic (LX), embedded processing and connectivity (FX), digital signal processing (SX). The Virtex-5 series was introduced in 2006. With it, Xilinx moved from its traditional four input LUT design to six-input LUTs. It is a 65-nm design fabricated in 1.0V, tripleoxide process technology. The Virtex-5 LX and the LXT are also intended for logic-intensive applications, and the

Virtex-5 SXT is for DSP applications. The Virtex-5 FXT has been described by Xilinx as the ultimate system integration platform designed for wired and wireless communications, audio/video broadcast equipment, military, aerospace, and industrial systems. The Virtex-5 TXT family includes up to 48 6.5 Gbit/s serial transceivers and is the industries first programmable 100G bridging solution.


1.High performance and low power FIR filter design based on sharing multiplication by JONGSUN PARK AND WOOPYYO JEONG Abstract In this they present a high performance and low power FIR filter design, which is based on computation sharing multiplier (CSHM). CSHM specifically targets computation re-use in vector-scalar products and is effectively used in our FIR filter design. Efficient circuit level techniques: a new carry select adder and conditional capture flip-flop (CCFF), are also used to further improve power and performance. The proposed FIR filter architecture was implemented in 0.25 /spl mu/m technology. Experimental results on a 10 tap low pass CSHM FIR filter show speed and power improvement of 19% and 17%, respectively, with respect to an FIR filter based on the Wallace tree multiplier. 2. A cascadable adaptive FIR filter VLSI IC by BORTH and GERSON Abstract In this they describes the architecture and features of the Motorola DSP56200, an algorithm-specific cascadable digital signal processing peripheral designed to perform the computationally intensive tasks associated with FIR and adaptive FIR digital filtering applications. The DSP56200 is implemented in high performance, low power 1.5m HCMOS technology and is available in a 28 pin DIP package. The on-chip computation unit includes 97.5 ns 2416-bit multiplier with a 40-bit accumulator, a 25624-bit coefficient RAM, and a 25616-bit data RAM. Three modes of operation allow the part to be used as a single FIR filter, a dual FIR filter, or a single adaptive FIR filter, with up to 256 taps/chip. In the adaptive FIR filter mode, the part performs the FIR filtering

and LMS coefficient update operations for a single tap in 195 ns, permitting use of the part as a 19 kHz sampling rate, 256 tap adaptive FIR filter. Programmable DC tap, coefficient leakage, and adaptation coefficient parameters in the adaptive FIR mode allow the DSP56200 to be used in a wide variety of adaptive FIR filtering applications. The performance of the part in an echo canceller configuration will be presented. Typical applications of the part will also be described.


Design of low pass digital FIR of 27 tap satisfying the following properties:
1. pass band cut-off frequency fp=150 hz 2. stop band cut off frequency fs= 250 hz 3. passband ripple Ap=0.1 db 4. stopband atenuation As=40 db 5. sampling frequency F= 1 khz

Chapter 2.




FIR filters are finite impulse response filters. The output of such digital filters depends on the previous input as well as on the present input faded to the filters. The transfer function of FIR filters of order M is given byM

H (z) = h (n) Z-n 2.1.1


Where, h(n) is known as the system response. The Fir filter of length M with input x(n) and output y(n) is described by the difference Equation

y(n) = b0x(n) + b1x(n-1) +..+bMx(n-M-1).


= bkx(n-k) 2.1.2

where {bk} is the set of filter coefficients.

So, we can express the output sequence as the convolution of the unit sample response of h(n) of the system with the input signal. Ultimately, we have


y (n) = bkx(n-k) 2.1.3


The lower and upper limit on the convolution sum reflects the causality and the finiteduration characteristics of the filter. So, any digital filter should be stable and causal for it to be physically realizable . One of the very important property of an FIR filter is that it is always stable and have a linear phase and hence physically realizable. Because of the fact that the poles of FIR filter are always at origin, Fir filters are always stable. Also, Fir filter can give a linear phase when the impulse response of the filter is symmetric about its mid point. The condition to be imposed on FIR sequence h(n) in order that the filter can be called as linear phase filter areSymmetric condition h (n) = h (N-1-n). .. 2.1.4 Asymmetric condition h (n) = -h(N-1-n). 2.1.5 For a digital filter to be causal and stable the following condition must be satisfiedCausal if impulse response h (n) is 0 for n < 0. A filter is stable if its impulse response is absolutely summable,

i.e. |h (n)| < . . 2.1.6

n =-

[2.1.1] Advantages Of Digital Filters:The following list gives some of the main advantages of digital over analog filters. 1. A digital filter is programmable, i.e. its operation is determined by a program stored in the processor's memory. This means the digital filter can easily be changed without

affecting the circuitry (hardware). An analog filter can only be changed by redesigning the filter circuit. 2. Digital filters are easily designed, tested and implemented on a general-purpose computer or workstation. 3. The characteristics of analog filter circuits (particularly those containing active components) are subject to drift and are dependent on temperature. Digital filters do not suffer from these problems, and so are extremely stable with respect both to time and temperature. 4. Unlike their analog counterparts, digital filters can handle low frequency signals accurately. As the speed of DSP technology continues to increase, digital filters are being applied to high frequency signals in the RF (radio frequency) domain, which in the past was the exclusive preserve of analog technology. 5. Digital filters are very much more versatile in their ability to process signals in a variety of ways; this includes the ability of some types of digital filter to adapt to changes in the characteristics of the signal.


The set of equation defines a computational procedure or an algorithm for implementing the system. From each set of equations we construct a block diagram consisting of an interconnection of delay elements, multipliers and adders. Such block diagrams are referred as the realization of the system or as the structure for realizing the system. But the major factor that influences the choice of a specific realization are computational analysis, memory requirement and finite-word-length effects in the computation. [2] Computation complexity refers to the number of arithmetic operations (multiplications, divisions and additions) required to compute an output value y (n) for the system. Memory requirements refers to the number of memory locations required to store the system parameters, past inputs, past outputs, and any intermediate computed value of the system. Finite-word-length refers to the quantization effects that are inherent in any digital

implementation of the system, either in hardware or in software. The parameters of the system must necessarily be represented with finite precision. The computation performed to obtain output from the system must be rounded off or truncated to fit within the limited precision constraints of the computer or the hardware used in the implementation. All these problems are usually called finite-word-length effects and very important to select a realization that is not very sensitive to finite-word-length effects.


There are basically three types of designing structures which are most commonly used network structure Direct form structure Cascaded form structure Lattice structure

[2.3.1] Direct Form:-:

The Direct form realization follows immediately from the nonrecursive difference equation given by the convolution summation

y (n) = h (k)x(n-k) .....


This structure requires M-1 memory locations for storing the M-1 previous input, and has a complexity of M multiplication and M-1 addition per output point. Since the output consists of a weighted linear combination of M-1 past values of the input and the weighted current value of the input, the structure is known as the tapped delay line filter or traversal filter. When the FIR system has a linear phase, the unit sample response of the system satisfies either the symmetric or asymmetric condition

h (n) = h (M-1-n) .

Figure - 2.1 : Direct form FIR filter

[2.3.2] Cascaded Form:-

The Cascaded form realization is obtained by factoring the polynomial system function. That is we represent H(z) as

H (z) = h (n) Z-n



= (b0k + b1kZ-1 + b2kZ-2)


k = 1, 2.K

Here K is the integer part of ( M + 1 )/2. The filter parameter b0 may be equally distributed

among the K filter section, such that b0 = b10b20.bK0 or it may be assigned to a single filter section. The zeros of H (z) are grouped in pairs to produce the second order FIR system of the form of the polynomial stated above. It is always desirable to form pairs of complex conjugate roots so that the coefficients {bki} are real valued.

Figure 2.2 : Cascaded form of FIR

[2.3.3] Lattice Form:-:

The Lattice form structures are used extensively in digital speech processing and in implementation of adaptive filters. A two-stage lattice filter can be formed by cascading two lattice stage as shown below-

Figure 2.3 : Lattice form of FIR [2.4] METHODS OF DESIGNING FIR ILTERS:-

There are basically three important methods of designing the Fir filters Fourier Series Method Window Technique Frequency Sampling Method

[2.4.1] Design by Fourier Series Method:-

The following two concepts lead to the design of FIR filters by this method1. The frequency response of a digital filter is periodic with period equal to the sampling frequency. 2. Any periodic function can be expressed as a linear combination of complex exponentials. In this method the desired frequency response Hd () can be converted to a Fourier Series representation by replacing by 2fT where T = sampling time. Then, using this expression the Fourier coefficients are evaluated which is the desired impulse response of the hd(n). On taking Z-transform of the hd(n) we get Hd(Z) which is the Transfer Function of the digital filter. Finally, we truncate the infinite impulse response to a finite duration sequence of length N. we get transfer function as

H(z) = h(0) + h(n)[Zn + Z-n]


But this is not physically realizable. Multiplying the transfer function by the delay Z-(N-1)/2 brings reliability, where, (N-1)/2 is delay in sample. Therefore,

H(Z) = Z-(N-1)/2 H(Z)


= Z-(N-1)/2 [ h(0) + h(n)(Zn + Z-n)] ..


This modification doesnt affect the amplitude response of the filter; however the abrupt

truncation of Fourier series results in the oscillations in the passband and stopband. These oscillations are due to the slow convergence of Fourier series, particularly near the point of discontinuity. This effect is known as Gibbs phenomenon. Multiplying the desired impulse response coefficients by an appropriate window function can reduce the undesirable oscillations.

[2.4.2] Design of FIR Filter by Window Technique:In Window Technique we proceed as follows-

Choose the desired frequency response of Hd().

Take the inverse Fourier transform of Hd() to obtain desired impulse response as

Hd(n) = Hd()e-j d .


Choose a window sequence w(n) and multiply the infinite response hd(n) with a chosen window sequence w(n) of length N to obtain filter coefficients h(n) i.e.

H(n) = hd(n) w(n) , |n| < (N-1)/2 = 0 , otherwise

Find the transfer function of realizable filter by taking Z-transfer of h(n). Realize the filter by suitable structure.

[2.4.3] Design of FIR Filter by Frequency Sampling Method:In this method the desired magnitude response is sampled and a linear phase response is specified. The samples of desired frequency response are identified as DFT coefficients. Then the filter coefficients are determined as the IDFT of this set of samples.


The design method based on the use of windows to truncate the impulse response hd(n) and obtaining the desired shaping was the first method proposed for designing linear phase FIR filters. Other methods like frequency sampling were later developed The major disadvantage of window design method is the lack of precise control of the critical frequencies, such as s and p, in the design of the low pass filters. The values of s and p in general depend upon the type of window and filter length M. The frequency sampling method provides as improvement over the window design method. Since Hr() is specified at the frequencies k = 2k/M and k = 2(K+1)/M and transition band is multiple of 2/M. This filter design method is particularly useful when FIR filter is realized either in the frequency domain by means of the DFT or in any of the frequency sampling realizations. The attractive features of these realizations are that Hr(k) is either zero or unity at all frequencies except in the transition band.

[2.5.1] Kaiser Window:In a window function , it is clear that the width of the main lobe is inversely proportional to the length of the filter. As the length of fiilter is increased the width of main lobe becomes narrower and narrower, and the transition band is reduced considerably. The attenuation in the side lobe is however independent of the length and is a function of the type of the window. Therefore a proper window function is to be selected in order to achieve a desired stop band attentuation. A window function with minimum stopband attenuation has the maximum main lobe width. Therefore the length of the filter must be increased considerable to reduce the main lobe width and to achieve the desired transition band . A desirable property of window function is that the function is of finite duration in the time domain and that the fourier transform has maximum energy in the main lobe . the prolate spheriodal function have this desirable property; however , this functions are

complicated and difficult to compute . a simple approximation to these function has been developed by Kaiser in terms of zeroth order modified bessel functions [6] of the first kind. In a kaiser window the side lobe level can be controlled with respect to the main lobe peak by varying a parameter .The width of the main lobe can be varied by adjusting the length of the filter.

[2.5.2] Design Specification:-

1. Filter type : Low-pass, high-pass, bandpass or bandstop. 2. Passband and stopband frequencies in Hz : For Low-pass/High pass : fp and fs. For band-pass/band-stop : fp1, fp2, fs1 and fs2. 3. passband ripple and minimum stopband attenuation in +ve decibals : Ap and As. 4. Sampling frequency in Hz : F 3. Filter order M- odd. [2.5.3] Design Procedure:1. Determine according to eq. where the actual design parameters can be determined from = min(p, s) where p = 10-0.05As s = (100.05Ap 1)/(100.05Ap + 1) 2. Calculate As as As = -20 log10 s dB 3. Determine the parameter where = 0 for As<=21 = 0.5842(As 21)0.4 + 0.07886(As 21), for 21<As<=50

= 0.1102(As 8.7), for As>50 4. Determine the parameter D as follows, D = 0.9222, for As<=21 D = (As 7.95)/14.36 for As>21 5. Calculate M as follows M>= FD/F + 1 6. The modified impulse response is then calculated as h(n) = wk(n)hd(n), for n<= (M-1)/2 For Low-pass filter Hd(n) = (2fc/F) (sin 2nfc/F)/ (2nfc/F), for n>0 Hd(n) = (2fc/F), for n=0 Where fc=0.5(fp + fs) and F=fs - fp [7]

[2.6] TYPICAL DESIGN REQUIREMENTS:Typical requirements which are considered in the design process are The filter should have a specific frequency function The filter should have a specefic impulse response The filter should be causal. The filter should be stable. The filter should be localized. The computational complexity of the filter should be low. The filter should be implemented in a particular hardware or software.

The Impulse Response

There is a direct correspondence between the filter's frequency function and its impulse

response, the former is the Fourier transform of the latter. This means that any requirement on the frequency function is a requirement on the impulse response, and vice versa. However, in certain applications it may be the filter's impulse response which is explicit and the design process then aims at producing as close an approximation as possible to the requested impulse response given all other requirements. In some cases it may even be relevant to consider a frequency function and impulse response of the filter which are chosen independently from each other. For example, we may both want a specific frequency function of the filter and that the resulting filter have a small effective width in the signal domain as possible. The latter condition can be realized by considering a very narrow function as the wanted impulse response of the filter even though this function has no relation to the desired frequency function. The goal of the design process is then to realize a filter which tries to meet both these contradicting design goals as much as possible.

In order to be implementable, any time-dependent filter must be causal: the filter response only depends on the current and past inputs. A standard approach is to leave this requirement until the final step. If the resulting filter is not causal, it can be made causal by introducing an appropriate time-shift (or delay). If the filter is a part of a larger system (which it normally is) these types of delays have to be introduced with care since they affect the operation of the entire system.

A stable filter assures that every limited input signal produces a limited filter response. A filter which does not meet this requirement may in some situations prove useless or even

harmful. Certain design approaches can guarantee stability, for example by using only feedforward circuits such as an FIR filter. On the other hand, filter based on feedback circuits have other advantages and may therefore be preferred, even if this class of filters include unstable filters. In this case, the filters must be carefully designed in order to avoid instability.

In certain applications we have to deal with signals which contain components which can be described as local phenomena, for example pulses or steps, which have certain time duration. A consequence of applying a filter to a signal is, in intuitive terms, that the duration of the local phenomena is extended by the width of the filter. This implies that it is sometimes important to keep the width of the filter's impulse response function as short as possible. According to the uncertainty relation of the Fourier transform, the product of the width of the filter's impulse response function and the width of its frequency function must exceed a certain constant. This means that any requirement on the filter's locality also implies a bound on its frequency function's width. Consequently, it may not be possible to simultaneously meet requirements on the locality of the filter's impulse response function as well as on its frequency function. This is a typical example of contradicting requirements.

Computational complexity
A general desire in any design is that the number of operations (additions and multiplications) needed to compute the filter response is as low as possible. In certain applications, this desire is a strict requirement, for example due to limited computational resources, limited power resources, or limited time. The last limitation is typical in realtime applications.

There are several ways in which a filter can have different computational complexity. For example, the order of a filter is more or less proportional to the number of operations. This means that by choosing a low order filter, the computation time can be reduced. For discrete filters the computational complexity is more or less proportional to the number of filter coefficients. If the filter has many coefficients, for example in the case of multidimensional signals such as tomography data, it may be relevant to reduce the number of coefficients by removing those which are sufficiently close to zero. Another issue related to computational complexity is separability, that is, if and how a filter can be written the convolution of two or more simpler filters. In particular, this issue is of importance for multidimensional filters, e.g., 2D filter which are used in image processing. In this case, a significant reduction in computational complexity can be obtained if the filter can be separated as the convolution of one 1D filter in the horizontal direction and one 1D filter in the vertical direction. A result of the filter design process may, e.g., be to approximate some desired filter as a separable filter or as a sum of separable filters.

The Transfer Function

The transfer function the input signal

of a filter is the ratio of the output signal as a function of the complex frequency :

to that of


The transfer function of all linear time-invariant filters generally share certain characteristics:

Since the filters are constructed of discrete components, their transfer function will be the ratio of two polynomials in , i.e. a rational funstion of . The order of the transfer function will be the highest power of encountered in either the numerator or the denominator. The polynomials of the transfer function will all have real coefficients. Therefore, the poles and zeroes of the transfer function will either be real or occur in complex conjugate pairs. Since the filters are assumed to be stable, the real part of all poles (i.e. zeroes the denominator) will be negative, i.e. they will lie in the left half-plane in complex frequency space.

Classification by Transfer Function

Filters may be specified by family and passband. A filter's family is specified by certain design criteria which give general rules for specifying the transfer function of the filter. Some common filter families and their particular design criteria are:

Butterworth filter - no gain ripple in pass band and stop band, slow cutoff Chebyshev filter(Type I) - no gain ripple in stop band, moderate cutoff Chebyshev filter(Type II) - no gain ripple in pass band, moderate cutoff Bessel filter - no group delay ripple, no gain ripple in both bands, slow gain cutoff Elliptic filter - gain ripple in pass and stop band, fast cutoff Optimum "L" filter Gaussian filter - no ripple in response to step function Hourglass filter Raised-cosine filter

Generally, each family of filters can be specified to a particular order. The higher the order, the more the filter will approach the "ideal" filter. The ideal filter has full

transmission in the pass band, and complete attenuation in the stop band, and the transition between the two bands is abrupt (often called brick-wall). Here is an image comparing Butterworth, Chebyshev, and elliptic filters. The filters in this illustration are all fifth-order low-pass filters. The particular implementation -analog or digital, passive or active -- makes no difference; their output would be the same. As is clear from the image, elliptic filters are sharper than all the others, but they show ripples on the whole bandwidth. Each family can be used to specify a particular pass band in which frequencies are transmitted , while frequencies in the stop band (i.e. outside the pass band) are more or less attenuated.

Chapter 3.


[3.1]DESIGN DESCRIPTION:1) We have designed 27 tap FIR filter. 2) FIR Filter usually has many stages. 3) Each stage is referred to as TAP. 4) The organization of a TAP is as shown below.

Organization of a Single Tap

Figure 3.1 : Basic FIR Filter Each stage has a 8-bit register.
1) Input signal 8-bit wide is going through register. 2) The stage of the register is multiplied with the coefficient. 3) The previous input is added to it. The truncated product 8-bit is registered. 4.) The truncated 8 bit o/p and delayed input is fed to the next tap.


Figure 3.2 : 27 Tap FIR Filter


Design of low pass digital FIR of 27 tap satisfying the following properties:
1. pass band cut-off frequency fp=150 hz 2. stop band cut off frequency fs= 250 hz 3. passband ripple Ap=0.1 db 4. stopband atenuation As=40 db 5. sampling frequency F= 1 khz


1. We took up an application of noise filtering with the desired parameters. 2. We calculated the filter coefficients using the kaiser window method . 3. We implemented the design using the direct form of implementation. 4. We made use of registers (as delay), adders, multipliers, and multiplexers for our implementation. 5. To make the multiplication fast we implemented it using the Booth algorithm.

6. We simulated the 27 tap FIR filter in VHDL and checked the result manually and found it to be correct.

The filter coefficients calculated using kaiser window method: h(0)=0.400=h(26) h(1)=0.299=h(25) h(2)=0.089=h(24) h(3)=-0.057=h(23) h(4)=-0.064=h(22) h(5)=0.0001=h(21) h(6)=0.035=h(20) h(7)=0.016=h(19) h(8)=-0.012=h(18) h(9)=-0.014=h(17) h(10)=0.000=h(16) h(11)=0.006=h(15) h(12)=0.002=h(14) h(13)=-0.001=h(13)




-- Uncomment the following lines to use the declarations that are -- provided for instantiating Xilinx primitive components. --library UNISIM; --use UNISIM.VComponents.all;

entity multiplier1 is Port ( m : in std_logic_vector(0 to 7); q : in std_logic_vector(0 to 7); p : out std_logic_vector(0 to 7)); end multiplier1; architecture Behavioral of multiplier1 is begin process(m,q) variable a:std_logic_vector(0 to 7); variable b:std_logic_vector (0 to 8); variable d:std_logic_vector (0 to 1); begin a:="00000000"; b:=q & '0'; for i in 1 to 8 loop d:=b(7) & b(8); case d is when "01" => a:=a + m ; when "10" => a:=a - m ; when others => a:=a ; end case ; b:=a(7) & b(0 to 7);

a:=a(0) & a (0 to 6); end loop; p<= a ; end process; end Behavioral;

MULTIPIER:-: RTL systematic:-:

Figure 3.3 : RTL systematic of Multiplier

MULTIPIER:-: RTL systematic:-:

Figure 3.4 : RTL of Multiplier

MULTIPLIER :-: Simulation Results:-:

Figure -3.5 : Multiplier output


1st input 01000000=0.5 01100000=0.75 00010000=0.125

2nd input 01000000=0.5 00100000=0.25 01100000=0.75

Output 00010000=0.25 00001100=0.1875 00000110=0.0937

[3.6] MAC UNIT(Multiply and Acumulate) :-: CODE:-:


-- Uncomment the following lines to use the declarations that are -- provided for instantiating Xilinx primitive components. --library UNISIM; --use UNISIM.VComponents.all;

entity mac1 is Port ( x : in std_logic_vector(0 to 7); h : in std_logic_vector(0 to 7); z : in std_logic_vector(0 to 7); y : out std_logic_vector(0 to 7)); end mac1; architecture Behavioral of mac1 is component multiplier1 port (m,q :in std_logic_vector (0 to 7); p:out std_logic_vector(0 to 7)); end component; signal y1:std_logic_vector (0 to 7); begin v0:multiplier1 port map (x,h,y1); y<=y1 +z ; end Behavioral;


Figure 3.6 : RTL systematic of MAC


Figure 3.7 : RTL of MAC

MAC:-:simulation results :-:

Figure 3.8 : MAC output

MAC:-:Analysis of output:-:

1st input 01000000=0.5 01000000=0.5 01010101=0.66

2nd input 01000000=0.5 01000000=0.5 01110000=0.875

3rd input 01000000=0.5 01100000=0.75 00100000=0.25

output 01010000=0.75 01110000=1.00 01000101=1.785

Table - 3.2 MAC output

[3.7] CODE:-: 27 TAP FIR FILTER:-:


-- Uncomment the following lines to use the declarations that are -- provided for instantiating Xilinx primitive components. --library UNISIM; --use UNISIM.VComponents.all;

entity fir27 is Port ( x0 : in std_logic_vector(0 to 7); clk : in std_logic; y0 : out std_logic_vector(0 to 7)); end fir27; architecture Behavioral of fir27 is component mac1 port (x,h,z :in std_logic_vector (0 to 7); y:out std_logic_vector(0 to 7)); end component; component multiplier1 port (m,q :in std_logic_vector (0 to 7); p:out std_logic_vector(0 to 7)); end component; signal s1 : std_logic_vector(0 to 7):="00000000"; signal s2 : std_logic_vector(0 to 7):="00000000"; signal s3 : std_logic_vector(0 to 7):="00000000"; signal s4 : std_logic_vector(0 to 7):="00000000"; signal s5 : std_logic_vector(0 to 7):="00000000"; signal s6 : std_logic_vector(0 to 7):="00000000"; signal s7 : std_logic_vector(0 to 7):="00000000";

signal s8 : std_logic_vector(0 to 7):="00000000"; signal s9 : std_logic_vector(0 to 7):="00000000"; signal s10 : std_logic_vector(0 to 7):="00000000"; signal s11 : std_logic_vector(0 to 7):="00000000"; signal s12 : std_logic_vector(0 to 7):="00000000"; signal s13 : std_logic_vector(0 to 7):="00000000"; signal s14 : std_logic_vector(0 to 7):="00000000"; signal s15 : std_logic_vector(0 to 7):="00000000"; signal s16 : std_logic_vector(0 to 7):="00000000"; signal s17 : std_logic_vector(0 to 7):="00000000"; signal s18 : std_logic_vector(0 to 7):="00000000"; signal s19 : std_logic_vector(0 to 7):="00000000"; signal s20 : std_logic_vector(0 to 7):="00000000"; signal s21 : std_logic_vector(0 to 7):="00000000"; signal s22 : std_logic_vector(0 to 7):="00000000"; signal s23 : std_logic_vector(0 to 7):="00000000"; signal s24 : std_logic_vector(0 to 7):="00000000"; signal s25 : std_logic_vector(0 to 7):="00000000"; signal s26 : std_logic_vector(0 to 7):="00000000"; signal s99 : std_logic_vector(0 to 7):="00000000"; signal s30,s31,s32,s33,s34,s35,s36,s37,s38,s39,s40,s41,s42,s43,s44,s45,s46,s47,s48,s49,s50,s51 ,s52 ,s53,s54,s55 : std_logic_vector(0 to 7); signal h0 : std_logic_vector(0 to 7):="01100110"; signal h1 : std_logic_vector(0 to 7):="01001100"; signal h2 : std_logic_vector(0 to 7):="00010110"; signal h3 : std_logic_vector(0 to 7):="11110010"; signal h4 : std_logic_vector(0 to 7):="11110000"; signal h5 : std_logic_vector(0 to 7):="00000000"; signal h6 : std_logic_vector(0 to 7):="00001000"; signal h7 : std_logic_vector(0 to 7):="00000100";

signal h8 : std_logic_vector(0 to 7):="11111101"; signal h9 : std_logic_vector(0 to 7):="00000011"; signal h10 : std_logic_vector(0 to 7):="00000000"; signal h11 : std_logic_vector(0 to 7):="00000001"; signal h12 : std_logic_vector(0 to 7):="00000000"; signal h13 : std_logic_vector(0 to 7):="00000000"; signal h14 : std_logic_vector(0 to 7):="00000000"; signal h15 : std_logic_vector(0 to 7):="00000001"; signal h16 : std_logic_vector(0 to 7):="00000000"; signal h17 : std_logic_vector(0 to 7):="00000011"; signal h18 : std_logic_vector(0 to 7):="11111101"; signal h19 : std_logic_vector(0 to 7):="00000100"; signal h20 : std_logic_vector(0 to 7):="00001000"; signal h21 : std_logic_vector(0 to 7):="00000000"; signal h22 : std_logic_vector(0 to 7):="11110000"; signal h23 : std_logic_vector(0 to 7):="11110010"; signal h24 : std_logic_vector(0 to 7):="00010110"; signal h25 : std_logic_vector(0 to 7):="01001100"; signal h26 : std_logic_vector(0 to 7):="01100110"; begin v1:multiplier1 port map (s99,h0,s30); v2:mac1 port map (s1,h1,s30,s31); v3:mac1 port map (s2,h2,s31,s32); v4:mac1 port map (s3,h3,s32,s33); v5:mac1 port map (s4,h4,s33,s34); v6:mac1 port map (s5,h5,s34,s35); v7:mac1 port map (s6,h6,s35,s36); v8:mac1 port map (s7,s7,s36,s37); v9:mac1 port map (s8,h8,s37,s38); v10:mac1 port map (s9,h9,s38,s39); v11:mac1 port map (s10,h10,s39,s40);

v12:mac1 port map (s11,h11,s40,s41); v13:mac1 port map (s12,h12,s41,s42); v14:mac1 port map (s13,h13,s42,s43); v15:mac1 port map (s14,h14,s43,s44); v16:mac1 port map (s15,h15,s44,s45); v17:mac1 port map (s16,h16,s45,s46); v18:mac1 port map (s17,h17,s46,s47); v19:mac1 port map (s18,h18,s47,s48); v20:mac1 port map (s19,h19,s48,s49); v21:mac1 port map (s20,h20,s49,s50); v22:mac1 port map (s21,h21,s50,s51); v23:mac1 port map (s22,h22,s51,s52); v24:mac1 port map (s23,h23,s52,s53); v25:mac1 port map (s24,h24,s53,s54); v26:mac1 port map (s25,h25,s54,s55); v27:mac1 port map (s26,h26,s55,y0); process(x0,h0,h1,h2,h3,h4,h5,h6,h7,h8,h9,h10,h11,h12,h13,h14,h15,h16,h17,h18,h19, h20 ,h21,h22,h23,h24,h25,h26,clk) begin if clk'event and clk='1' then s26<=s25; s25<=s24; s24<=s23; s23<=s22; s22<=s21; s21<=s20; s20<=s19; s19<=s18; s18<=s17; s17<=s16; s16<=s15;

s15<=s14; s14<=s13; s13<=s12; s12<=s11; s11<=s10; s10<=s9; s9<=s8; s8<=s7; s7<=s6; s6<=s5; s5<=s4; s4<=s3; s3<=s2; s2<=s1; s1<=s99; s99<=x0; end if; end process; end Behavioral;


Figure -3.9 : RTL of FIR


Figure 3.10 : RTL of FIR


Figure - 3.11 : FIR RTL


Figure 3.12 : FIR output







00110011 =(0.2)

01100110= (0.4)


00010100= 0.078


01100110 =(0.4)

01001100= (0.299)


00110111= 0.2148





1. Extensively used in Digital Signal Processing. 2. In filtering problem where linear phase characteristic within the pass band of the filter is required. 3. Defense Application like RADAR. 4. Adaptive Antenna System 5. Adaptive Noise canceling techniques. 6. System Modeling


1. They have an exact linear phase 2. They are always stable., non recursive . 3. The design methods are generally linear. 4. They can be realized efficiently in hardware.

Our FIR filter can be used in noise filtering application where a desired frequency signal has to be passed. We can change our filter to high pass, band pass, or band reject just by manipulating the filter coefficients.



Filters are one the main processing element in any digital processing system .FIR filters are one of the important class of filters because they are guaranteed to be stable and to

have linear phase response, hence they are widely used in digital communication system , in spectral analysis and particularly in application where non-linear phase distortion cannot be tolerated.

The FIR filter output was verified and it is clear from the simulation results that FIR filter works on the basis of shifting and adding i.e. the present output depends on the present input and previous input to the filter. Since this is a low pass fir filter, higher frequencies will be blocked and only low frequencies will be allowed to pass through the filter.


Further our FIR filter can be optimised by increasing the number of taps and also using some coefficient optimization algorithm which will reduce the error probability and increase its accuracy in filtering problems.

REFERENCES:[1]. Dimitris G. Manolakis,2000,Stastical and Adaptive Signal Processing, McGraw Hill.

[2]. JOHN G. PROAKIS, 2007.Digital Signal Processing ,Pearson Education. [3]. VAIDYANATHAN,P.P.1990. Multirate Digital Filters, Filter Bank, Polyphase Networks and Application .Proc IEEE, Vol 78. [4] CROCHIERE,R.E, and RABINER,L.R.1975 Optimum FIR Digital Filter Implementation for Decimation, Interpolation, and Narrow band Filt ering [5] THOMAS J.CAVICCHI ,2000,Digital Signal Processing,Willey Student Edition. [6]. Sanjit K Mitra, Digital Signal Processing, Tata McGraw-Hill Edition 2001. [7]. John G Proakis and Dimitris G Manolakis, Digital signal processing. Pearson Prentice Hall, Fourth Edition. [8]. Dag Stranneby and William Walker, Digital Signal Processing and applications. [9]. Li Tan, Digital Signal Processing. [10].Williams, Arthur B & Taylor, Fred J (1995). Electronic Filter Design Handbook. [11].Rabiner, Lawrence R., and Gold, Bernard, 1975: Theory and Application of Digital Signal [12]. [13].