7.6.2.

Poly-silicon gate technology

An early improvement of the technology was obtained by using a poly-silicon gate. Such gate yields a compact self-aligned structure with better performance. The poly-silicon gate is used as a mask during the implantation so that the source and drain regions are self-aligned with respect to the gate. This self-alignment structure reduces the device size. In addition, it eliminates the large overlap capacitance between gate and drain, while maintaining a continuous inversion layer between source and drain. A further improvement of this technique is the use of a low-doped drain (LDD) structure. As an example we consider the structure shown in Figure 7.6.1. Here a first shallow implant is used to contact the inversion layer underneath the gate. The shallow implant causes only a small overlap between the gate and source/drain regions. After adding a sidewall to the gate a second deep implant is added to the first one. This deep implant has a low sheet resistance and adds a minimal series resistance. The combination of the two implants therefore yields a minimal overlap capacitance and low access resistance.

Figure 7.6.1:

Cross-sectional view of a self-aligned poly-silicon gate transistor with LOCOS isolation

Shown is also the local oxidation isolation (LOCOS). Typically, there would also be an additional field and channel implant. The field implant increases the doping density under the oxide and thereby increases the threshold voltage of the parasitic transistor formed by the metal wiring on top of the isolation oxide. The channel implant provides an adjustment of the threshold voltage of the transistors. The use of a poly-silicon gate has the disadvantage that the sheet resistance of the gate is much larger than that of a metal gate. This leads to high RC time-constants of long poly-silicon lines. Silicides (WSi, TaSi, CoSi etc.) or a combination of silicides and poly-silicon are used to reduce these RC delays. Also by using the poly-silicon only as gate material and not as a wiring level one can further eliminated such RC time delays.

Layout of a CMOS Inverter

This tutorial will guide you through various steps of LAYING out a CMOS inverter.

Introduction
This document contains design guidelines for NT CMOS4S, a 1.2- micron, double polysilicon, double metal N-Well process. Various Layers in the CMOS Transistors CMOS transistors are made up of several layers. A brief summary of the MASKS used to generate these layers is given below. The reader can find an extended summary of these masks in the Layout Manual for CMOS4S, provided by CMC.

N-Well Device Well P-Guard Exclusion Polysilicon Capacitor Polysilicon N+Doping(Exclusion) P+ Doping (Inclusion) Contact Windows Metal 1 Metal 2 Via 1 Passivation Windows

Various Steps For Laying out an Inverter

A CMOS inverter consists of both P-type and N-type MOS devices on the same common substrate. In the case of CMOS4s, we shall be dealing with an N-Well process. This implies that the substrate is of P-type and an N-Well must be etched into the P Substrate. When you open a window in df II, the plane of the screen represents the P-Substrate. The following steps show you how to layout both PMOS and NMOS on the P type substrate. LAYOUT OF A CMOS INVERTER

Place the device wells in the area which shall be active.

Draw a rectangle on the screen of the N-Well as shown below.

Surround the N-WEll with the P-Guard.

Place the polysilicon gates.

Place the Ndope and Pdope masks, overlapping each other.

Add Metal1, Contacts, and Split Contacts.

Connect Input pin to the polysilicon gate.

Connect the Output pin to the metal 1 wire connecting the drains of the two transistors. Connect the Metal 1 to Metal 2 using a "Via". Metal 2 is used for I/O connection purposes only.

Your CMOS inverter is ready for test and simulation.