RISC and CISC Central processing units CPU key component in the computer which decodes instructions received

d from memory and perform transfer, arithmetic, logic and control operations on data stored internally. It also provides one or more buses for transferring instructions, data and control information. RISC reduced instruction set computer single cycle computer CISC complex instruction set computer multiple cycle computer 2.4 ns are required to perform a single microoperation. The maximum rate at which microoperations can be performed is the inverse of 2.4 n.s this is the maximum frequency at which the clock can be operated (measured in MHz) Delay paths that pass through both datapath and control signal limit the clock frequency. Execution of of microoperation = execution of an instruction execution of instructions = clock frequency. Pipeline breaking up the stages of microoperations (delay paths) with registers, called pipeline platforms, which provide temporary storage for data travelling through the pipeline Processing of an instruction with pipeline consists of n 1 steps Latency time length of time required to process an instruction. Pipeline does not decrease the latency time, but improves the processing rate or throughput

3 stages: 1. Operand fetch 0.8 ns Reading register file (0.6) + MUX selection (0.2) Reading register values from the register file and selecting between the register value and a constant by MUX B Platform Flip flop delay 1ns minimum 2. Execution - 1 ns clock period 1 ns maximum clock frequency 1 GH maximum throughput 1 billion instructions / s Platform (0.2) + functional unit (0.8) A function unit operation occurs Platform 3. Write back 1 ns Platform (0.2) +MUX selection (0.2) + write back into register file (0.6) The result saved from the previous stage or the value Data in is selected by MUX D and written back into register file Platform (write part of the register platform) Movement of the data through pipeline is in discrete steps. Length of time in each stage is the same and equals to the clock period The clock period is governed by the longest delay, not average! There are up to three operations at some stage at the same time Pipeline execution pattern diagram Vertical position microoperation Horizontal position clock cycle Throughput of the pipeline datapath is 2.4 times that of conventional one () at best Fillinf and emptying reduce the pipeline speed Filling first two cycles Emptying last two cycles

Pipelined control Stages: 1. Instruction fetch that includes the PC and instruction memory Instruction is fetched from the instruction memory and PC is updated. Platform (instruction register) 2. Instruction decoder + register file read Decoding of the instruction register into control signals AA BA and MB controls signals are used Platform (store control signals to be used later) 3. Function unit + data memory read and write ALU operations, shift operation or memory operation is executed, memory read FS and MS control signals are used Platform (memory write) 4. Register file write Platform (DA MD RW signals)