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[17] M. L. Crow and M. Ilic, The parallel implementation of the waveform relaxation method for transient stability simulations, in Proc. IEEE Trans. Power Syst., 1990, pp. 922932. [18] R. A. Saleh, K. A. Gallivan, M.-C. Chang, I. N. Haij, D. Smart, and T. N. Trick, Parallel circuit simulation on supercomputers, in Proc. IEEE, 1989, pp. 19151931. [19] L. Dagum and R. Menon, OpenMP: An industry standard API for shared-memory programming, in Proc. IEEE CompUT. Science Eng., 1998, pp. 4655. [20] J. Hensley, A. Lastra, and M. Singh, An area- and energy-efcient asynchronous booth multiplier for mobile devices, in Proc. ICCD, 2004, pp. 1825. [21] V. Salapura, R. Bickford, M. Blumrich, A. A. Bright, and D. Chen, Power and performance optimization at the system level, in Proc. CF, 2005, pp. 125132. [22] J. Blazewicz, K. H. Ecker, E. Pesch, G. Schmidt, and J. Weglarz, Scheduling Computer and Manufacturing Processes. Berlin, Germany: Springer-Verlag, 1996. [23] R. Jejurikar, C. Periera, and R. Gupta, Leakage aware dynamic voltage scaling for real-time embedded systems, in Proc. DAC, 2004, pp. 275280. [24] R. Xu, D. Mosse, and R. Melhem, Practical pace for embedded systems, in Proc. EMSoft, 2004, pp. 5463.

An Accumulator-Based Compaction Scheme For Online BIST of RAMs

Ioannis Voyiatzis

AbstractTransparent built-in self test (BIST) schemes for RAM modules assure the preservation of the memory contents during periodic testing. Symmetric transparent BIST skips the signature prediction phase required in traditional transparent BIST schemes, achieving considerable reduction in test time. In symmetric transparent BIST schemes proposed to date, output data compaction is performed using either single-input or multipleinput shift registers whose characteristic polynomials are modied during testing. In this paper the utilization of accumulator modules for output data compaction in symmetric transparent BIST for RAMs is proposed. It is shown that in this way the hardware overhead, the complexity of the controller, and the aliasing probability are considerably reduced. Index TermsOnline testing, random access memories (RAMs), self testing.

I. INTRODUCTION Embedded semiconductor memories tend to play an increasingly important role in the operation of integrated circuits and systems. Since advances in memory technology tend to make memory devices more and more complicated (due to the appearance of new defect mechanisms), considerable effort has been put to the direction of efciently testing such modules [1][4], [14][21]. RAMs are typically discerned into bit- and word-organized [4]. For the testing of embedded RAMs, march algorithms outperform competitive schemes, since they result in simple, yet effective, testing scenarios [5]. A march algorithm comprises a series of march elements

Manuscript received December 15, 2006; revised September 20, 2007. First published July 25, 2008; last published August 20, 2008 (projected). A preliminary version of this work was presented in the First IEEE Conference on Design and Test in Deep Submicron Technology, Tunis, August 2006. The author is with the Department of Informatics, Technological Educational Institute of Athens, Athens 12210, Greece (e-mail: voyageri@otenet.gr). Digital Object Identier 10.1109/TVLSI.2008.2000868

that perform a predetermined sequence of operations (read and/or write) in every cell (for the case of bit-organized RAMs) or word (for the case of word-organized RAMs). Testing of RAM modules is performed both right after manufacturing and periodically in the eld. During manufacturing testing, various kinds of tests are applied in order to ensure that the RAM operates normally; typical tests applied during manufacturing testing are march tests. Traditional march algorithms, e.g., [5][7], start with an initial write-all-zero phase, where all the RAM cells are set to 0 in order to ensure that the nal signature in the output compactor is known [5]. Periodic testing is discerned into start-up testing and testing during normal operation. Start-up testing is performed during the start-up of the system and resembles manufacturing testing. In testing during normal operation, the RAM normal operation is stalled (i.e., set out of normal operation), tested and then given back to operation. This kind of testing is applied to circuits where it is difcult and/or impractical to shut down the system since the contents of the RAM cannot be lost. In this kind of testing, traditional march tests cannot be applied since (due to the initial write-all zero phase) the contents of the RAM cells before the test are lost. In order to confront the previously mentioned problems, transparent built-in self test (BIST) was proposed by Nicolaidis [1]; in a transparent BIST algorithm, the initial write-all-zero phase is skipped; instead, a signature prediction phase is issued that precedes the normal march series. During this signature prediction phase, a signature is captured and stored. In the sequel, a sequence of carefully selected read and write operations are performed, that leave the RAM contents equal to the initial ones with the same fault coverage of the corresponding traditional march algorithm; the nal signature is compared to the one captured during the signature prediction phase and a decision is made as to whether a fault has occurred in the RAM or not. The concept of transparent BIST is further analyzed in Section II-B. Yarmolik et al. [8], [9] advanced the eld proposing the concept of symmetric transparent BIST. In symmetric transparent BIST, the signature prediction phase is skipped and the march series is modied in such a way that the nal signature is equal to the all-zero state, irrespectively of the RAM initial contents. For response compaction of bit organized RAMs, in [8] a single-input shift register (SISR) was utilized whose characteristic polynomial toggles between a primitive polynomial and its reciprocal one during the different march elements of the march series. For the case of word-organized RAMs, it was proven in [9] that a multiple-input shift register (MISR) whose characteristic polynomial is altered in a similar fashion could serve as response compactor for symmetric transparent BIST, resulting in a predetermined (all-zero) state. The concept of symmetric transparent BIST is analyzed and exemplied in Section II-C. The work of Yarmolik et al., although revolutionary, requires modifying existing registers (or SISRs/MISRs) in order to serve as response evaluators and requires complicated control logic in such way to toggle between the two different polynomials during the application of the march series. It is widely accepted by the test community that the utilization of modules that typically exist in the circuit, e.g., accumulators [10] or arithmetic logic units (ALUs) [11], for BIST test pattern generation and/or response verication possesses advantages, such as lower hardware overhead and elimination of the need for multiplexers in the circuit path; furthermore, the modules are exercised, therefore, faults existing in them can be discovered [12]. In this paper, we propose the use of accumulator-based compaction in symmetric transparent RAM BIST (ASTRA). In modules that contain accumulators, the output of the RAM is either directly driven to the accumulator inputs or can be driven using processor instructions. It is shown that the proposed scheme imposes lower hardware overhead

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Fig. 1. C- march algorithm: (a) original version; (b) transparent version; and (c) symmetric transparent version.

and less complexity in the control circuitry than previously proposed schemes. This paper is organized as follows. In Section II, a review of the march algorithms (traditional, transparent, and symmetric transparent) is given. In Section III, the proposed accumulator-based compaction scheme for symmetric transparent BIST (ASTRA) is introduced and exemplied for the case of word-organized RAMs. Next, in Section IV, the proposed scheme is compared to previously proposed schemes for response compaction in symmetric transparent BIST. Finally, in Section V, we conclude this paper. II. MARCH ALGORITHMS A. Traditional March Algorithms A march algorithm consists of n march elements, denoted by Mi , with 0  i < n. Each march element comprises zero (or more) write operations, denoted by w0 =w1 meaning that 0/1 is written to the RAM cell, and zero (or more) read operations denoted by r0 =r1 , meaning that 0/1 is expected to be read from the memory cell. For example, the Calgorithm [see Fig. 1(a)] consists of six march elements denoted by M0 to M5 [5]. In Fig. 1, * denotes an increasing addressing order (which can be any arbitrary addressing order) and + denotes a decreasing addressing order (which is the inverse addressing order of *). B. Transparent BIST Algorithms Traditional march algorithms erase the memory contents prior to testing, therefore, they do not serve as good platforms for periodic BIST. Nikolaidis [1] proposed the concept of transparent BIST where the initial w0 phase is bypassed, and a signature prediction phase is used instead. The signature prediction phase consists of read operations equivalent to all the read operations of the march algorithm and it is utilized in order to calculate a signature that will be compared against the compacted signature calculated during the (remaining) march test. The transparent version of the C-algorithm is shown in Fig. 1(b). The notation for the transparent versions of the algorithms differs slightly from the one used in traditional march algorithms. Instead of r0 , r1 , w0 , w1 , c c the notations ra , ra , wa , wa and (ra )c are utilized. Their meanings are as follows.

By default, the data driven to the compactor with the (ra )c operation c are identical to the data driven by the ra . The importance of the (ra )c operation is the following: during the signature prediction phase the contents of the RAM are equal to the initial contents (since no write opc eration has been performed); therefore, in order to simulate the ra operation we invert these contents prior to driving them to the compactor. It has been shown in [1] and [2] that, with the transparent BIST algorithms, the contents of the memory at the end of the test are identical to those before the test. Also, since the read elements of the signature prediction phase (M0 ) are identical to the read elements of the testing phase (M1 -M5 ), then if we store the result of the compaction of M0 and compare it to the result of the compaction of M1 -M5 , then we can detect faults that occur due to the write operations of the march algorithm. Traditional transparent BIST has the disadvantage that the signature prediction phase adds up to the total testing time with a percentage of (more than) 30% [8]. In order to confront this problem, Yarmolik et al. introduced the concept of symmetric transparent BIST, which is explained in the next subsection. C. Symmetric Transparent BIST In order to dene a symmetric transparent algorithm, some notations will be introduced rst. Let d = (d0 ; d1 ; . . . ; dn01 ) 2 f0; 1gn be a data stream, then d3 = (dn01 ; dn02 ; . . . ; d1 ; d0 ) denotes the data c stream with components in reverse order and dc = (d0 ; . . . ; dn01 ) denotes the data stream with inverted components. For example, if d = (1011), d3 = (1101) and dc = (0100). A data string D 2 f0; 1g2n is called symmetric, if there exists a data string d 2 f0; 1gn with D = (d; d3 ) or D = (d; d3c ). For example, D1 = (1010 0101) and D2 = (1010 1010) are symmetric data strings, since (0101) = (1010)3 and (1010) = (1010)3c . Furthermore, a transparent march test is called symmetric if it produces a symmetric test data string D . In order to derive a symmetric transparent algorithm, the march series is modied in such way that the expected output response is equal to a known value. Therefore, the signature prediction phase can be skipped and the time required for the test is reduced. In order to achieve this, Yarmolik et al. [8] noticed that most of the march algorithms used for transparent BIST produce test data with a high degree of symmetry. For example, the read elements of the transparent C- march algorithms [see Fig. 1(b)], ignoring the signature prediction phase (and the write elements) are: * (ra ); c c * (ra ); + (ra ); + (ra ); + (ra ). It is easy to detect the approximate symmetry; furthermore, it is also easy to derive a symmetric sequence by adding an additional read element, resulting in the following c c sequence of read elements: * ((ra )c ); * (ra ); * (ra ); + (ra ); + (ra ); + (ra ). For example, for a bit-organized memory with ve words whose initial contents are (11010), the result of the latter sequence is (00101 11010 00101 j 01011 10100 01011) which is easily shown to be symmetric with respect to the given denition. Yarmolik et al. [8], [9] have shown that by exploiting the previously mentioned symmetry and by using linear structures as compactors for the outputs of the RAM, the nal value of the compactor is equal to a known value, i.e., the all-zero value. For the case of bit-organized memories, SISRs were utilized, while for word-organized memories MISRs were exploited. In [8] and [9], it was proven that by toggling between a primitive polynomial and its reciprocal one during the * r and + r operations, the nal signature is equal to the all-zero state. They even reported marginal increase in the fault coverage of the symmetric schemes compared to the respective transparent ones with signature prediction. For example, in Fig. 1(c) the symmetric transparent version of the C- algorithm is presented.

ra

Read the contents of a word of the RAM, expecting to read the initial contents of the RAM word (i.e., before the beginning of the test). c ra Read the contents of a word of the RAM, expecting to read the complement of the initial contents of the RAM word. (ra )c Read the contents of a word of the RAM expecting to read the initial word contents and feed the complement value to the compactor. wa Write to the memory word; the value that was stored in this memory word at the beginning of the test is (assumed to be) written to the word. c wa Write to the memory word; the inverse of the value that was stored in this memory word at the beginning of the test is (assumed to be) written to the word.

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TABLE I OUTPUT DATA COMPACTION IN SYMMETRIC TRANSPARENT BIST: COMPARISON

Fig. 2. Accumulator-based compaction in word-organized memories.

c c the form (ra ; wa ) or (ra ; wa ) the output of the RAM must be inverted and then fed back to its inputs; with the proposed scheme, this can be done by forcing the all-1 vector to one input of the adder/subtractor and perform a subtract operation. This is done with the OR gates whose one input is driven by the inv signal in Fig. 2. Therefore, the inverse of the read vector appears at the outputs the adder/subtractor and applied to the RAM inputs.

III. ACCUMULATOR-BASED COMPACTION OF THE RESPONSES IN SYMMETRIC TRANSPARENT BIST The accumulator-based response compaction scheme proposed in this paper, stems from the following two observations. 1) Observation 1: If the march algorithm is symmetric (as in the case of symmetric transparent BIST) then the number of ra elements c equals the number of ra elements plus the number of ((ra )c ) elements (without taking into account the addressing order, *, + of the march element). 2) Observation 2: The accumulator-based compaction of the responses holds the order-independent property (i.e., the nal signature is independent of the order of the incoming vectors [13]). Observation 2 stems directly from the permutational property of the addition operation. Accumulator-based compaction for symmetric transparent BIST for the case of word-organized memories is based on Lemma 1. Lemma 1: If a symmetric transparent march algorithm is applied to a word-organized memory whose word length is n and the responses are captured in an n-stage accumulator comprising a 1s complement adder (starting from the all-0 state), then the nal content of the accumulator is equal to the all-1 state. Proof: Let M be the number of elements of the march algorithm; since the algorithm is symmetric, the total number of ra elements is c equal to the total number of ra (plus the number of (ra )c ) elements. Therefore, for every vector a driven to the inputs of the accumulator, its complement ac is also driven to the inputs of the accumulator exactly once. But
n01 c a+a = 2 :

IV. COMPARISONS In this section, we shall compare the proposed scheme with the one proposed in [9], with respect to the required hardware overhead. For the calculations, we assume that a D-type ip-op requires 8 gate equivalents, a ip-op with shift capability requires 10 gates, a ip-op with double-shift capability requires 12 gates, and an XOR gate requires 4 gates. For the scheme proposed in [9], a MISR with double-shift (i.e., both left-to-right and right-to-left) capability is required; in case that a register is available, the transformation of n ip-ops into multiplexed input, two-way ip-ops is required; furthermore, n two-input XOR gates (to invert the values of the outputs of the RAM) and another n two-input XOR gates are required (in case A MISR is not available, in order to transform the register into a MISR). In case that a MISR exists, the transformation of n multiplexed input ip-ops into two-way multiplexed input ip-ops is required. The overhead is presented in Table I. For the implementation of the proposed scheme, assuming the existence of an accumulator, n two-input OR gates are required at the inputs of the accumulator. Since the outputs of the RAM can be driven to the inputs of the accumulator by proper control of the datapath module, no additional overhead is imposed. From Table I, it is evident that the proposed scheme requires lower hardware overhead than the scheme proposed in [9] for the same purpose. V. CONCLUSION In this paper, we have proposed the utilization of accumulators for the compaction of the responses in ASTRA. The proposed scheme presents lower hardware overhead and requires less complicated control compared to the scheme proposed in [9], therefore, it may prove a viable solution for periodic testing of RAMs embedded into current VLSI chips. ACKNOWLEDGMENT

(1)

Furthermore, for 1s complement addition it holds that the sum of two numbers A and B is given by (A 0 1 + B (mod 2n 0 1)) + 1, therefore, the sum of 2n 0 1 and 2n 0 1 is (2n01 0 1+2n01) mod (2n 0 n n 1) + 1 = (2 0 2) + 1 = 2 0 1. Therefore, it is trivial to show (by induction) that (2) holds for any value of i
i n n i 2 (2 0 1) = 2 0 1:

(2)

From (1) and (2), and taking into account that the addition operation is per mutative (Observation 2), we have the proof. For example, let us consider the 4-word 3-bit RAM presented in Fig. 2(a). The outputs of the memory are driven to an n = 3-stage accumulator comprising a 1s complement adder, Fig. 2(b). For the implementation of the (ra)c march element, the subtraction operation of the accumulator can be utilized. In order to apply march elements of

The author would like to thank the anonymous reviewers and the Associate Editor for their constructive comments on the submitted manuscript.

REFERENCES
[1] M. Nicolaidis, Theory of transparent BIST for RAMs, IEEE Trans. Comput., vol. 45, no. 10, pp. 11411156, Oct. 1996. [2] M. Nicolaidis, An efcient built-in self test for functional test of embedded RAMs, in Proc. 15th Symp. Fault Tolerant Comput., Jun. 1985, pp. 118123.

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[3] A. Castro, M. Nicolaidis, P. Lestrat, and B. Courtois, Built-in self test for multi-port RAMs, presented at the ICCAD, Santa Clara, CA, Nov. 1991. [4] A. J. van de Goor, Testing Semiconductor Memories, Theory and Practice. Chichester, U.K.: Wiley, 1991. [5] A. J. van de Goor, Using march tests to test SRAMs, IEEE Des. Test Comput., vol. 10, no. 1, pp. 814, 1993. [6] A. J. van de Goor and C. A. Verruijt, An overview of deterministic functional RAM chip testing, ACM Comput. Surveys, vol. 22, no. 1, pp. 533, Mar. 1990. [7] M. Marinescu, Simple and efcient algorithms for functional RAM testing, in Proc. IEEE Int. Test Conf., 1982, pp. 236239. [8] V. N. Yarmolik, S. Hellebrand, and H.-J. Wunderlich, Symmetric transparent BIST for RAMs, presented at the DATE, Munich, Germany, Mar. 1999. [9] V. N. Yarmolik, I. V. Bykov, S. Hellebrand, and H.-J. Wunderlich, Transparent word-oriented memory BIST based on symmetric march algorithms, in Proc. Eur. Dependable Comput. Conf., 1999, pp. 339350. [10] I. Voyiatzis, Test vector embedding into accumulator-generated sequences: A linear-time solution, IEEE Trans. Comput., vol. 54, no. 4, pp. 476484, Apr. 2005. [11] A. Stroele, BIST patter generators using addition and subtraction operations, J. Electron. Test.: Theory Appl., vol. 11, pp. 6980, 1997. [12] R. Dorsch and H.-J. Wunderlich, Accumulator-based deterministic BIST, in Proc. Int. Test Conf., 1998, pp. 412421. [13] I. Voyiatzis, A. Paschalis, D. Gizopoulos, N. Kranitis, and C. Halatsis, A concurrent built-in self-test architecture based on a self-testing RAM, IEEE Trans. Reliab., vol. 54, no. 1, pp. 6978, Mar. 2005. [14] W. L. Wang, K. J. Lee, and J. F. Wang, An on-chip march pattern generator for testing embedded memory cores, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 9, no. 5, pp. 730735, Oct. 2001. [15] C.-T. Huang, J.-R. Huang, C.-F. Wu, C.-W. Wu, and T.-Y. Chang, A programmable BIST core for embedded DRAM, IEEE Des. Test Comput., vol. 16, no. 1, pp. 5970, Jan./Mar. 1999. [16] J. -F. Li, R.-S. Tzeng, and C.-W. Wu, Diagnostic data compression techniques for embedded memories with built-in self-test, J. Electron. Test.: Theory Appl., vol. 18, pp. 515527, 2002. [17] S. Hamdioui and J. E. Q. D. Reyes, New data-background sequences and their industrial evaluation for word-oriented random-access memories, IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 24, no. 6, pp. 892904, Jun. 2005. [18] S. Hamdioui, Z. Al-Ars, and A. J. van de Goor, Opens and delay faults in CMOS RAM address decoders, IEEE Trans. Comput., vol. 55, no. 12, pp. 16301639, Dec. 2006. [19] W.-L. Wang, K.-J. Lee, and J.-F. Wang, An on-chip march pattern generator for testing embedded memory cores, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 9, no. 5, pp. 730735, Oct. 2001. [20] D.-C. Huang and W.-B. Jone, A parallel built-in self-diagnostic method for embedded memory arrays, IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 21, no. 4, pp. 449465, Apr. 2002. [21] B. H. Fang and N. Nicolici, Power-constrained embedded memory BIST architecture, in Proc. 18th IEEE Int. Symp. Defect Fault Tolerance VLSI Syst. (DFT), 2003, pp. 451458.

Injection-Locked Clocking: A Low-Power Clock Distribution Scheme for High-Performance Microprocessors

Lin Zhang, Aaron Carpenter, Berkehan Ciftcioglu, Alok Garg, Michael Huang, and Hui Wu

AbstractWe propose injection-locked clocking (ILC) to combat deteriorating clock skew and jitter, and reduce power consumption in high-performance microprocessors. In the new clocking scheme, injection-locked oscillators are used as local clock receivers. Compared to conventional clocking with buffered trees or grids, ILC can achieve better power efciency, lower jitter, and much simpler skew compensation thanks to its built-in deskewing capability. Unlike other alternatives, ILC is fully compatible with conventional clock distribution networks. In this paper, a quantitative study based on circuit and microarchitectural-level simulations is performed. Alpha21264 is used as the baseline processor, and is scaled to 0.13 m and 3 GHz. Simulations show 20- and 23-ps jitter reduction, 10.1% and 17% power savings in two ILC congurations. A test chip distributing 5-GHz clock is implemented in a standard 0.18- m CMOS technology and achieved excellent jitter performance and a deskew range up to 80 ps.

I. INTRODUCTION Clock distribution is a crucial aspect of modern multi-gigahertz microprocessor design. Conventional distribution schemes are more or less monolithic in that a single clock source is generated by an on-chip phase-locked loop (PLL) and then fed through hierarchies of clock buffers and interconnects to eventually drive the entire chip (see Fig. 1). This raises a number of challenges. First, the nonuniform load of the clock network and deteriorating process, voltage, and temperature (PVT) variations give rises to spatial timing uncertainties known as clock skews. To minimize the global clock skew, the global clock-distribution network has to be balanced by meticulous design of the interconnects and buffers [5]. This practice puts a very demanding constraint on the physical design of the chip. Another practice is to use a grid instead of a tree for clock distribution, as shown in the upper-left local clock region in Fig. 1. A grid has a lower resistance than a tree between two end nodes, and hence can reduce skew. However, a grid usually has much larger parasitic capacitance (due to larger metal area) than an equivalent tree, and therefore takes more power to drive. Passive and active deskew methods have also been employed to compensate skew after chip fabrication. Unfortunately, these approaches often increase the circuit complexity, chip area, and power consumption. Second, given the substantial load of the clock, sending a high quality clock signal to every corner of the chip requires driving the clock distribution network hard, usually in full swing of the power supply voltage. Not only does this mean high power expenditure, but it also requires a chain of clock buffers, which are subject to power supply noise and hence add delay uncertainty-jitter. Unlike skew, (short-term) jitter is very difcult to compensate due to its random nature and thus poses an even larger threat to microprocessor performance and power consumption. To reduce jitter, the interconnect
Manuscript received February 19, 2007; revised October 2, 2007. Published August 20, 2008 (projected).This paper is a preliminary version of the technical report Injection-locked clocking: a lower-power clock distribution scheme for high-performance microprocessors. This work was supported in part by National Semiconductor and by NSF under Grant 0509270 and Grant 0719790. The authors are with the Department of Electrical and Computer Engineering, University of Rochester, Rochester, NY 14627 USA (e-mail: linzhang@ece. rochester.edu; carpente@ece.rochester.edu; ciftciog@ece.rochester.edu; garg@ece.rochester.edu; huang@ece.rochester.edu; hwu@ece.rochester.edu). Color versions of one or more of the gures in this paper are available online at http://ieeexplore.ieee.org Digital Object Identier 10.1109/TVLSI.2008.2000976

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