Clock Skew In circuit design, clock skew is a phenomenon in synchronous circuit in which the clock signal arrives at different

components at different times. This can be caused by many different things, such as wireinterconnect length, temperature variations and differences in input capacitance on the clock inputs of devices using the clock It is a fundamental design principle that timing must satisfy register setup and hold time requirements. What is local-skew, global-skew,useful-skew mean? Local skew : The difference between the clock reaching at the launching flop vs the clock reaching at the destination flip-flop of a timing-path. Global skew : The difference between the earliest reaching flip-flop and latest reaching flip-flop for a same clock-domain. Useful skew: Useful skew is a concept of delaying the capturing flip-flop clock path, this approach helps in meeting setup requirement within the launch and capture timing path. But the hold-requirement has to be met for the design. What are the various timing-paths which i should take care in my STA runs? 1. Timing path starting from an Input-port and ending at the Output port (purely combinational path). 2. Timing path starting from an Input-port and ending at the Register. 3. Timing path starting from an Register and ending at the Output-port. 4. Timing path starting from an Register and ending at the Register.

What are the various Design constraints used while performing Synthesis for a design? 1. 2. 3. 4. 5. 6. 7. 8. 9. Create the clocks ( Frequency, Duty-Cycle). Define transition-time requirements for the input-ports Specify load values for the output ports For the inputs and the outputs, specify the delay values (input delay and ouput delay), which are already consumed by the neighbour chip. Specify the case-setting (in case of a mux) to report the timing to a specific paths. Specify the False-paths in the design Specify the Multi-cycle paths in the design. Specify the clock-uncertainity values (with respect to jitter and the margin values for setup/hold). Specify few verilog constructs which are not supported by the synthesis tool.

case-setting (in case of a mux) to report the timing to a specific paths.

What is meant by wire-load model? In the synthesis tool, in order to model the wires we use a concept called Wireload models. Wireload models are statistical based on models with respect to Fanout. Say, for a particular technology based on our previous chip experience we have a rough estimate we know if a wire goes for "n" number of fanout, then we estimate its delay as say "x" delay units. So a model file is created with the fanout numbers and corresponding estimated delay values. This file is used while performing Synthesis to estimate the delay for Wires and to estimate the delay for cells. What is STA? STA stands for Static Timing Analysis, which is used to check whether the design meets the timing requirements across all the timing arcs. What do you mean by Timing arcs? Setup Timing Check, Hold Timing Check and Clock-gating Check. Tell me about the path delays. The fundamental aim of STA is to measure the delay of every path. The value for gate delays comes from the vendor library. Interconnect delays are either estimated during synthesis or extracted after P&R. The summation of all the gates propagation delay and the interconnect delays are used to calculate the path delay. Just like synthesis, the STA is best suited for synchronous design. What is False path? As the STA tool determines delay, it considers only the paths that actually affect the output. If the path is never activated or sensitized, it can't contribute to the delay. Any path that doesn't change or doesn't affect the operation of the circuit should also be labeled as false path. What is Multi cycle path? They are the paths that intentionally require more than one clock cycle to become stable. Therefore, they require special multi-cycle setup and hold time calculations. Declaring the multi-cycle path tells the tool to adjust its measurements so it doesn't incorrectly report timing violations. Setup violations occurs when the data path is too slow compared to the clock speed. Hold violations occurs when data is too fast when compared to the clock speed. Clock Reversing: Clock reversing is another method to get around the problem of short data paths and clock skew. In this method, the clock signal arrives at the receiving FF earlier than the source FF. Therefore, the receiving FF will clock in the transmitting FF's value before the transmitting FF receives its clock edge.

Clock Tree Synthesis Now-a-days, designing clock-distribution networks for high-speed chips is more complex than just meeting timing specifications. Achieving clock latency and clock skew are difficult when you have clock signals of 300 MHz or more transversing the chip. Because the clock network is one of the most powerhungry nets on a chip, you need to design with power dissipation in mind. The basics of CTS is to develop the interconnect that connects the system clock into all the cells in the chip that uses the clock. For CTS, your major concerns are,

Minimizing the clock skew Optimizing clock buffers to meet skew specifications and Minimize clock-tree power dissipation

The primary job of CTS tools is to vary routing paths, placement of the clocked cells and clock buffers to meet maximum skew specifications. For a balanced tree without buffers (before CTS), the clock line's capacitance increases exponentially as you move from the clocked element to the primary clock input. The extra capacitance results from the wider metal needed to carry current to the branching segments. The extra metal also results in additional chip area to accommodate the extra clock-line width. Adding buffers at the branching points of the tree significantly lowers clock-interconnect capacitance, because you can reduce clock-line width toward the root. When designing a clock tree, you need to consider performance specifications that are timing-related. Clock-tree timing specifications include clock latency, skew, and jitter. Non-timing specifications include power dissipation, signal integrity. Many clock-design issues affect multiple performance parameters; for example, adding clock buffers to balance clock lines and decrease skew may result in additional clock-tree power dissipation. The biggest problem we face in designing clock trees is skew minimization. The factors that contribute to clock skew include loading mismatch at the clocked elements, mismatch in RC delay. Clock skew adds to cycle times, reducing the clock rate at which a chip can operate. Typically, skew should be 10% or less of a chip's clock cycle, meaning that for a 100-MHz clock, skew must be 1 nsec or less. High-performance designs may require skew to be 5% of the clock cycle. Balanced clock tree : The delays from the root of the clock tree to leaves are almost same. Clock distribution: The main task of clock distribution is to distribute the clock signal across the chip in order to minimize the clock skew. Clock buffer: To keep equal rise and fall delays of the clock signal. Global skew: Difference in clock timing paths b/w any combination of two FFs in the design within the same clock domain. Local skew : Balances the skew only b/w related FF pairs. FFs are related only when one FF launches date which is captured by the other.

Engineering Change Order (ECO) I wanted to know about the ECO and how the flow will be. Recently I had a great time to work on the ECO netlist. In chip design, ECO is the process of inserting a logic change directly into the netlist after it has already been processed by an automatic tool. Before the chip masks are made, ECOs are usually done to save time, by avoiding the need for full ASIC synthesis. EDA tools are often built with incremental modes of operation to facilitate this type of ECO. Re-timing is based on the concept of balancing out the positive and negative slacks throughout the design. In this context, the positive slack means, the amount of time by which the conditions are met and negative slack means, the amount of time by which the condition is not met. Pipelinining: Combinational logic broken into individual blocks to increase your throughput.