ES LAB Report

M.V.S.
R Engineering College, Nadergul
DEPT OF I.T
EMBEDDED SYSTEM PRACTICALS LAB REPORT

(BIT(BIT-481)
Name of the Student : ____________________________________ Roll Number Class Year : ______________ : ______________ Sec : ______________ _________
DEPARTMENT OF INFORMATION TECHNOLOGY INFORMATION TECHNOLOGY
M. V. S. R ENGINEERING COLLEGE R.
(AFFILIATED TO OSMANIA UNIVERSITY HYD. & RECOGNISED BY AICTE, NEW DELHI) UNIVERSITY, .
NADERGUL (P.O), HYDERABAD-501 510. (P.O), HYDERABAD510.
EMBEDDED SYSTEM PRACTI CTICALS LAB REPORT
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M.V.S.R Engineering College, Nadergul
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M. V. S. R. ENGINEERING COLLEGE R.
(AFFILIATED TO OSMANIA UNIVERSITY, HYD. & RECOGNISED BY AICTE, NEW DELHI)
NADERGUL NADERGUL (P.O), HYDERABAD-501 510. HYDERABAD510.
DEPARTMENT OF INFORMATION TECHNOLOGY INFORMATION
CERTIFICATE
Certified that it is a bonafi bonafied laboratory work of experiments oratory carried out by Mr. /Miss. ______________________________ Miss. __________________________________bearing Roll. No. __________________ under the laboratory course of Embedded . he System Practicals Lab prescribed for B.E 4/4 - I. T - II SEM class during the academic year ___________ prescribed by Osmania University ____________ University.
Staff Member I/C
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M. V. S. R. ENGINEERING COLLEGE
INDEX
Sl. No Date Title of the Experiment Page no Remarks
PART A: FPGA Based Applications using VHDL 1. 2. 3. 4. 5. 6. Design and Implementation of all logic gates. Design and Implementation of Half adder and Full adder. Design and Implementation of Half subtractor and Full subtractor. Design and Implementation of basic Flip Flops. Design and Implementation of 4-BIT ALU. Design and Implementation of 16-BIT PRBS. PART B: AT89C51 Microcontroller Based Applications 7. 8. 9. 10. 11. 12. 13. 14. 15. Design and Implementation of Interface an LED. Design and Implementation of Interfacing four LEDs. Design and Implementation of Interfacing Switch and LED. Design and Implementation of Interfacing a Buzzer. Design and Implementation of Interfacing a RELAY. Design and Implementation of Interfacing Timer. Design and Implementation of Interfacing of LCD in 4-Bit mode. Design and Implementation of Interfacing of Stepper Motor. Design and Implementation of Interfacing RS-232 Serial communication. PART C: VxWorks Based Applications 16 17 To demonstrate how to time a single subroutine using the VxWorks timex () routine. To demonstrate how to initiate multiple processes using Vxworks tasking routines.
Staff Member I/C
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PART-A ARTFPGA Based Applications
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FPGA Programming What is an FPGA? A field-programmable gate array (FPGA) is an integrated circuit designed to be configured by the customer or designer after manufacturing. The FPGA configuration is generally specified using a hardware description language (HDL). Instead of being restricted to any predetermined hardware function, an FPGA allows you to program product features and functions, adapt to new standards, and reconfigure hardware for specific applications even after the product has been installed in the field hence the name "field-programmable". FPGAs contain programmable logic components called "logic blocks", and a hierarchy of reconfigurable interconnects that allow the blocks to be "wired together"somewhat like many (changeable) logic gates that can be inter-wired in (many) different configurations. Logic blocks can be configured to perform complex combinational functions, or merely simple logic gates like AND and XOR. In most FPGAs, the logic blocks also include memory elements, which may be simple flipflops or more complete blocks of memory. FPGA Configuration: Spartan-II family: the XC2S200. As high-volume designs grow more complex, the need for higher density, increased memory, and greater I/O count grows as well. For these designs, the XC2S200 fits the bill by featuring up to 200,000 system gates, 14 total RAM blocks, and up to 284 I/Os in three low-cost, high-volume packages: PQ208, FG256, and FG456.
The Xilinx Spartan-IIE FPGAs have the model number (XC2S200E), package type (PQ208), and speed grade (6) printed on the top of the chip.
About Xilinx
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Xilinx ISE is a software tool produced by Xilinx for synthesis and analysis of HDL designs, which enables the developer to synthesize ("compile") their designs, perform timing analysis, examine RTL diagrams, simulate a design's reaction to different stimuli, and configure the target device with the programmer. About VHDL VHDL (VHSIC hardware description language) is a hardware description language used in electronic design automation to describe digital and mixed-signal systems such as field-programmable gate arrays and integrated circuits. VHDL is commonly used to write text models that describe a logic circuit. Such a model is processed by a synthesis program, only if it is part of the logic design. A simulation program is used to test the logic design using simulation models to represent the logic circuits that interface to the design. This collection of simulation models is commonly called a testbench.
Precautions
Insert power cable in proper direction and power ON. The hardware connections must be carefully done. Adjust input switch settings using toothpicks. Insert J-TAG cable properly.
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NADERGUL (P.O), HYDERABAD-501 510. HYDERABAD510.
LABORATORY REPORT
Class: 4/4 I.T. - II SEM Laboratory: Embedded System Practical
Name of the Student: _______________________________________________
Roll. No.
: ____________________________ ______________________________
Experiment Name
Date of Experiment :
Date of Submission :
Remarks
Marks/Grade Awarded:
Signature of the Instructor Instructor:
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Experiment 1: Design and Implementation of all logic gates. Aim: VHDL implementation of AND Gate on FPGA Spartan II using Xilinx 8.1i.
Requirements:
Hardware Universal Trainer Kit MXALUK-001 Spartan II FPGA- XC2S200-PQ208 J-TAG connector Desktop PC Software Xilinx 8.1i. Simulators : ISE Simulator Synthesizers : Xilinx ISE
VHDL code for AND gate:
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input Simulation results of 2-input AND gate:
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Aim: VHDL implementation of OR Gate on FPGA Spartan II using Xilinx 8.1i.
Requirements:
VHDL code for OR gate:
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input Simulation results of 2-input OR gate:
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Aim: VHDL implementation of NOT Gate on FPGA Spartan II using Xilinx 8.1i 8.1i.
Requirements:
Hardware Universal Trainer Kit MXALUK niversal MXALUK-001 Spartan II FPGA- XC2S200 XC2S200-PQ208 J-TAG connector Desktop PC Software Xilinx 8.1i. Simulators : ISE Simulator Synthesizers : Xilinx ISE
VHDL code for NOT gate:
: Simulation results of NOT gate:
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Aim: VHDL implementation of NAND Gate on FPGA Spartan II using Xilinx 8.1i.
Requirements:
VHDL code for NAND gate:
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input Gate: Simulation results of 2-input NAND Gate
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Aim: VHDL implementation of NOR Gate on FPGA Spartan II using Xilinx 8.1i.
Requirements:
VHDL code for NOR gate:
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input Simulation results of 2-input NOR gate:
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Aim: VHDL implementation of EXCLUSIVE-OR Gate on FPGA Spartan II using Xilinx 8.1i.
Requirements:
VHDL code for EXCLUSIVE-OR gate:
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input EXCLUSIVE-OR gate: Simulation results of 2-input EX
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LABORATORY REPORT
Roll. No.
: ____________________________ ______________________________
Experiment Name
Remarks
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Experiment 2: Design and Implementation of Half adder and Full adder. Aim: VHDL implementation of Half Adder on FPGA Spartan II using Xilinx 8.1i.
Requirements:
Theory: The half adder adds two one-bit binary numbers A and B. It has two outputs, S and C (the value theoretically carried on to the next addition); the final sum is 2C + S. The simplest half-adder design, pictured on the right, incorporates an XOR gate for S and an AND gate for C. With the addition of an OR gate to combine their carry outputs, two half adders can be combined to make a full adder.
VHDL code for Half Adder:
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adder: Simulation results of Half adder
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Aim: VHDL implementation of Full adder on FPGA Spartan II using Xilinx 8.1i 8.1i.
Requirements:
Hardware Universal Trainer Kit MXALUK iner MXALUK-001 Spartan II FPGA- XC2S200 XC2S200-PQ208 J-TAG connector Desktop PC Software Xilinx 8.1i. Simulators : ISE Simulator Synthesizers : Xilinx ISE
Theory: A full adder adds binary numbers and accounts for values carried in as well as out. A one one-bit full adder adds three one-bit numbers, often written as A, B, and Cin; A and B are the operands, and Cin is bit a bit carried in from the next less significant stage. The full adder is usually a component in a cascade full-adder of adders, which add 8, 16, 32, etc. binary numbers. The circuit produces a two two-bit output sum typically represented by the signals Cout and S, where .
VHDL code for Full Adder:
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ull adder: Simulation results of Full adder
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LABORATORY REPORT
Roll. No.
: ____________________________ ______________________________
Experiment Name
Remarks
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Experiment 3: Design and Implementation of Half subtractor and Full subtractor. Aim: VHDL implementation of half subtractor on FPGA Spartan II using Xilinx 8.1i.
Requirements:
Theory: The half-subtractor is a combinational circuit which is used to perform subtraction of two bits. It has two inputs, X (minuend) and Y (subtrahend) and two outputs D (difference) and B (borrow).
VHDL code for Half Subtractor:
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Subtractor: Simulation results of Half Subtractor
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Aim: VHDL implementation of Full subtractor on FPGA Spartan II using Xilinx 8.1i.
Requirements:
Theory: The full-subtractor is a combinational circuit which is used to perform subtraction of three bits. It has three inputs, X (minuend) and Y (subtrahend) and Z (subtrahend) and two outputs D (difference) and B (borrow).
VHDL code for Full Subtractor:
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Subtractor: Simulation results of Full Subtractor
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LABORATORY REPORT
Roll. No.
: ____________________________ ______________________________
Experiment Name
Remarks
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Experiment 4: Design and Implementation of basic Flip Flops Flops. Aim: VHDL implementation of SR Flip Flop on FPGA Spartan II using Xilinx 8.1i.
Requirements:
Hardware Universal Trainer Kit MXALUK MXALUK-001 Spartan II FPGA- XC2S200 XC2S200-PQ208 J-TAG connector Desktop PC Software Xilinx 8.1i. Simulators : ISE Simulator Synthesizers : Xilinx ISE
Theory: Flip-flop: Flip-flop is a sequential logic circuit, which is One -bit memory element. OR It i a basic flop bit is memory element in digital systems (same as the bi stable multivibrator) It has two stable state logic bi-stable 1 and logic 0. S-R Flip-flop (Set-Reset) In a memory device set and Reset is often required for synchronization of the device in such ca S-R case Flip-flop is need & this is refereed as clocked set flop set-reset.
Logic diagram
Set-Reset Truth table Reset
VHDL code for SR Flip-Flop:
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Flop: Simulation results of SR Flip-Flop
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Aim: VHDL implementation of D Flip Flop on FPGA Spartan II using Xilinx 8.1i 8.1i.
Requirements:
Theory: D Flip Flop: In D-Flip-flop the transfer of data from the input to the output is delayed and hence the flop utput name delay D-Flip-flop. The D-Type Flip Type Flip-flop is either used as a delay device or as a latch to store 1 evice bit of binary information. D input is transferred to Q output when clock is asserted Logic diagram D-F/F Truth table F/F
VHDL code for D Flip-Flop:
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lop: Simulation results of D Flip-Flop
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Aim: VHDL implementation of JK Flip Flop on FPGA Spartan II using Xilinx 8.1i.
Requirements:
Theory: JK Flip Flop: The race conditions in S Flip-flop can be eliminated by converting it in to J.K, the S-R data inputs J and K are ANDed with Q and Q to obtain S & R inputs. Here SR, T, or D depending on Q\ inputs. Logic Circuit: JK-F/F Truth table:
VHDL code for JK Flip-Flop:
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Flop: Simulation results of JK Flip-Flop
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Aim: VHDL implementation of T Flip Flop on FPGA Spartan II using Xilinx 8.1i mplementation 8.1i.
Requirements:
Hardware Universal Trainer Kit MXALUK ainer MXALUK-001 Spartan II FPGA- XC2S200 XC2S200-PQ208 J-TAG connector Desktop PC Software Xilinx 8.1i. Simulators : ISE Simulator Synthesizers : Xilinx ISE
Theory: T Flip-Flop: On every change in clock pulse the output Q changes its state (Toggle). A Flip-flop with one data input which changes state for every clock pulse. (J=K=1 in JQK Flip Flip-flop the resulting output is T Flip-flop). Logic diagram Truth Table
VHDL code for T Flip-Flop:
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Flop: Simulation results of T Flip-Flop
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LABORATORY REPORT
Roll. No.
: ____________________________ ______________________________
Experiment Name
Remarks
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Experiment 5: Design and Implementation of 4-BIT ALU. Aim: VHDL implementation of 4-BIT ALU on FPGA Spartan II using Xilinx 8.1i.
Requirements:
Theory:
ALU should use combinational logic to calculate an output base on the four bit op-code input ALU should pass the result to the out bus when enable line is high and tri state the out bus when the enable line is low. ALU should decode the 4-bit opcode according to that given below.
OpCode 0000 0001 0010 0011 0100 0101 0110 0111
ALU operation A+B A-B NOT OFA A*B A AND B A NAND B A OR B A XOR B
Truth Table Operation a+b a-b a or b a and b nota a1*b1 a nand b a xor b alu_op(3:0) 0000 0001 0010 0011 0100 0101 0110 0111 op1 1111 1110 1111 1001 1111 1111 1111 0000 op2 0000 0010 1000 1000 0000 1111 0010 0100 alu_out 00001111 00001100 00001111 00001000 11110000 11100001 11111101 00000100
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VHDL code for 4-BIT ALU:
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Simulation results of 4-bit:
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LABORATORY REPORT
Roll. No.
: ____________________________ ______________________________
Experiment Name
Remarks
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Experiment 6: Design and Implementat : Implementation of 16-BIT PRBS. Aim: VHDL implementation of 16-BIT PRBS on FPGA Spartan II using Xilinx 8.1i. mplementation
Requirements:
Theory: The implementation of PRBS generator is based on the linear feedback shift register (LFSR). The PRBS generator produces a predefined sequence of 1's and 0's, with 1 and 0 occurring with the same probability. A sequence of consecutive n*(2^n -1) bits comprise one data pattern, and this pattern will . repeat itself over time.
VHDL code for PRBS:
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bit PRBS: Simulation results of 16-bit PRBS
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PART-B PARTAtmel AT89C51 Microcontroller Based Applications
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Microcontrollers Introduction
A microcontroller is a small computer on a single integrated circuit containing a processor core, memory, and programmable input/output peripherals. Program memory in the form of NOR flash or OTP ROM is also often included on chip, as well as a typically small amount of RAM. Microcontrollers are designed for embedded applications, in contrast to the microprocessors used in personal computers or other general purpose applications. Microcontrollers are used in automatically controlled products and devices, such as automobile engine control systems, implantable medical devices, remote controls, office machines, appliances, power tools, toys and other embedded systems. By reducing the size and cost compared to a design that uses a separate microprocessor, memory, and input/output devices, microcontrollers make it economical to digitally control even more devices and processes. Mixed signal microcontrollers are common, integrating analog components needed to control non-digital electronic systems. Difference between 8051 and 89C51? (Exercise for students)
Precautions:
AT89C51 chip must be inserted properly. The dumping programming into hardware must be handled carefully. The hardware connections must be carefully done.
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LABORATORY REPORT
Roll. No.
: ____________________________ ______________________________
Experiment Name
Remarks
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Experiment 7: Design and Implementation of Interface an LED. Aim: To interface an LED with AT89C51 microcontroller in bit addressing mode. Hardware Requirements: Computer systems-1 GB RAM, 80GB Hard Disk, Pentium 4 processor AT895C1Microcontroller-see for specifications in data sheet no LED Transistor SL100 Resisor-1K, 500 Embedded systems kit
Software Requirements: Operating systems WINDOWS XP RIDE IDE version 06.10.13 RL-51 C compiler EZDL4 downloader
Procedure: Decide the details of electrical connections i.e. interfacing the AT89C51 kit with the LED, with respect to data flow connections from the diagram. Write an embedded C program in RIDE IDE. Save and compile the program using RIDE 51 compiler. Now a HEX code will be generated. Burn the code into AT89C51c using EZDL4 software. Place AT89C51c in the kit. The controller is connected with its peripherals. Power the kit and run. Circuit Diagram:
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Port Map: P0.7 X P0.6 X P0.5 X P0.4 X P0.3 X P0.2 X P0.1 X P0.0 LED
Program:
Result: The interface between the AT89C51 and LED has been successfully carried out.
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LABORATORY REPORT
Roll. No.
: ____________________________ ______________________________
Experiment Name
Remarks
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Experiment 8: Design and Implementation of Interfacing LEDs. Aim: To interfacing four LEDs with an AT89C51 microcontroller in byte addressing mode. Hardware Requirements: Computer systems-1 GB RAM, 80GB Hard Disk, Pentium 4 processor AT895C1Microcontroller -see for specifications in data sheet no 4-LED 4-Transistors SL100 4- 1KResistors Embedded systems kit
Procedure: Decide the details of electrical connections i.e. interfacing the 89C51 kit with the LED, with respect to data flow connections from the diagram. Write an embedded C program in RIDE IDE. Save and compile the program using RIDE 51 compiler. Now a HEX code will be generated. Burn the code into AT89C51 c using EZDL4 software. Place AT89C51 in the kit. The controller is connected with its peripherals. Power the kit and run.
Circuit Diagram:
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Port Map: P0.7 X P0.6 X P0.5 X P0.4 X P0.3 LED4 P0.2 LED3 P0.1 LED2 P0.0 LED1
Program:
Result:
The interface between the 89C51 and LEDs has been successfully carried out.
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LABORATORY REPORT
Roll. No.
: ____________________________ ______________________________
Experiment Name
Remarks
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Experiment 9: Design and Implementation of Interfacing Switch and LED. Aim: To interface switch and LED using interrupts to AT89C51C. Hardware Requirements: Computer systems-1 GB RAM, 80GB Hard Disk, Pentium 4 processor AT895C1Microcontroller-see for specifications in data sheet no Switch and LED Transistor SL100 Resistors1k, 500 Embedded Systems kit Software Requirements: Operating systems WINDOWS XP RIDE IDE version 06.10.13 RL-51 C compiler EZDL4 downloader Procedure: Decide the details of electrical connections i.e. interfacing the AT89C51 kit with the buzzer, with respect to data flow connections from the diagram. Write an embedded C program in RIDE IDE, to interface a switch and LEDs using interrupt for AT89C51c. Save and compile the program using RIDE 51 compiler. Now a HEX code will be generated. Burn the code into AT89C51 microcontroller using EZDL4 software. Place AT89C51 chip in the kit. The controller is connected with its peripherals. Power the kit and run. Circuit Diagram:
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Port Map: P2.7 X P2.6 X P2.5 X P2.4 X P2.3 X P2.2 X P2.1 X P2.0 LED
P1.7 X
P1.6 X
P1.5 X
P1.4 X
P1.3 X
P1.2 X
P1.1 X
P1.0 SWITCH
Program:
Result:
ON and OFF of the LED by the switch check condition is observed by interfacing switch and LED to Microcontroller.
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LABORATORY REPORT
Roll. No.
: ____________________________ ______________________________
Experiment Name
Remarks
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Experiment 10: Design and Implementation of Interfacing a Buzzer. Aim: To interfacing a buzzer with AT89C51microcontroller. Hardware Requirements: Computer systems-1 GB RAM, 80GB Hard Disk, Pentium 4 processor AT89C51Microcontroller -see for specifications in data sheet no Buzzer Transistor SL100 Resisor-330 Embedded systems kit
Software Requirements: Operating systems WINDOWS XP RIDE IDE version 06.10.13 RL-51 C compiler EZDL4 downloader Procedure: Decide the details of electrical connections i.e. interfacing the AT89C51 kit with the buzzer and LED, with respect to data flow connections from the diagram. Write an embedded C program using the RIDE IDE. Save and compile the program using RIDE 51 compiler. Now a HEX code will be generated. Burn the code in AT89C51 using EZDL4 software. Place AT89C51 in the kit. The controller is connected with its peripherals. Power the kit and run. Now the buzzer operates ON and OFF states. Circuit Diagram:
Port Map:
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P0.7 X
P0.6 X
P0.5 BUZZER
P0.4 X
P0.3 LED1
P0.2 LED2
P0.1 LED3
P0.0 LED4
Program:
Result:
The interface between the AT89C51 and buzzer has been successfully carried out.
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LABORATORY REPORT
Roll. No.
: ____________________________ ______________________________
Experiment Name
Remarks
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Experiment 11: Design and Implementation of Interfacing a RELAY. Aim: To interface a relay with AT89C51 microcontroller. Hardware Requirements: Computer systems-1 GB RAM, 80GB Hard Disk, Pentium 4 processor AT 895C1Microcontroller-see for specifications in data sheet no 4-LEDs 4- Transistor SL100 4- Resistors-1K Embedded systems kit Software Requirements: Operating systems WINDOWS XP RIDE IDE version 06.10.13 RL-51 C compiler EZDL4 downloader Theory: A relay is an electro mechanical switch that turns ON and OFF periodically. The timing signals for these periods are generated by 89C51. Procedure: Decide the details of electrical connections i.e. interfacing the 89C51 kit with the relay and LED, with respect to data flow connections from the diagram. Write a program on the system using the RIDE IDE. Save and compile the program using RIDE 51 compiler. Now a HEX code will be generated. Burn the code in AT89C51using EZDL4 software. Place AT89C51 in the kit. The controller is connected with its peripherals. Power the kit and run. Now observe ON and OFF time periods.
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Circuit Diagram:
Port Map:
P0.7 X
P0.6 X
P0.5 X
P0.4 RELAY
P0.3 LED4
P0.2 LED3
P0.1 LED2
P0.0 LED1
Program:
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Result:
The interface between the 89C51 and LED has been successfully carried out through a relay.
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LABORATORY REPORT
Roll. No.
: ____________________________ ______________________________
Experiment Name
Remarks
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Experiment 12: Design and Implementation of Interfacing Timer. : Aim: To interface the on-chip timer with AT89C51 microcontroller microcontroller. Hardware Requirements: Computer systems-1 GB RAM, 80GB Hard Disk, Pentium 4 processor 1 AT 895C1-see for specifications in data sheet no DS1307- Timer Resistor -330, 10k Embedded systems kit Software Requirements: Operating systems WINDOWS XP RIDE IDE version 06.10.13 RL-51 C compiler EZDL4 downloader
Theory: Counters and Timers The 89C51 microcontroller has 2 timers/counters called T0 and T1. As their names suggest, their 51 main purpose is to measure time and count external events. Besides, they can be used for generating clock pulses to be used in serial c communication, so called Baud Rate. Timer T0 As seen in figure below, the timer T0 consists of two registers TH0 and TL0 representing a low and a high byte of one 16-digit binary number. Accordingly, if the content of the timer T0 is equal to 0 digit (T0=0) then both registers it consists of will contain 0. If the timer contains for example number 1000 n (decimal), then the TH0 register (high byte) will contain the number 3, while the TL0 register (low byte) will contain decimal number 232.
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Formula used to calculate values in these two registers is very simple: culate TH0 256 + TL0 = T TMOD Register (Timer Mode) TMOD register decides the source of the clock of the timer. If CLT=0 timer gets pulses from the crystal. When CLT=1 the timer is used as a counter. The TMOD register selects the operational mode of the timers T0 and T1. As seen in figure below, the low 4 bits (bit0 - bit3) refer to the timer 0, while the high 4 bits (bit4 - bit7) refer to the timer 1. There are 4 operational modes and each of them is described herein.
Procedure: Decide the details of electrical connections i.e. interfacing the 89C51 kit with the timer and LEDs with respect to data flow connections from the diagram. Write an embedded C program using the RIDE IDE, for interfacing the timer wi AT89C51 with microcontroller. Save and compile the program using RIDE 51 COMPILER. HEX code will be generated. Burn the code in AT89C 9C51using EZDL4 software. Place AT89C51 in the kit. The controller is connected with its peripherals. 51 Power the kit and run.
Circuit Diagram:
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Port Map: P0.7 X P0.6 X P0.5 X P0.4 X P0.3 LED4 P0.2 LED3 P0.1 LED2 P0.0 LED1
Program
Result:
It can be observed that the pulses were depending upon the LEDs ON and OFF.
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LABORATORY REPORT
Roll. No.
: ____________________________ ______________________________
Experiment Name
Remarks
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Experiment 13: Design and Implementation of Interfacing of LCD in 4-BIT mode. Aim: To interface the LCD in 4-bit mode with AT89C51 microcontroller. Hardware Requirements: Computer systems-1 GB RAM, 80GB Hard Disk, Pentium 4 processor AT 895C1-see for specifications in data sheet no Resisor-4.7K, 5K variable 16X2 LCD Embedded systems kit Software Requirements: Operating systems WINDOWS XP RIDE IDE version 06.10.13 RL-51 C compiler EZDL4 downloader
Theory: LCD (Liquid Crystal Display) screen is a display module and a 16x2 LCD module is very commonly used. Generally LCD works in both 4bit and 8bit mode. The control bit register selects besides if data is to be written is a command or just data. Enable (en) enables the display of strings. It has 3 pins for external power supply. The data to be display is transferred in 4 bits. A 16x2 LCD means it can display 16 characters per line and there are 2 such lines. In this LCD each character is displayed in 5x7 pixel matrix. This LCD has two registers. 1. Command/Instruction Register- stores the command instructions given to the LCD. A command is an instruction given to LCD to do a predefined task like initializing, clearing the screen, setting the cursor position, controlling display etc. 2. Data Register- stores the data to be displayed on the LCD. The data is the ASCII value of the character to be displayed on the LCD. In 4-bit mode the data is sent in nibbles, first we send the higher nibble and then the lower nibble. To enable the 4-bit mode of LCD, we need to follow special sequence of initialization that tells the LCD controller that user has selected 4-bit mode of operation. We call this special sequence as resetting the LCD. The busy flag will only be valid after the above reset sequence. Usually we do not use busy flag in 4-bit mode as we have to write code for reading two nibbles from the LCD.
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Commonly used LCD Command cod codes: Hex Code 1 2 4 6 E 80 C0 38 Command to LCD Instruction Register Clear screen display Return home Decrement cursor Increment cursor Display ON, Cursor ON Force the cursor to the beginning of the 1st line Force cursor to the beginning of the 2nd line Use 2 lines and 5x7 matrix
Procedure: Decide the details of electrical connections i.e. interfacing the 89C51 kit with the LCD in 4 bit mode with respect to data flow connections from the diagram. Write a C program using the RIDE IDE, for interfacing the LCD in 4 bit mode with 89C51. Save and compile the program using RIDE 51 COMPILER. HEX code will be generated. Burn the code in 89C51 using EZDL4 software. Place 89C51 in the kit. The controller is connected with its peripherals. Power the kit and run. Observe the display on the LCD.
Circuit Diagram1:
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Port Map:
P2.7 DB7
P2.6 DB6
P2.5 DB5
P2.4 DB4
P2.3 X
P2.2 X
P2.1 EN
P2.0 RS
Program:
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Result:
The message given in the display function of the program is observed on the LCD. The interface between the 89C51 and LCD in 4-bit mode has been successfully carried out.
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LABORATORY REPORT
Roll. No.
: ____________________________ ______________________________
Experiment Name
Remarks
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Experiment 14: Design and Implementation of Interfacing RS-232 Serial communication. : erial 232 Aim: To interface RS-232 serial communication device using loop back test with AT89C51 microcontroller. Hardware Requirements: Computer systems-1 GB RAM, 80GB Hard Disk, Pentium 4 processor 1 AT 895C1Microcontroller Microcontroller-see for specifications in data sheet no LCD Interface RS-232 Port Embedded systems kit
Theory: The RS-232 interface is the Electronic Industries Association (EIA) standard for the interchange of 232 serial binary data between two devices. Three wires are sufficient: send data, receive data, and signal a ground. The remaining lines can be hardwired on or off permanently. The signal transmission is bipolar, requiring two voltages, from 5 to 25 volts, of opposite polarity. TMOD Register (Timer Mode) TMOD register decides the source of the clock of the timer. If C T=0 timer gets pulses from the C/T=0 crystal. When C/T=1 the timer is used as a counter. T=1 The TMOD register selects the operational mode of the timers T0 and T1. As seen in figure below, the low 4 bits (bit0 - bit3) refer to the timer 0, while the high 4 bits (bit4 - bit7) refer to the timer 1.
SCON (Serial Control, Addresses 98h, Bit Bit-Addressable): The Serial Control SFR is used to configure the behavior of the 8051's o board serial port. This SFR controls the baud rate of the serial on-board port, whether the serial port is activated to receive data, and also contains flags that are set when a byte is successfully sent or received.
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SM0 - Serial port mode bit 0 is used for serial port mode selection. SM1 - Serial port mode bit 1. SM2 - Serial port mode 2 bit, also known as multiprocessor communication enable bit. REN - Reception Enable bit enables serial reception when set. When cleared, serial reception is disabled.
TB8 - Transmitter bit 8. It is set to transmit logic 1 in the 9th bit. RB8 - Receiver bit 8 or the 9th bit received in modes 2 and 3. Cleared by hardware if 9th bit received is logic 0. Set by hardware if 9th bit received is logic 1.
TI - Transmit Interrupt flag is automatically set at the moment the last bit of one byte is sent. RI - Receive Interrupt flag is automatically set upon one byte receive.
Procedure: Decide the details of electrical connections i.e. interfacing the 89C51 kit with the RS232, with respect to data flow connections from the diagram. Write an embedded C program using the RIDE IDE. Save and compile the program using RIDE 51 compiler. Now a HEX code will be generated. Burn the code in AT89C51 using EZDL4 software. Place AT89C51 c in the kit. The controller is connected with its peripherals. Power the kit and run.
Circuit Diagram:
Port Map:
P2.7 DB7 P3.7 X
P2.6 DB6 P3.6 X
P2.5 DB5 P3.5 X
P2.4 DB4 P3.4 X
P2.3 X P3.3 X
P2.2 X P3.2 X
P2.1 EN P3.1 TXD
P2.0 RS P3.0 RXD
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Program:
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Result: The communication between PC and Microcontroller has done. The interface between the 89C51 and LCD has been successfully carried out.
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LABORATORY REPORT
Roll. No.
: ____________________________ ______________________________
Experiment Name
Remarks
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Experiment 15: Design and Implementation of Interfa : Interfacing of Stepper Motor. . Aim: To interface stepper motor with an 89C51 microcontroller. Hardware Requirements: Computer systems-1 GB RAM, 80GB Hard Disk, Pentium 4 processor 1 AT 895C1-see for specifications in data sheet no 4-Diode 1N4007. 4-Transistor BDX 33 4-Resistor-1K Uni polar stepper motor Embedded systems kit
Theory: A stepper motor is a brushless DC electric motor that can divide a full rotation into a large number of steps. The motor's position can be controlled precisely without any feedback mechanism (an openloop controller), as long as the motor is carefully sized to the application. The stepper motor is used ), he for position control in applications such as disk drivers, dot matrix printers, and robotics, etc.
This type of stepper motor is commonly referred to as a four phase stepper motor. The center tap four-phase allows a change of current direction in each of two coils when a winding is grounded, thereby irection resulting in a polarity change of the stator The stepper motor discussed here has a total of 6 leads, 4 leads representing the four stator windings, 2 commons for the center tapped leads. As the sequence of power is applied to each stator winding, s the rotor will rotate.
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Procedure: Decide the details of electrical connections i.e. interfacing the AT89C51 kit with the Stepper 89C51 Motor, with respect to data flow connections from the diagram. Write a program on the system using the RIDE IDE. To operate the stepper motor in clock te wise/anti clockwise direction. Save and compile the program using RIDE 51 compiler. Now a HEX code will be generated. . Burn the code in AT89C using EZLD4 software. 9C51 Place AT89C51 in the kit. The controller is connected with its peripherals. Power the kit and run. Now the stepper motor rotates in both clock wise/anti clockwise directions directions.
Circuit Diagram:
Port Map: P2.7 X P2.6 X P2.5 X P2.4 X P2.3 PHASE4 P2.2 PHASE3 P2.1 PHASE2 P2.0 PHASE1
P0.7 X
P0.6 X
P0.5 X
P0.4 X
P0.3 X
P0.2 X
P0.1 X
P0.0 SWITCH
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Program:
Result: Clockwise and anti clockwise directions of stepper motor have been observed The interface between the 89C51 and Stepper Motor has been carried out.
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PARTPART-C
VxWorks Based Applications
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LABORATORY REPORT
Roll. No.
: ____________________________ ______________________________
Experiment Name
Remarks
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Experiment 16: To demonstrate how to time a single subroutine using the VxWorks timex () routine. Introduction To understand and optimize the performance of a real-time system, it can be useful to time some of the VxWorks and application functions. VxWorks provides a number of timing facilities to help with this task. The VxWorks execution timer can time any subroutine or group of subroutines. To time very fast subroutines, the timer can also repeatedly execute a group of functions until the time of a single iteration is known with reasonable certainty. Objectives The following are the primary objectives of this experiment:
To demonstrate how to time a single subroutine using the VxWorks timex () routine.
Description The timex() routine times a single execution of a specified function with up to eight integer arguments to be passed to the function. When execution us complete, timex() routine displays the execution time and a margin of error in milliseconds. If the execution was so fast relative to the clock rate that the time is meaningless (error > 50%), a warning message will appear. In such cases, use timexN() which will repeatedly execute the function until the time of a single iteration is known with reasonable certainty. 1. Syntax void timex(FUNCPTR function_name, int arg1, .., int arg8) Note: the first argument in timex() routine is a pointer to the function to be timed. 2. Example This small example has two subroutines. The first subroutine "timing" makes a call to timex() with the function name "printit" which is the subroutine to be timed. The arguments are all NULL, so no parameters are being passed to "printit". The second subroutine, "printit", which is being timed iterates 200 times while printing its task id(using taskIdSelf()) and the increment variable "i". #include "vxWorks.h" /* Always include this as the first thing in every program */ #include "timexLib.h" #include "stdio.h" #define ITERATIONS 200 int printit(void);
void timing() /* Function to perform the timing */ { FUNCPTR function_ptr = printit; /* a pointer to the function "printit" */ timex(function_ptr,NULL,NULL,NULL,NULL,NULL,NULL,NULL,NULL); /* Timing the "print" function */ } int printit(void) /* Function being timed */ { int i; for(i=0; i < ITERATIONS; i++) /* Printing the task id number and the increment variable "i" */ printf("Hello, I am task %d and is i = %d\n",taskIdSelf(),i);
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return 0; } Procedures 1. Copy the source code in the example and compile it. 2. Load the object file onto the target machine. 3. Run the example by executing "timing" on the WindSh. Note: Make sure you have redirected I/O, otherwise you won't see the results of the printf commands. Follow On Experiment Experiment 1. Vary the number of ITERATIONS in the loop (300,400,500,600,700) and note the changes in execution speed. Experiment 2. Decrease the number of the iteration to 5, note what happens (you should get a warning message). Write a program to get the timing in this case.
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LABORATORY REPORT
Roll. No.
: ____________________________ ______________________________
Experiment Name
Remarks
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Experiment 17: To demonstrate how to initiate multiple processes using VxWorks tasking routines. Introduction Modern real-time systems are based on the complementary concepts of multitasking and inter task communications. A multitasking environment allows real-time applications to be constructed as a set of independent tasks, each with a separate thread of execution and its own set of system resources. The inter task communication facilities allow these tasks to synchronize and coordinate their activities. The VxWorks multitasking kernel, wind, uses interrupt-driven, priority- based task scheduling. It features fast context switch time and low interrupt latency. Objectives The following are the primary objectives of this experiment:
To demonstrate how to initiate multiple processes using VxWorks tasking routines.
Description Multitasking creates the appearance of many threads of execution running concurrently when, in fact, the kernel interleaves their execution on a basis of a scheduling algorithm. Each apparently independent program is called a task. Each task has its own context, which is the CPU environment and system resources that the task sees each time it is scheduled to run by the kernel. On a context switch, a task's context is saved in the Task Control Block(TCB). A task's context includes:

a thread of execution, that is, the task's program counter the CPU registers and floating-point registers if necessary a stack of dynamic variables and return addresses of function calls I/O assignments for standard input, output, error a delay timer a timeslice timer kernel control structures signal handlers debugging and performance monitoring values
1. Task Creation and Activation The routine taskSpawn creates the new task context, which includes allocating and setting up the task environment to call the main routine(an ordinary subroutine) with the specified arguments. The new task begins at the entry to the specified routine. The arguments to taskSpawn() are the new task's name(an ASCII string), priority, an "options" word(also hex value), stack size(int), main routine address(also main routine name), and 10 integer arguments to be passed to the main routine as startup parameters. 2. Syntax id = taskSpawn(name,priority,options,stacksize,function, arg1,..,arg10); 3. Example This example creates ten tasks which all print their task Id once: #define ITERATIONS 10 void print(void); spawn_ten() /* Subroutine to perform the spawning */ { int i, taskId;
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for(i=0; i < ITERATIONS; i++) /* Creates ten tasks */ taskId = taskSpawn("tprint",90,0x100,2000,print,0,0,0,0,0,0,0,0,0,0); } void print(void) /* Subroutine to be spawned */ { printf("Hello, I am task %d\n",taskIdSelf()); /* Print task Id */ } Procedures 1. Copy the source code in the example and compile it. 2. Load the object file onto the target machine. 3. Run the example by executing "spawn_ten" on the WindSh. Note: Make sure you have redirected I/O, otherwise you won't see the results of the printf commands. Follow On Experiment As shown in the example, the task creation process allows the passing of ten arguments to the function. Experiment 1. As discussed above, up to a ten integer arguments can be passed to a task during the call to taskSpawn(). Pass a unique argument to each of the ten tasks and have them print it. For example, pass the increment variable "i" in subroutine spawn_ten(). Experiment 2. Assign each task a unique priority. Is there any difference in output? Has the order in which the ten tasks print changed? If not, explain why.
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M.V.S.

R Engineering College, Nadergul

EMBEDDED SYSTEM PRACTICALS LAB REPORT

DEPARTMENT OF INFORMATION TECHNOLOGY INFORMATION TECHNOLOGY

NADERGUL (P.O), HYDERABAD-501 510. (P.O), HYDERABAD510.

EMBEDDED SYSTEM PRACTI CTICALS LAB REPORT

M.V.S.R Engineering College, Nadergul

NADERGUL NADERGUL (P.O), HYDERABAD-501 510. HYDERABAD510.

DEPARTMENT OF INFORMATION TECHNOLOGY INFORMATION

Staff Member I/C

EMBEDDED SYSTEM PRACTI CTICALS LAB REPORT

M.V.S.R Engineering College, Nadergul

DEPARTMENT OF INFORMATION TECHNOLOGY INFORMATION

Staff Member I/C

EMBEDDED SYSTEM PRACTICALS LAB REPORT

M.V.S.R Engineering College, Nadergul

PART-A ARTFPGA Based Applications

EMBEDDED SYSTEM PRACTICALS LAB REPORT

M.V.S.R Engineering College, Nadergul

EMBEDDED SYSTEM PRACTICALS LAB REPORT

M.V.S.R Engineering College, Nadergul

EMBEDDED SYSTEM PRACTICALS LAB REPORT

M.V.S.R Engineering College, Nadergul

NADERGUL (P.O), HYDERABAD-501 510. HYDERABAD510.

DEPARTMENT OF INFORMATION TECHNOLOGY INFORMATION

Name of the Student: _______________________________________________

Signature of the Instructor Instructor:

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M.V.S.R Engineering College, Nadergul

VHDL code for AND gate:

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M.V.S.R Engineering College, Nadergul

input Simulation results of 2-input AND gate:

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M.V.S.R Engineering College, Nadergul

Aim: VHDL implementation of OR Gate on FPGA Spartan II using Xilinx 8.1i.

VHDL code for OR gate:

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input Simulation results of 2-input OR gate:

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M.V.S.R Engineering College, Nadergul

VHDL code for NOT gate:

: Simulation results of NOT gate:

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M.V.S.R Engineering College, Nadergul

VHDL code for NAND gate:

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input Gate: Simulation results of 2-input NAND Gate

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M.V.S.R Engineering College, Nadergul

VHDL code for NOR gate:

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M.V.S.R Engineering College, Nadergul

input Simulation results of 2-input NOR gate:

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M.V.S.R Engineering College, Nadergul

VHDL code for EXCLUSIVE-OR gate:

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input EXCLUSIVE-OR gate: Simulation results of 2-input EX

EMBEDDED SYSTEM PRACTI CTICALS LAB REPORT

M.V.S.R Engineering College, Nadergul