Aptio 4.

x Status Codes

Checkpoints & Beep Codes for Debugging

Document Revision 1.12 Revision Date: January 6, 2012

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Disclaimer This publication contains proprietary information which is protected by copyright. No part of this publication may be reproduced, transcribed, stored in a retrieval system, translated into any language or computer language, or transmitted in any form whatsoever without the prior written consent of the publisher, American Megatrends, Inc. American Megatrends, Inc. retains the right to update, change, modify this publication at any time, without notice. For Additional Information Call American Megatrends, Inc. at 1-800-828-9264 for additional information. Limitations of Liability In no event shall American Megatrends be held liable for any loss, expenses, or damages of any kind whatsoever, whether direct, indirect, incidental, or consequential, arising from the design or use of this product or the support materials provided with the product. Limited Warranty No warranties are made, either expressed or implied, with regard to the contents of this work, its merchantability, or fitness for a particular use. American Megatrends assumes no responsibility for errors and omissions or for the uses made of the material contained herein or reader decisions based on such use. Trademark and Copyright Acknowledgments Copyright 2012 American Megatrends, Inc. 5555 Oakbrook Parkway Suite 200 Norcross, GA 30093 All product names used in this publication are for identification purposes only and are trademarks of their respective companies.

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Table of Contents
DOCUMENT INFORMATION
Purpose Audience References Change History Review History

4
4 4 4 4 4

CONCEPT & DESIGN

Introduction Aptio Boot Flow Viewing Checkpoints

5
5 5 5

APTIO CHECKPOINTS
Checkpoint Ranges Standard Checkpoints SEC Phase SEC Beep Codes PEI Phase PEI Beep Codes DXE Phase DXE Beep Codes ACPI/ASL Checkpoints OEM-Reserved Checkpoint Ranges

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6 6 6 7 7 9 9 12 12 12

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Document Information
Purpose
This document lists standard status codes generated by Aptio 4.x core firmware. The checkpoints defined in this document are inherent to the Aptio 4.x core generic core, and do not include any chipset or board specific checkpoint definitions.

Audience
The intended audiences are Generic Chipset Porting Engineers, OEM Porting Engineers, Technicians, and AMI Customers.

References
AMI Debug Rx product page AMI Debug Rx User Manual AMI Debug Rx Quick Start Guide

Change History
Date
2009-03-12 2009-12-30

Revision
1.00 1.10

Description
First Public Version Updated with information on AMI Debug Rx. Corrected some of use of status code where the term checkpoint should be used. Added References section with links to additional documentation. Updated checkpoint values based on latest core implementation. Resorted beep code tables (ascending). Updated properties. Updated information

2009-12-31 2012-01-06

1.11 1.12

Review History
Date Comments Approval

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Concept & Design

Introduction
A status code is a data value used to indicate progress during the boot phase. A subset of these status codes, known commonly as checkpoints, indicate common phases of the BIOS boot process. Checkpoints are typically output to I/O port 80h, but Aptio 4.x core can be configured to send status codes to a variety of sources. Aptio 4.x core outputs checkpoints throughout the boot process to indicate the task the system is currently executing. Checkpoints are very useful in aiding software developers or technicians in debugging problems that occur during the pre-boot process.

Aptio Boot Flow

While performing the functions of the traditional BIOS, Aptio 4.x core follows the firmware model described by the Intel Platform Innovation Framework for EFI (the Framework). The Framework refers the following boot phases, which may apply to various status code & checkpoint descriptions: Security (SEC) initial low-level initialization Pre-EFI Initialization (PEI) memory initialization
1 2

Driver Execution Environment (DXE) main hardware initialization

Boot Device Selection (BDS) system setup, pre-OS user interface & selecting a bootable device (CD/DVD, HDD, USB, Network, Shell, )

Viewing Checkpoints
Checkpoints generated by Aptio firmware can be viewed using a PCI checkpoint card, also referred to as a POST Card or POST Diagnostic Card. These PCI add-in cards show the value of I/O port 80h on a LED display. Checkpoint cards are available through a variety of computer mailorder outlets. Newer systems feature support for AMI Debug Rx, a USB connected alternative to the PCI POST Card. AMI Debug Rx is a low-cost debug tool built around the debug port feature common to todays USB 2.0 EHCI controllers. AMI Debug Rx is designed as replacement for the PCI POST Checkpoint Card as newer systems omit PCI expansion slots. Along with checkpoints, AMI Debug Rx has a number of features specifically designed for BIOS developers.
1 2

Analogous to bootblock functionality of legacy BIOS Analogous to POST functionality in legacy BIOS

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Aptio Checkpoints
Checkpoint Ranges
Status Code Range 0x01 0x0B 0x0C 0x0F 0x10 0x2F 0x30 0x4F 0x50 0x5F 0x60 0x8F 0x90 0xCF 0xD0 0xDF 0xE0 0xE8 0xE9 0xEF 0xF0 0xF8 0xF9 0xFF SEC execution SEC errors PEI execution up to and including memory detection PEI execution after memory detection PEI errors DXE execution up to BDS BDS execution DXE errors S3 Resume (PEI) S3 Resume errors (PEI) Recovery (PEI) Recovery errors (PEI) Description

Standard Checkpoints
SEC Phase
Status Code 0x00 Progress Codes 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B Power on. Reset type detection (soft/hard). AP initialization before microcode loading North Bridge initialization before microcode loading South Bridge initialization before microcode loading OEM initialization before microcode loading Microcode loading AP initialization after microcode loading North Bridge initialization after microcode loading South Bridge initialization after microcode loading OEM initialization after microcode loading Cache initialization Not used Description

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SEC Error Codes 0x0C 0x0D 0x0E 0x0F Reserved for future AMI SEC error codes Microcode not found Microcode not loaded

SEC Beep Codes

None

PEI Phase
Status Code Progress Codes 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 PEI Core is started Pre-memory CPU initialization is started Pre-memory CPU initialization (CPU module specific) Pre-memory CPU initialization (CPU module specific) Pre-memory CPU initialization (CPU module specific) Pre-memory North Bridge initialization is started Pre-Memory North Bridge initialization (North Bridge module specific) Pre-Memory North Bridge initialization (North Bridge module specific) Pre-Memory North Bridge initialization (North Bridge module specific) Pre-memory South Bridge initialization is started Pre-memory South Bridge initialization (South Bridge module specific) Pre-memory South Bridge initialization (South Bridge module specific) Pre-memory South Bridge initialization (South Bridge module specific) OEM pre-memory initialization codes Memory initialization. Serial Presence Detect (SPD) data reading Memory initialization. Memory presence detection Memory initialization. Programming memory timing information Memory initialization. Configuring memory Memory initialization (other). Reserved for ASL (see ASL Status Codes section below) Memory Installed CPU post-memory initialization is started CPU post-memory initialization. Cache initialization CPU post-memory initialization. Application Processor(s) (AP) initialization CPU post-memory initialization. Boot Strap Processor (BSP) selection CPU post-memory initialization. System Management Mode (SMM) initialization Post-Memory North Bridge initialization is started Description

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0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F-0x4E 0x4F PEI Error Codes 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C-0x5F 0xE0 0xE1 0xE2 0xE3 0xE4-0xE7 0xE8 0xE9 0xEA 0xEB 0xEC-0xEF

Post-Memory North Bridge initialization (North Bridge module specific) Post-Memory North Bridge initialization (North Bridge module specific) Post-Memory North Bridge initialization (North Bridge module specific) Post-Memory South Bridge initialization is started Post-Memory South Bridge initialization (South Bridge module specific) Post-Memory South Bridge initialization (South Bridge module specific) Post-Memory South Bridge initialization (South Bridge module specific) OEM post memory initialization codes DXE IPL is started Memory initialization error. Invalid memory type or incompatible memory speed Memory initialization error. SPD reading has failed Memory initialization error. Invalid memory size or memory modules do not match. Memory initialization error. No usable memory detected Unspecified memory initialization error. Memory not installed Invalid CPU type or Speed CPU mismatch CPU self test failed or possible CPU cache error CPU micro-code is not found or micro-code update is failed Internal CPU error reset PPI is not available Reserved for future AMI error codes S3 Resume is stared (S3 Resume PPI is called by the DXE IPL) S3 Boot Script execution Video repost OS S3 wake vector call Reserved for future AMI progress codes S3 Resume Failed S3 Resume PPI not Found S3 Resume Boot Script Error S3 OS Wake Error Reserved for future AMI error codes

S3 Resume Progress Codes

S3 Resume Error Codes

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Recovery Progress Codes 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5-0xF7 0xF8 0xF9 0xFA 0xFB 0xFF Recovery condition triggered by firmware (Auto recovery) Recovery condition triggered by user (Forced recovery) Recovery process started Recovery firmware image is found Recovery firmware image is loaded Reserved for future AMI progress codes Recovery PPI is not available Recovery capsule is not found Invalid recovery capsule Reserved for future AMI error codes

Recovery Error Codes

PEI Beep Codes

# of Beeps 1 1 2 3 3 4 4 7 Description Memory not Installed Memory was installed twice (InstallPeiMemory routine in PEI Core called twice) Recovery started DXEIPL was not found DXE Core Firmware Volume was not found Recovery failed S3 Resume failed Reset PPI is not available

DXE Phase
Status Code 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B Description DXE Core is started NVRAM initialization Installation of the South Bridge Runtime Services CPU DXE initialization is started CPU DXE initialization (CPU module specific) CPU DXE initialization (CPU module specific) CPU DXE initialization (CPU module specific) CPU DXE initialization (CPU module specific) PCI host bridge initialization North Bridge DXE initialization is started North Bridge DXE SMM initialization is started North Bridge DXE initialization (North Bridge module specific)

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0x6C 0x6D 0x6E 0x6F 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7F 0x80 0x8F 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6

North Bridge DXE initialization (North Bridge module specific) North Bridge DXE initialization (North Bridge module specific) North Bridge DXE initialization (North Bridge module specific) North Bridge DXE initialization (North Bridge module specific) South Bridge DXE initialization is started South Bridge DXE SMM initialization is started South Bridge devices initialization South Bridge DXE Initialization (South Bridge module specific) South Bridge DXE Initialization (South Bridge module specific) South Bridge DXE Initialization (South Bridge module specific) South Bridge DXE Initialization (South Bridge module specific) South Bridge DXE Initialization (South Bridge module specific) ACPI module initialization CSM initialization Reserved for future AMI DXE codes OEM DXE initialization codes Boot Device Selection (BDS) phase is started Driver connecting is started PCI Bus initialization is started PCI Bus Hot Plug Controller Initialization PCI Bus Enumeration PCI Bus Request Resources PCI Bus Assign Resources Console Output devices connect Console input devices connect Super IO Initialization USB initialization is started USB Reset USB Detect USB Enable Reserved for future AMI codes IDE initialization is started IDE Reset IDE Detect IDE Enable SCSI initialization is started SCSI Reset SCSI Detect

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0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xBF 0xC0 0xCF 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC

SCSI Enable Setup Verifying Password Start of Setup Reserved for ASL (see ASL Status Codes section below) Setup Input Wait Reserved for ASL (see ASL Status Codes section below) Ready To Boot event Legacy Boot event Exit Boot Services event Runtime Set Virtual Address MAP Begin Runtime Set Virtual Address MAP End Legacy Option ROM Initialization System Reset USB hot plug PCI bus hot plug Clean-up of NVRAM Configuration Reset (reset of NVRAM settings) Reserved for future AMI codes OEM BDS initialization codes CPU initialization error North Bridge initialization error South Bridge initialization error Some of the Architectural Protocols are not available PCI resource allocation error. Out of Resources No Space for Legacy Option ROM No Console Output Devices are found No Console Input Devices are found Invalid password Error loading Boot Option (LoadImage returned error) Boot Option is failed (StartImage returned error) Flash update is failed Reset protocol is not available

DXE Error Codes

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DXE Beep Codes

# of Beeps 1 4 5 5 6 7 8 Description Invalid password Some of the Architectural Protocols are not available No Console Output Devices are found No Console Input Devices are found Flash update is failed Reset protocol is not available Platform PCI resource requirements cannot be met

ACPI/ASL Checkpoints
Status Code 0x01 0x02 0x03 0x04 0x05 0x10 0x20 0x30 0x40 0xAC 0xAA Description System is entering S1 sleep state System is entering S2 sleep state System is entering S3 sleep state System is entering S4 sleep state System is entering S5 sleep state System is waking up from the S1 sleep state System is waking up from the S2 sleep state System is waking up from the S3 sleep state System is waking up from the S4 sleep state System has transitioned into ACPI mode. Interrupt controller is in PIC mode. System has transitioned into ACPI mode. Interrupt controller is in APIC mode.

OEM-Reserved Checkpoint Ranges

Status Code 0x05 0x0A 0x1D 0x2A 0x3F 0x4E 0x80 0x8F 0xC0 0xCF Description OEM SEC initialization before microcode loading OEM SEC initialization after microcode loading OEM pre-memory initialization codes OEM PEI post memory initialization codes OEM DXE initialization codes OEM BDS initialization codes

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