Performance comparison of buffer and schmitt trigger in VLSI interconnects

Sunil raina,Saurabh Chakravarty,K Sivasankaran School of Electronics Engineering VIT University, Vellore-632014, Tamilnadu, India sunil.raina2011,saurabh.chakravarty2011@vit.ac.in; +91-9092055287

Abstract: This paper presents the performance comparison of buffer and Schmitt trigger. Buffers are the inevitable part of VLSI interconnects as they are used for the purpose of delay ,also for power and noise reduction. Although buffers can eliminate the above problems but with a drawback of signal delay, due to certain switching time. To overcome this problem, Schmitt trigger is used in such a way that by adjusting its threshold voltage, the signal can be made to rise early thereby reducing the signal propagation delay. Also due to less switching time, power dissipation is low as compared to buffers. The circuits are simulated in cadence in both 180nm and 90nm technology. Simulation results shows that the Schmitt trigger gives 12.5% delay reduction and 7.75% power reduction as compared to buffer.

Keywords: Interconnects, Buffer, Schmitt trigger, Threshold Voltage

Introduction: With the rapid scaling of technology for the faster operation and better performance of devices, the role of interconnects have become much more significant. When the devices and interconnects are scaled down,the delay of local interconnects remains the same, but the delay of global interconnects increases.As a result, the interconnect delay has become the dominating factor in determining system performance. It has been observed that maximum percentage (approximately 70%) of clock cycles are consumed by interconnect delays[1].Buffers play an important role in VLSI interconnects, and any problem caused by buffer can directly affect the overall system performance. Although buffers are used for the purpose of delay, power and noise reduction but the switching time associated with it can cause significant signal delay in interconnects. To overcome this problem, Schmitt trigger can be used as a replacement of buffer as by changing the threshold voltage of Schmitt trigger the switching time can be reduced, which ultimately reduces the signal delay.

Background As VLSI interconnects play a major role in deep submicron technology [2],so delay associated with it has to be considered into account. Various techniques have been proposed to overcome the delay in interconnects like optimum insertion of buffers in long interconnects to reduce the El-more delay [4],performance optimization algorithm for VLSI interconnects [5], optimum wire segmentation for buffer insertion [6].Apart from these , a few techniques have also been proposed for handling delays in tree structured interconnects. Almost all papers used buffers to reduce the interconnect delays. By considering the effect of RC delays caused by buffers in interconnects, a technique is given in this paper where buffers can be replaced by the given Schmitt trigger.

Design Methodology: The major criteria for choosing Schmitt trigger as an option for buffer is that Schmitt trigger can act as a signal restoring circuit like buffer. As the threshold voltage of Schmitt trigger changes, the switching time also changes accordingly. A low threshold Schmitt trigger doesnt hamper the duty cycle of the waveform due to presence of dual threshold [2] unlike buffers which results in non uniform duty cycle with low threshold. The given Schmitt trigger[Fig-2] consists of three pmos transistors and three nmos transistors. Either of the upper pmos or lower nmos transistors can be considered as the load for each other. The lower two nmos transistors can be considered as a series connection of two resistors. The CMOS buffer used for the comparison consists of two CMOS inverter connected back to back [Fig1].The size of second inverter is four times the size of first inverter to meet the current carrying ability [2].In case of buffer, signal restoration occurs after its input exceeds a voltage of Vdd/2.Whereas a Schmitt trigger can be made to do the same job by adjusting its threshold voltage in such a way that it can operate after its input exceeds the voltage of Vdd/3.Thereby reducing the response time towards incoming signal as compared to buffers.

Figure 1: shows CMOS buffer

Figure 2:shows low voltage CMOS schmitt trigger

Figure 3: Hysteresis of the Schmitt trigger.

Figure 4: Input waveform for the Schmitt trigger.

Delay Analysis: The main aim of using Schmitt trigger in our project rather than buffer is that we can set the threshold limits as per our requirements. when a square wave is given as input to one end of the interconnect, the output at the other end will be delayed due to the RC delay in the interconnects .Ideally the output should be distortion less but due to the presence of parasitic components, it will be somewhat distorted .So we can use Schmitt trigger here for signal restoration. As we know that interconnects play a vital role in DSM technologies. So we have to be very careful about the signal level delay while working with DSM technologies. It is observed that Schmitt trigger gives a better performance as compared to buffers in interconnects. Due to the lower threshold level of Schmitt trigger, we can observe that the

signal rise and fall times are lower giving a fast signal propagation and hence less delay.For 90nm technology, when Schmitt trigger is used in interconnect model as shown in Fig.6 ,we get a delay of 105 psec.For the same model using buffer, we get a delay of 120 psec. So,we can clearly observe that there is a delay reduction of 12.5% using Schmitt trigger as compared to buffers in interconnects. For 180nm technology, we get a delay reduction of 8.85% using given Schmitt trigger. But we can observe that it is more effective in 90nm technology. Moreover, we have varied the supply voltages and observed the changes in delays for both 180 and 90nm technology as shown in figures 7 and 8 respectively.

Figure 5:shows buffers inserted in an RC interconnect model [from 2].

Figure 6:shows Schmitt trigger at the output end of RC interconnect model [from 2].

400 350 300 250 200 150 100 50 0 1.6 1.7 1.8 1.9 2 schmitt trigger buffer

160 140 120 100 80 60 40 20 0 0.8 0.9 1 1.1 1.2 Schmitt Trigger Buffer

Figure 7: delay analysis in 180nm technology

Figure 8: delay analysis in 90nm technology

Power Analysis In Schmitt trigger, either the transistors are in off mode or in on mode due to the early switching of the opposite level. While as in buffer, at Vdd/2 all the transistors are in saturation mode, so it results in more power consumption. For 180nm technology, as shown in figure 6, with Schmitt trigger, it consumes a power of 65.30W and with buffer, it consumes 69.19W power. So, we achieved a power reduction of 5.62% in this case. In 90nm technology, for the same example, with Schmitt trigger, it consumes a power of 2.357W and with buffer, it consumes 2.597W power. So, we achieved a power reduction of 9.24% using Schmitt trigger. It can be observed that in 90nm technology more power reduction is there as compared to 180nm technology. Moreover, we have varied the supply voltages and observed the changes in power for both 180 and 90nm technology as shown in figures 9 and 10 respectively.

120 100 80 60 40 20 Series 1 Series 2

7 6 5 4 3 2 1 0 0.8 0.9 1 1.1 1.2 Schmitt Trigger Buffer

0
1.6 1.7 1.8 1.9 2

Figure 9: power analysis in 180nm technology

Figure 10: power analysis in 90nm technology

Simulation results: The circuits were simulated in cadence for the 180nm and 90nm technology. The model of used interconnect bus including the parasitic resistors and capacitors values have been taken from predictive technology models(PTM)[9].From the result table, we can observe that for 90nm technology, we are getting effective percentage reduction in delay and power as compared to 180nm technology.

Table 1. Performance comparison for buffer and Schmitt trigger Circuit Delay (in ps) Power (in W) 180nm 90nm 180nm 90nm 212 235 105 120 12.5 53.14 55.83 4.82 2.35 2.59 9.27

Schmitt trigger Buffer

Percentage in reduction(%) 9.79

Conclusion In this paper we compared the performance of Schmitt trigger with buffer and we found that when we deal with DSM technologies, Schmitt trigger gives a better performance in terms of delay, power and noise reduction as compared to buffers in interconnects . The only limitation of the above approach is that we have a small increase in area due to the additional use of two transistors in Schmitt trigger as compared to four transistors used in buffer circuit. But overall performance of Schmitt trigger is effective in VLSI interconnects.

References:
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[9] http://www.ptm.asu.edu/