1

Experiment no. 1
Aim: Gilbert Multiplier Cell
(i) DC Transfer characteristics and find the range of maximum input signal which can be applied to Vx and Vy (ii) Application as tone burst generator. Apply a square wave of low frequency (100Hz) at Vx and sine wave of high frequency at Vy (iii)Application as squarer by giving same input signal. Also verify operation as frequency doubler

CIRCUIT DIAGRAM

DC ANALYSIS
.LIB C:\msimev71\lib\EVAL.lib R_Rcm 1 2 10k R_Rl1 1 3 11k R_Rl2 1 4 11k R_Rx 13 14 15k R_Ry 15 16 15k Q_Q1 2 18 5 Q2N2222 Q_Q2 2 18 6 Q2N2222 Q_Q3 3 5 7 Q2N2222 Q_Q4 4 6 7 Q2N2222 Q_Q5 3 6 8 Q2N2222 Q_Q6 4 5 8 Q2N2222 Q_Q7 5 9 13 Q2N2222 Q_Q8 6 16 14 Q2N2222 Q_Q9 7 11 15 Q2N2222 Q_Q10 8 12 16 Q2N2222 VEE 0 17 DC 15V VCC 1 0 DC 15V V_Vx 9 16 DC 1V V_Vy 12 11 DC 1V I_Ix1 13 17 DC 1mA I_Ix2 14 17 DC 1mA I_Iy1 15 17 DC 1mA I_Iy2 16 17 DC 1mA .DC LIN V_Vx -20 20 1 V_Vy -20 20 5 .PROBE .END
20V

10V

0V

-10V

-20V -20V V(3)- V(4)

-15V

-10V

-5V

0V V_Vx

5V

10V

15V

20V

TONE BURST GENERATOR

.LIB C:\msimev71\lib\EVAL.lib R_Rcm 1 2 10k R_Rl1 1 3 11k R_Rl2 1 4 11k R_Rx 13 14 15k R_Ry 15 16 15k Q_Q1 2 18 5 Q2N2222 Q_Q2 2 18 6 Q2N2222 Q_Q3 3 5 7 Q2N2222 Q_Q4 4 6 7 Q2N2222 Q_Q5 3 6 8 Q2N2222 Q_Q6 4 5 8 Q2N2222 Q_Q7 5 9 13 Q2N2222 Q_Q8 6 16 14 Q2N2222 Q_Q9 7 11 15 Q2N2222 Q_Q10 8 12 16 Q2N2222 VEE 0 17 DC 15V VCC 1 0 DC 15V V_Vx 9 16 sin(0 1 1k) V_Vy 12 11 PULSE(0 1 0 0 0 5ms 10ms) I_Ix1 13 17 DC 1mA I_Ix2 14 17 DC 1mA I_Iy1 15 17 DC 1mA I_Iy2 16 17 DC 1mA .TRAN 0.001ms 50ms 0 0.001ms .PROBE .END
120mV

80mV

40mV

0V

-40mV

-80mV

-120mV 0s 5ms V(3) - V(4) 10ms 15ms 20ms 25ms Time 30ms 35ms 40ms 45ms 50ms

SQUARER
* Gilbert Multiplier Squarer .Lib "nom.Lib" Vcc 1 0 15V Vee 0 17 15V Q1 2 2 5 Q2N2222 Q2 2 2 6 Q2N2222 Rcm 1 2 10K Rl1 1 3 11K Rl2 1 4 11K Q3 3 5 7 Q2N2222 Q4 4 6 7 Q2N2222 Q5 3 6 8 Q2N2222 Q6 4 5 8 Q2N2222 Q7 5 9 13 Q2N2222 Q8 6 10 14 Q2N2222 Q9 7 11 15 Q2N2222 Q10 8 12 16 Q2N2222 Rx 13 14 15K Ry 15 16 15K Ix1 13 17 1mA Ix2 14 17 1mA Iy1 15 17 1mA Iy2 16 17 1mA vx 9 10 PWL (0ms 0V 5ms 1V 15ms -1V 25ms 1V 35ms -1V 45ms 1V) vy 12 11 PWL (0ms 0V 5ms 1V 15ms -1V 25ms 1V 35ms -1V 45ms 1V) .tran 0.01ms 15ms 5ms 0.01ms .PROBE .END
100mV

80mV

60mV

40mV

20mV

0V

-20mV 5ms

6ms v(4)-v(3)

7ms

8ms

9ms

10ms Time

11ms

12ms

13ms

14ms

15ms

FREQUENCY DOUBLER
* Gilbert Frequency Doubler .Lib "nom.Lib" Vcc 1 0 15V Vee 0 17 15V Q1 2 2 5 Q2N2222 Q2 2 2 6 Q2N2222 Rcm 1 2 10K Rl1 1 3 11K Rl2 1 4 11K Q3 3 5 7 Q2N2222 Q4 4 6 7 Q2N2222 Q5 3 6 8 Q2N2222 Q6 4 5 8 Q2N2222 Q7 5 9 13 Q2N2222 Q8 6 10 14 Q2N2222 Q9 7 11 15 Q2N2222 Q10 8 12 16 Q2N2222 Rx 13 14 15K Ry 15 16 15K Ix1 13 17 1mA Ix2 14 17 1mA Iy1 15 17 1mA Iy2 16 17 1mA vx 9 10 sin(0 5 1K) vy 12 11 sin(0 5 1K) .tran 0.01ms 15ms 5ms 0.01ms .PROBE .END
5.0V

0V

-5.0V 5ms

6ms 7ms v(4)-v(3) v(9)-v(10)

8ms

9ms

10ms Time

11ms

12ms

13ms

14ms

15ms

Result:
1) From DC analysis, it has been found that the range of inputs that can be applied to Vx and Vy = +/- 15V. 2) The application of Gilbert Cell as a Tone Burst Generator, Squarer and Frequency Doubler has been verified.

Experiment no. 2
Aim: (i) Simulation of a MOS Amplifier circuit
(ii) MOS current mirror Using SPICE, determine the Norton equivalent of mirror circuit when Iin= 100uA.What is the minimum voltage that can appear at the O/P of this circuit while maintaining linear operation

Theory: (i)MOS AMPLIFIER

MOSFETs are the most commonly used type of FETs which are used extensively in amplification and switching applications. Circuit description: The MOS amplifier circuit being used for simulation is shown below. It consists of an NMOS transistor which is connected in common source mode, with the transistor being in saturation mode. This amplifier circuit is biased with a current source of 100uA.

FIGURE 2 MOS AMPLIFIER

8 Operation: In the saturation mode, VGS>Vth and VDS>(VGS-Vth), where the subscripts stand for drain, gate and source, respectively. The transistor is turned on, which allows current to flow between the drain and source through the channel. The drain voltage is higher than the gate voltage, and conduction takes place through the substrate. This state is also known as pinch-off since there is no channel region near the drain. The drain current becomes independent of drain voltage and is now controlled primarily by the gate-source voltage as ID= (nCox/2)*(W/L)*(1+VDS)*(VGS-Vth)2 where is the channel-length modulation parameter which reflects the current dependence on drain voltage due to the Early effect. W/L ratio depends on the body dimensions of the device. Using the above formula for ID we can obtain the MOSFET trans-conductance as gm=2ID/(VGS-Vth) The output impedence of the MOSFET gives an idea about how much the output current varies with the voltage applied to the mirror. It is given as rout = (1/ +VDS)/ID

(ii)MOS CURRENT MIRROR

A current mirror is a circuit that produces a current at its output node, which is identical to the current applied at the input node. The output current is constant whatever may be the loading in the circuit. The characteristics of a current mirror are: Gain: For an ideal current mirror, the gain is equal to unity. However, this may not be the case with practical mirrors where the gain may deviate from unity due to the passive components in the circuit. Output impedance: An ideal current mirror has infinite AC output impedance. However, because of channel-length modulation, the mirror has a finite output resistance given as rout = (1/ +VDS)/ID where is the channel modulation, VDS is he drain-source voltage and ID is the drain current. Input impedance: This is the impedance of the circuit at the input and must be ideally infinite since the gatesource junction of the input NMOS is open. Another important parameter for this circuit is the minimum voltage drop across the mirror necessary to make it work properly. This voltage is required to keep the output transistor of the mirror in active mode. Circuit description:

The MOS current mirror uses two NMOS transistors with their gates shorted. The drain and gate of the input transistors are also shorted. The circuit diagram is as follows-

FIGURE 3 MOS CURRENT MIRROR Operation: Transistors Q1 and Q2 are operating in the saturation or active mode. The drain current of a MOSFET is given by ID = f(VGS, VDG). In the case of transistor Q1, ID = IREF where IREF is the reference current. With VDG=0 for transistor Q1, the drain current in Q1 is ID = f (VGS, 0) = IREF. Thus IREF sets the value of VGS. Since the gates are shorted, the same VGS is applied to Q2. If Q2 also is biased with zero VDG and, Q1 and Q2 are matched, IOUT = f (VGS,0), thus setting IOUT = IREF.

10

MOS AMPLIFIER DC ANALYSIS

* MOS amplifier .Lib "nom.Lib" .model n1 nmos(kp=20u vto=1V lambda=0.01) .model p1 pmos(kp=10u vto=-1V lambda=0.01) vdd 1 0 DC 10V M1 3 4 0 0 n1 l=10u w=100u M2 3 2 1 1 p1 l=10u w=100u M3 2 2 1 1 p1 l=10u w=100u Iref 2 0 100uA Vin 4 0 DC 2V .DC LIN Vin 1.90 2.05 0.1m .PROBE .END

10V

8V

6V

4V

2V

0V 1.90V V(3)

1.92V

1.94V

1.96V

1.98V Vin

2.00V

2.02V

2.04V

2.06V

11

MOS AMPLIFIER AC ANALYSIS

* MOS amplifier AC analysis .Lib "nom.Lib" .model n1 nmos(kp=20u vto=1V lambda=0.01) .model p1 pmos(kp=10u vto=-1V lambda=0.01) vdd 1 0 DC 10V M1 3 4 0 0 n1 l=10u w=100u M2 3 2 1 1 p1 l=10u w=100u M3 2 2 1 1 p1 l=10u w=100u Iref 2 0 100uA Vdc 5 0 DC 2V Vin 4 5 AC 0.01V .ac DEC 20 1Hz 100MegHz .PROBE .END

1.6V

1.4V

1.2V

1.0V

0.8V

0.6V

0.4V 1.0Hz V(3)

10Hz

100Hz

1.0KHz

10KHz Frequency

100KHz

1.0MHz

10MHz

100MHz

12

MOS AMPLIFIER TRANSIENT ANALYSIS

* MOS amplifier Transient analysis .Lib "nom.Lib" .model n1 nmos(kp=20u vto=1V lambda=0.01) .model p1 pmos(kp=10u vto=-1V lambda=0.01) vdd 1 0 DC 10V M1 3 4 0 0 n1 l=10u w=100u M2 3 2 1 1 p1 l=10u w=100u M3 2 2 1 1 p1 l=10u w=100u Iref 2 0 100uA Vdc 5 0 DC 2V Vin 4 5 sin (0 0.01 1KHz) .tran 0.1ms 5ms 0ms 0.01ms .PROBE .END
2.01V

2.00V

1.99V V(4) 5.0V

4.0V

3.0V

SEL>> 2.0V 0s V(3)

0.5ms

1.0ms

1.5ms

2.0ms

2.5ms Time

3.0ms

3.5ms

4.0ms

4.5ms

5.0ms

13

MOS AMPLIFIER TRANSFER FUNCTION

* MOS amplifier Transfer function .Lib "nom.Lib" .model n1 nmos(kp=20u vto=1V lambda=0.01) .model p1 pmos(kp=10u vto=-1V lambda=0.01) vdd 1 0 DC 10V M1 3 4 0 0 n1 l=10u w=100u M2 3 2 1 1 p1 l=10u w=100u M3 2 2 1 1 p1 l=10u w=100u Iref 2 0 100uA Vdc 5 0 DC 2V Vin 4 5 DC .01V .tf v(3) Vin .PROBE .END

V(3)/Vin = -1.039E+02 INPUT RESISTANCE AT Vin = 1.000E+20 ohms OUTPUT RESISTANCE AT V(3) = 5.008E+05 ohms

14

CURRENT MIRROR DC ANALYSIS

* MOS mirror DC Analysis .Lib "nom.Lib" .model n1 nmos(kp=20u vto=1V lambda=0.01) vdd 1 0 DC 5V vss 0 4 DC 5V M1 2 2 4 4 n1 l=10u w=100u M2 3 2 4 4 n1 l=10u w=100u Iin 1 2 0A Vdc 5 3 DC 0V Rl 5 0 1K .DC LIN Iin 0 0.01 0.0001 .PROBE .END

10mA

8mA

6mA

4mA

2mA

0A 0A I(Vdc) 1mA I(Iin) 2mA 3mA 4mA 5mA Iin 6mA 7mA 8mA 9mA 10mA

15

CURRENT MIRROR AC ANALYSIS

* MOS mirror AC Analysis .Lib "nom.Lib" .model n1 nmos(kp=20u vto=1V lambda=0.01) vdd 1 0 DC 5V vss 0 4 DC 5V M1 2 2 4 4 n1 l=10u w=100u M2 3 2 4 4 n1 l=10u w=100u Iin 1 2 AC 0.001 I1 1 2 DC 0.001 Vdc 5 3 DC 0V Rl 5 0 1K .AC DEC 20 1Hz 10000tHz .PROBE .END

1.6mA

1.2mA

0.8mA

0.4mA 1.0Hz I(Vdc)

10KHz

100MHz Frequency

1.0THz

10e+15Hz

16

CURRENT MIRROR TRANSIENT ANALYSIS

* MOS mirror DC Analysis .Lib "nom.Lib" .model n1 nmos(kp=20u vto=1V lambda=0.01) vdd 1 0 DC 5V vss 0 4 DC 5V M1 2 2 4 4 n1 l=10u w=100u M2 3 2 4 4 n1 l=10u w=100u Iin 1 2 sin (0.001 0.001 1K) Vdc 5 3 DC 0V Rl 5 0 1K .tran 0.1ms 5ms 0ms 0.01ms .PROBE .END

2.0mA

1.5mA

1.0mA

0.5mA

0A 0s I(Vdc) Time 0.5ms 1.0ms 1.5ms 2.0ms 2.5ms 3.0ms 3.5ms 4.0ms 4.5ms 5.0ms

17

CURRENT MIRROR TRANSFER FUNCTION

* MOS mirror Transfer Function .Lib "nom.Lib" model n1 nmos(kp=20u vto=1V lambda=0.01) vdd 1 0 DC 5V vss 0 4 DC 5V M1 2 2 4 4 n1 l=10u w=100u M2 3 2 4 4 n1 l=10u w=100u Iin 1 2 DC 0.001 Vdc 5 3 DC 0V Rl 5 0 1K .tf I(Vdc) Iin .PROBE .END

I(Vdc)/Iin = 9.750E-01 INPUT RESISTANCE AT Iin = 1.527E+03 ohms OUTPUT RESISTANCE AT I(Vdc) = 1.051E+05 ohms

Result:
1) The operation of MOS amplifier biased with a current source MOS current mirror has been verified. 2) It has been observed that bandwidth of MOS circuits is ideally infinite.

18

Experiment no. 3
Aim: Simulation of the current follower using OMA (Inverting and Non Inverting)
(a) Inverting. (i) DC characteristics To find maximum Iin which can be applied while maintaining the linearity of Io (ii) Transient Response (.tran) (iii) Frequency Response and Bandwidth (.ac) (iv) Large signal transient response with large input current as square wave signal. Determine the slew rate. (v) Small signal analysis to find Rin, Rout and gain of CCCS (.tf). (vi) What modification is required in the circuit to bring Io=Iin (NonInverting) (b) Non Inverting. (i) DC characteristics To find maximum Iin which can be applied while maintaining the linearity of Io (ii) Transient Response (.tran) (iii) Frequency Response and Bandwidth (.ac) (iv) Large signal transient response with large input current as square wave signal. Determine the slew rate. (v) Small signal analysis to find Rin, Rout and gain of CCCS (.tf).

Theory:
The AD704 is a quad, low power bipolar op amp that has the low input bias current of a BiFET amplifier but which offers a significantly lower IB drift over temperature. AD704 achieves 75 V offset voltage and low noise characteristics of a precision bipolar input op amp.

19 OMA+ It has two output terminals namely the current output terminal (high impedance) and the voltage output terminal (low impedance). The same current I0 flows through the output terminals. Therefore, it is known as mirrored amplifier. I1 + I2 + Ip + I0 = In Where I1 is the current entering the non-inverting terminal of AD-704 I2 is the current entering the inverting terminal of AD-704 Ip is the current flowing through Vcc In is the current flowing through Vcc I0 is the output current. Since, I1 and I2 are negligible, it implies I0 = In - Ip Which means current at the output terminal is derived from power supply.I0 is ac current as the DC components cancel out. The output impedance of an OMA at the voltage output terminal is very low (ideally zero) and at the current output terminal is very high (ideally infinite). Advantages of current follower using OMA over OP-AMP 1. As compared to conventional technique which needs as many as two OP-AMPs and five matched resistors, only one OP-AMP and no resistors are employed.
2. Slew rate based effects are not as prominent as compared to traditional circuit.

Circuit Description

The circuit of figure 4 is an inverting current follower with I0 = -Iin. It may be noted that the voltage at the voltage output terminal of the op-amp is zero for any input current. Hence, the circuit doesnt suffer from finite slew rate effects. Similarly , the circuit shown in figure 5 is of non inverting types having two cross connected mirrors to make I0 = Iin. Cascode current mirrors are used in circuit of figure 4 and simple current mirrors are used in circuit of figure 5.

20

CIRCUIT DIAGRAM

FIGURE 4: INVERTING CURRENT FOLLOWER USING OMA

21

22 FIGURE 5: NON INVERTING CURRENT FOLLOWER USING OMA

INVERTING CURRENT FOLLOWER

DC ANALYSIS
* OMA DC Analysis .Lib "nom.Lib" .Lib "anlg_dev.lib" X 0 6 4 8 6 AD704/AD Vp 1 0 10V Vn 0 12 10V Q1 2 2 1 Q2N2907A Q2 3 2 1 Q2N2907A Q3 4 4 3 Q2N2907A Q4 5 4 2 Q2N2907A Q5 8 8 9 Q2N2222 Q6 5 8 11 Q2N2222 Q7 9 11 12 Q2N2222 Q8 11 11 12 Q2N2222 Iin 0 6 0A RL 5 0 1K .DC Lin Iin -12mA 15mA 10uA .PROBE .END

23
15mA

10mA

5mA

0A

-5mA

-10mA

-15mA -12mA -10mA I(RL) I(Iin)

-8mA

-6mA

-4mA

-2mA

0mA

2mA Iin

4mA

6mA

8mA

10mA

12mA

14mA

16mA

TRANSIENT ANALYSIS
* OMA Transient Analysis .Lib "nom.Lib" .Lib "anlg_dev.lib" X 0 6 4 8 6 AD704/AD Vp 1 0 10V Vn 0 12 10V Q1 2 2 1 Q2N2907A Q2 3 2 1 Q2N2907A Q3 4 4 3 Q2N2907A Q4 5 4 2 Q2N2907A Q5 8 8 9 Q2N2222 Q6 5 8 11 Q2N2222 Q7 9 11 12 Q2N2222 Q8 11 11 12 Q2N2222 Iin 0 6 sin(0 1m 1kHz) RL 5 0 1K .tran 0.1ms 2ms 0ms 0.01ms .PROBE .END

24
1.2mA

0.8mA

0.4mA

0.0mA

-0.4mA

-0.8mA

-1.2mA 0s I(RL) 0.2ms I(Iin) 0.4ms 0.6ms 0.8ms 1.0ms Time 1.2ms 1.4ms 1.6ms 1.8ms 2.0ms

AC ANALYSIS
* OMA AC Analysis .Lib "nom.Lib" .Lib "anlg_dev.lib" X 0 6 4 8 6 AD704/AD Vp 1 0 10V Vn 0 12 10V Q1 2 2 1 Q2N2907A Q2 3 2 1 Q2N2907A Q3 4 4 3 Q2N2907A Q4 5 4 2 Q2N2907A Q5 8 8 9 Q2N2222 Q6 5 8 11 Q2N2222 Q7 9 11 12 Q2N2222 Q8 11 11 12 Q2N2222 Iin 0 6 AC 1mA RL 5 0 1K .AC DEC 20 100Hz 1gHz .PROBE .END

25
1.2mA

1.0mA

0.8mA

0.6mA

0.4mA

0.2mA

0A 100Hz 300Hz I(Iin) I(RL)

1.0KHz

3.0KHz

10KHz

30KHz

100KHz

300KHz Frequency

1.0MHz

3.0MHz

10MHz

30MHz

100MHz

300MHz

1.0GHz

SLEW RATE ANALYSIS

* OMA Slew Rate Analysis .Lib "nom.Lib" .Lib "anlg_dev.lib" X 0 6 4 8 6 AD704/AD Vp 1 0 10V Vn 0 12 10V Q1 2 2 1 Q2N2907A Q2 3 2 1 Q2N2907A Q3 4 4 3 Q2N2907A Q4 5 4 2 Q2N2907A Q5 8 8 9 Q2N2222 Q6 5 8 11 Q2N2222 Q7 9 11 12 Q2N2222 Q8 11 11 12 Q2N2222 Iin 0 6 PULSE(-10m 10m 1f 1f 1f 0.5ms 1ms) RL 5 0 1K .tran .1ms 1ms 0ms 100ns .PROBE .END

26
10mA

5mA

0A

-5mA

-10mA 0s I(RL) 40us I(Iin) 80us 120us 160us 200us 240us Time 280us 320us 360us 400us 440us 480us 520us

TRANSFER FUNCTION
* OMA Transfer Function .Lib "nom.Lib" .Lib "anlg_dev.lib" X 0 6 4 8 6 AD704/AD Vp 1 0 10V Vn 0 12 10V Q1 2 2 1 Q2N2907A Q2 3 2 1 Q2N2907A Q3 4 4 3 Q2N2907A Q4 5 4 2 Q2N2907A Q5 8 8 9 Q2N2222 Q6 5 8 11 Q2N2222 Q7 9 11 12 Q2N2222 Q8 11 11 12 Q2N2222 Iin 0 6 DC 1mA Vd 5 13 0 RL 13 0 1K .tf I(Vd) Iin .PROBE .END

27 I(Vd)/Iin = -1.001E+00 INPUT RESISTANCE AT Iin = 2.649E-04 OUTPUT RESISTANCE AT I (Vd) = 4.692E+06

NON-INVERTING CURRENT FOLLOWER

DC ANALYSIS
* OMA DC Analysis .Lib "nom.Lib" .Lib "anlg_dev.lib" X 0 6 2 3 6 AD704/AD Vp 1 0 10V Vn 0 4 10V Q1 2 2 1 Q2N2907A Q2 5 2 1 Q2N2907A Q5 7 7 1 Q2N2907A Q6 8 7 1 Q2N2907A Q3 3 3 4 Q2N2222 Q4 7 3 4 Q2N2222 Q7 5 5 4 Q2N2222 Q8 8 5 4 Q2N2222 Iin 0 6 0A RL 8 0 1K .DC Lin Iin -12mA 15mA 10uA .PROBE .END

28

15mA

10mA

5mA

0A

-5mA

-10mA

-15mA -12mA -10mA I(RL) I(Iin)

-8mA

-6mA

-4mA

-2mA

0mA

2mA Iin

4mA

6mA

8mA

10mA

12mA

14mA

16mA

TRANSIENT ANALYSIS
* OMA Transient Analysis .Lib "nom.Lib" .Lib "anlg_dev.lib" X 0 6 2 3 6 AD704/AD Vp 1 0 10V Vn 0 4 10V Q1 2 2 1 Q2N2907A Q2 5 2 1 Q2N2907A Q5 7 7 1 Q2N2907A Q6 8 7 1 Q2N2907A Q3 3 3 4 Q2N2222 Q4 7 3 4 Q2N2222 Q7 5 5 4 Q2N2222 Q8 8 5 4 Q2N2222 Iin 0 6 sin(0 1m 1KHz) RL 8 0 1K .tran 0.1ms 2ms 0ms 0.01ms .PROBE .END

29

1.5mA

1.0mA

0.5mA

0A

-0.5mA

-1.0mA

-1.5mA 0s I(RL) 0.2ms I(Iin) 0.4ms 0.6ms 0.8ms 1.0ms Time 1.2ms 1.4ms 1.6ms 1.8ms 2.0ms

AC ANALYSIS
* OMA Transient Analysis .Lib "nom.Lib" .Lib "anlg_dev.lib" X 0 6 2 3 6 AD704/AD Vp 1 0 10V Vn 0 4 10V Q1 2 2 1 Q2N2907A Q2 5 2 1 Q2N2907A Q5 7 7 1 Q2N2907A Q6 8 7 1 Q2N2907A Q3 3 3 4 Q2N2222 Q4 7 3 4 Q2N2222 Q7 5 5 4 Q2N2222 Q8 8 5 4 Q2N2222 Iin 0 6 AC 1mA RL 8 0 1K .AC DEC 20 100Hz 1gHz .PROBE .END

30

1.5mA

1.0mA

0.5mA

0A 100Hz 300Hz I(Iin) I(RL)

1.0KHz

3.0KHz

10KHz

30KHz

100KHz

300KHz Frequency

1.0MHz

3.0MHz

10MHz

30MHz

100MHz

300MHz

1.0GHz

SLEW RATE ANALYSIS

* OMA Slew Rate Analysis .Lib "nom.Lib" .Lib "anlg_dev.lib" X 0 6 2 3 6 AD704/AD Vp 1 0 10V Vn 0 4 10V Q1 2 2 1 Q2N2907A Q2 5 2 1 Q2N2907A Q5 7 7 1 Q2N2907A Q6 8 7 1 Q2N2907A Q3 3 3 4 Q2N2222 Q4 7 3 4 Q2N2222 Q7 5 5 4 Q2N2222 Q8 8 5 4 Q2N2222 Iin 0 6 PULSE(-10m 10m 1f 1f 1f 0.5ms 1ms) RL 8 0 1K .tran .1ms 1ms 0ms 100ns .PROBE .END

31

10mA

5mA

0A

-5mA

-10mA 0s I(RL) 0.1ms I(Iin) 0.2ms 0.3ms 0.4ms 0.5ms Time 0.6ms 0.7ms 0.8ms 0.9ms 1.0ms

TRANSFER FUNCTION
* OMA Transfer Function .Lib "nom.Lib" .Lib "anlg_dev.lib" X 0 6 2 3 6 AD704/AD Vp 1 0 10V Vn 0 4 10V Q1 2 2 1 Q2N2907A Q2 5 2 1 Q2N2907A Q5 7 7 1 Q2N2907A Q6 8 7 1 Q2N2907A Q3 3 3 4 Q2N2222 Q4 7 3 4 Q2N2222 Q7 5 5 4 Q2N2222 Q8 8 5 4 Q2N2222 Iin 0 6 DC 1mA Vd 8 13 0 RL 13 0 1K .tf I(Vd) Iin .PROBE .END

32 I (Vd)/Iin = 1.283E+00 INPUT RESISTANCE AT Iin = 2.576E-04 OUTPUT RESISTANCE AT I (Vd) = 5.065E+04

Result:
The analysis of inverting and non inverting current followers using OMAs has been carried out.

Experiment no. 4
Aim: SPICE simulation and verification of the operation of trans-linear squarer
(i) To setup the circuit using Q2N2222 from library file and perform DC analysis (transfer characteristics) to determine the following: a) Maximum range of Iin for which circuit functions as a squarer b) Value of I for which the Iin range is maximum (ii) To perform transient analysis with sinusoidal input Iin (Vin) and verify the operation by checking the output waveform (iii) To find out if there any limitation on the values of RL

Theory:
Trans-linear circuits are synthesized using circuit elements like BJT and MOS in which the current shares an exponential relationship with voltage. The trans-conductance in these circuits is a linear function of DC bias current. The advantages of trans-linear circuit are No resistors are required which results in saving of area. Performance is independent of temperature.

33

The circuit diagram of trans-linear squarer (the output current is square of the input current) is shown on the following page. Applying the trans-linear loop through transistors Q4, Q1, Q5 and Q6 VBE4+VBE1=VBE5+VBE6 And thus IC4.IC1=IC5.IC6 Now, IC1=IC3=I+iin (neglecting base currents) Similarly, IC4=IC2=2I-(I+iin)=I-iin And, IC5=I, IC6=I-io Hence, (I+iin).(I-iin)=I.(I-io) which implies I2-iin2=I2-I.io or, io=iin2/I This is the expression for a trans-linear squarer.

CIRCUIT DIAGRAM

34

FIGURE 6: TRANSLINEAR SQUARER

Maximum range of Iin

*Maximum Range of Iin by varying RL

35 .Lib "nom.Lib" V1 1 0 15V V2 0 6 15V I1 1 2 200uA I2 1 8 100uA I3 7 0 100uA I4 5 6 100uA Q1 2 2 3 Q2N2222 Q2 2 2 4 Q2N2222 Q3 3 4 5 Q2N2222 Q4 4 3 0 Q2N2222 Q5 1 2 7 Q2N2222 Q6 8 7 0 Q2N2222 Iin 0 5 0 RL 8 0 1K .DC Lin Iin -120uA 120uA 1uA .PROBE .END

200uA

100uA

0A

-100uA

-200uA -120uA I(Iin)

-80uA I(RL)

-40uA

0uA Iin

40uA

80uA

120uA

Maximum range if Iin = -100uA to 100uA Value of I for which Iinrange is maximum
*Maximum range of I

36 .Lib "nom.Lib" V1 1 0 15V V2 0 6 15V I1 1 2 0.6mA I2 1 8 0.3mA I3 7 0 0.3mA I4 5 6 0.3mA Q1 2 2 3 Q2N2222 Q2 2 2 4 Q2N2222 Q3 3 4 5 Q2N2222 Q4 4 3 0 Q2N2222 Q5 1 2 7 Q2N2222 Q6 8 7 0 Q2N2222 Iin 0 5 0 RL 8 0 1K .DC Lin Iin -.31mA 0.31mA 1uA .PROBE .END

400uA

200uA

0A

-200uA

-400uA -400uA I(Iin)

-300uA I(RL)

-200uA

-100uA

0A Iin

100uA

200uA

300uA

400uA

Desired value of I = 0.3mA

TRANSIENT ANALYSIS
*Transient

37 .Lib "nom.Lib" V1 1 0 15V V2 0 6 15V I1 1 2 200uA I2 1 8 100uA I3 7 0 100uA I4 5 6 100uA Q1 2 2 3 Q2N2222 Q2 2 2 4 Q2N2222 Q3 3 4 5 Q2N2222 Q4 4 3 0 Q2N2222 Q5 1 2 7 Q2N2222 Q6 8 7 0 Q2N2222 Iin 0 5 sin(0 50uA 1KHz) RL 8 0 1K .tran 0.1ms 5ms 0ms 0.01ms .PROBE .END

50uA

0A

-50uA 0s I(Iin) 0.5ms I(RL) 1.0ms 1.5ms 2.0ms 2.5ms Time 3.0ms 3.5ms 4.0ms 4.5ms 5.0ms

Result: The analysis of translinear squarer has been carried out.

Experiment no. 5

38

Aim: Simulate a differential amplifier biased with current mirror. Do the following.
(a) (b) (c) (d) Transfer characteristics(offset calculations) Frequency Response Transient analysis Calculate ADM, ACM and CMRR

Theory:
A differential signal is defined as one that is measured between two nodes that have equal and opposite signal excursions around a fixed potential. In the strict sense, the two nodes must also exhibit equal impedances to that potential. It offers many advantages of differential signaling such as high rejection of supply noise, higher output swings, suppression of non ideal effects etc. The differential circuits occupy twice as much area as single ended alternatives but the numerous advantages of differential operation by far outweigh the possible increase in area. Common Mode Rejection Ratio(CMRR) is defined as the ratio of differential mode gain to the common mode gain and is thus calculated followed by the differential and common mode analysis. A high value of CMRR is often desirable.

Circuit Description and Operation:

The circuit diagram is shown on the following page. It consists of six MOS transistors namely M1, M2, M3, M4, M5, M6 and a current source Iref which is connected to the drain of M6. The positive power supply is given to the source of M5 and M6 and the negative power supply to the source of M3 and M4 as shown. The given MOS transistors operate in saturation region ( VDS > VGS VTH ). The transistors M5 and M6(PMOS) are identical and form a current mirror. Thus the current Iref is duplicated to the drain of M5 (current mirror) which further divides in M1 and M2. Similarly, the transistors(NMOS) are identical and form a current mirror and same current which flows through the drain of M3 and M4 (=Iref/2) which implies that the current flowing in M1 and M3 and M2 and M4 are equal. The differential input is applied at the gate of the transistors M1 and M2(PMOS) . The differential output is taken across the drain of the transistors M1 and M2. For differential mode analysis Vcm applied is zero and for common mode analysis an appropriate value of Vcm is applied or the two input terminals are joined and given a common input to get the output at V(7) or V(8) ( which can also be joined as they are equal ).

CIRCUIT DIAGRAM

39

FIGURE 7:DIFFERENTIAL AMPLIFIER BIASED WITH CURRENT MIRROR

TRANSFER CHARACTERISTICS(OFFSET CALCULATIONS)

40

* MOS differential amplifier .Lib "nom.Lib" .model NM NMOS(kp=20u vto=1V lambda=0.04) .model PM PMOS(kp=10u vto=-1V lambda=0.04) vdd 1 0 DC 5V vss 0 3 DC 5V M1 7 5 4 1 PM l=8u w=120u M2 8 6 4 1 PM l=8u w=120u M3 7 7 3 3 NM l=10u w=50u M4 8 7 3 3 NM l=10u w=50u M5 4 2 1 1 PM l=10u w=150u M6 2 2 1 1 PM l=10u w=150u Iref 2 3 25u Vd 9 10 0V Vdc 10 0 25mV Rd 9 0 1k EV1 5 11 9 0 0.5 EV2 11 6 9 0 0.5 Vcm 11 0 0V .DC LIN Vd -100m 100m 0.1m .PROBE .END
2.0V

0V

-2.0V

-4.0V

-6.0V -100mV -80mV V(7) - V(8)

-60mV

-40mV

-20mV

0V Vd

2 0m V

40mV

60mV

80mV

100mV

Vdc = 25mV to avoid offset

AC ANALYSIS

41

* MOS differential amplifier .Lib "nom.Lib" .model NM NMOS(kp=20u vto=1V lambda=0.04) .model PM PMOS(kp=10u vto=-1V lambda=0.04) vdd 1 0 DC 5V vss 0 3 DC 5V M1 7 5 4 1 PM l=8u w=120u M2 8 6 4 1 PM l=8u w=120u M3 7 7 3 3 NM l=10u w=50u M4 8 7 3 3 NM l=10u w=50u M5 4 2 1 1 PM l=10u w=150u M6 2 2 1 1 PM l=10u w=150u Iref 2 3 25u Vd 9 10 AC 10mV Vdc 10 0 DC 25mV Rd 9 0 1k EV1 5 11 9 0 0.5 EV2 11 6 9 0 0.5 Vcm 11 0 0V .AC DEC 20 1Hz 1tHz .PROBE .END
1.2V

1.0V

0.8V

0.6V

0.4V

0.2V 1.0Hz 10Hz (v(7)-v(8))

100Hz

1.0KHz

10KHz

100KHz

1.0MHz Frequency

10MHz

100MHz

1.0GHz

10GHz

100GHz 1.0THz

TRANSIENT ANALYSIS

42

* MOS differential amplifier .Lib "nom.Lib" .model NM NMOS(kp=20u vto=1V lambda=0.04) .model PM PMOS(kp=10u vto=-1V lambda=0.04) vdd 1 0 DC 5V vss 0 3 DC 5V M1 7 5 4 1 PM l=8u w=120u M2 8 6 4 1 PM l=8u w=120u M3 7 7 3 3 NM l=10u w=50u M4 8 7 3 3 NM l=10u w=50u M5 4 2 1 1 PM l=10u w=150u M6 2 2 1 1 PM l=10u w=150u Iref 2 3 25u Vd 9 10 sin(0 10m 1Khz) Vdc 10 0 DC 25mV Rd 9 0 1k EV1 5 11 9 0 0.5 EV2 11 6 9 0 0.5 Vcm 11 0 0V .tran 0.01ms 5ms 0ms 0.01ms .PROBE .END
-1.0V

-1.5V

-2.0V

SEL>> -2.5V v(7)-v(8) 10mV

0V

-10mV 0s 0.5ms v(9)-v(10)

1.0ms

1.5ms

2.0ms

2.5ms Time

3.0ms

3.5ms

4.0ms

4.5ms

5.0ms

DIFFERENTIAL GAIN

43

* MOS differential amplifier .Lib "nom.Lib" .model NM NMOS(kp=20u vto=1V lambda=0.04) .model PM PMOS(kp=10u vto=-1V lambda=0.04) vdd 1 0 DC 5V vss 0 3 DC 5V M1 7 5 4 1 PM l=8u w=120u M2 8 6 4 1 PM l=8u w=120u M3 7 7 3 3 NM l=10u w=50u M4 8 7 3 3 NM l=10u w=50u M5 4 2 1 1 PM l=10u w=150u M6 2 2 1 1 PM l=10u w=150u Iref 2 3 25u Vd 9 10 DC 10mv Vdc 10 0 DC 25mv Rd 9 0 1k EV1 5 11 9 0 0.5 EV2 11 6 9 0 0.5 Vcm 11 0 0V .tf V(7,8) Vd .PROBE .END

OUTPUT ADM = V(7,8)/Vd = -6.967E+01 Input Resistance at Vd = 1.000E+03 Output Resistance at V(7,8) = 2.050E+06

COMMON MODE GAIN

44

* MOS differential amplifier .Lib "nom.Lib" .model NM NMOS(kp=20u vto=1V lambda=0.04) .model PM PMOS(kp=10u vto=-1V lambda=0.04) vdd 1 0 DC 5V vss 0 3 DC 5V M1 7 5 4 1 PM l=8u w=120u M2 8 6 4 1 PM l=8u w=120u M3 7 7 3 3 NM l=10u w=50u M4 8 7 3 3 NM l=10u w=50u M5 4 2 1 1 PM l=10u w=150u M6 2 2 1 1 PM l=10u w=150u Iref 2 3 25u Vd 9 10 DC 0mv Vdc 10 0 DC 25mv Rd 9 0 1k EV1 5 11 9 0 0.5 EV2 11 6 9 0 0.5 Vcm 11 0 10mv .tf V(7,8) Vcm .PROBE .END OUTPUT ACM = V(7,8)/Vcm = -8.991E-02 Input Resistance at Vcm = 1.000E+20 Output Resistance at V(7,8) = 2.065E+06 CALCULATION OF CMRR CMRR = ADM/ACM = (-6.967E+01)/( -8.991E-02) = 774.886

Result:
The analysis of differential amplifier biased with current mirror has been carried out.

Experiment no. 6

45

Aim: To simulate the linear voltage controlled resistance in CMOS

Conventional MOS resistor Linearised grounded resistor Linearised floating resistor

Theory:
Current expressions in MOS circuits Triode region [Vds < (Vgs-Vth)]Id = Cox(W/L)[(Vgs-Vth)Vds-Vds2 /2] = Cox(W/L)(Vgs-Vth)Vds, for Vds << 2(Vgs-Vth) Saturation region [Vds > (Vgs-Vth)] Id = Cox(W/2L)[Vgs-Vth]2[1+Vds]

(i) CONVENTIONAL MOS RESISTOR

Circuit Description

FIGURE 8 CONVENTIONAL MOS RESISTOR

The MOS is operating in the triode. The current is given by (taking =0) Id = Cox(W/L)(Vgs-Vth)Vds Hence, Rd = Vds/Id = 1/[Cox(W/L)(Vgs-Vth)]

(ii) LINEARISED GROUNDED RESISTOR

46

Circuit Description

FIGURE 9 LINEARISED GROUNDED RESISTOR The MOS M1 is operating in the triode region. The current is given by Id = Cox(W/L)(Vgs-Vth)Vds With Vgs=Vc and Rd = Vin/Iin, we obtain Rd= 1/[Cox(W/L)1(Vc-Vth)]

(iii) LINEARISED FLOATING RESISTOR

Circuit Description The MOSFETs M3, M4, M5 and M6 operate in saturation Now, Id5 = Id6 = (Cox/2)(W/L)5[Vc-Vth]2, (assuming =0) ------------(i)

Similarly, Id3 = (Cox/2)(W/L)3[V1-Vx-Vth]2 where Vx = V(4) ------------(ii) Id4 = (Cox/2)(W/L)4[V2-Vy-Vth]2 where Vy = V(5) ------------(iii) Also, Id3 = Id5 and Id6 = Id4 ------------(iv)

47

FIGURE 10 LINEARISED FLOATING RESISTOR On solving (i),(ii),(iii)&(iv), we obtain Vy - V2 = - ((W/L)6/(W/L)4)(Vc-Vth) Vth Vx- V1= - ((W/L)5/(W/L)3)(Vc-Vth) Vth The MOSFETs M1 and M2 are PMOS. The drain of M1 is connected to V2 and source to V1, thus for saturation of M1 (Vx+|Vth|) >V2 i.e. (V2-Vx)<|Vth|. But V1-Vx>Vth because M3 is conducting and hence M1 operating in triode region. Similarly, drain of M2 is connected to V1 and source to V2 and it is operating in triode region. Hence, Id1 = -Cox(W/L)1[(Vx-V1+Vth)(V2-V1)-(V2-V1)2 /2] and Id2 = -Cox(W/L)2[(Vy-V2+Vth)(V1-V2)-(V2-V1)2 /2] Now Iin1 = -Iin2 = Id2-Id1 If (W/L)1=(W/L)2 =(W/L) Then, Iin1 = -Cox(W/L)[(Vy-V2+Vth)(V1-V2)+(Vx-V1+Vth)(V1-V2)] Iin1 = - Cox(W/L)(V1-V2)[Vy-V2+Vth+Vx-V1+Vth] Using Iin1 = (V1-V2)/R, we obtain R = 1/[ Cox(W/L) (((W/L)6/(W/L)4)+((W/L)5/(W/L)3))(Vc-Vth)]

48

CONVENTIONAL MOS RESISTOR: DC Analysis

* MOS Conventional resistor .Lib "nom.Lib" .model NM NMOS(kp=20u vto=1V lambda=0.01) .model PM PMOS(kp=10u vto=-1V lambda=0.01) vd 3 2 DC 0V vds 3 0 DC 0V vgs 1 0 DC 0V M1 2 1 0 0 NM l=10u w=150u .DC LIN vds -0.6V 3V 1m LIN vgs 0V 10V 2 .PROBE .END
8.0mA

4.0mA

0A

-4.0mA -1.0V I(vd)

-0.5V

0V

0.5V

1.0V vds

1.5V

2.0V

2.5V

3.0V

OUTPUT Output: R=0.42K at Vgs=10V

49

LINEARISED GROUNDED RESISTOR: DC Analysis

* Grounded linearised resistor .Lib "nom.Lib" .model NM NMOS(kp=20u vto=1V lambda=0.01) .model PM PMOS(kp=10u vto=-1V lambda=0.01) vdd 7 0 DC 15V vss 0 5 DC 15V vc 3 0 DC 0V vin 2 0 DC 0V M1 2 3 0 0 NM l=6u w=36u M2 4 2 5 5 NM l=6u w=36u M3 6 0 5 5 NM l=6u w=36u M4 6 6 7 7 PM l=10u w=150u M5 4 6 7 7 PM l=10u w=150u .DC LIN vin -0.6 1.5V 1m LIN vc 0V 10V 2 .PROBE .END OUTPUT
2.0mA

1.0mA

0A

-1.0mA -0.8V ID(M1)

-0.4V

0V

0.4V vin

0.8V

1.2V

1.6V

2.0V

OUTPUT Rd=0.97K at Vc=10V

50

LINEARISED FLOATING RESISTOR

* Floating linearised resistor .lib "NOM.lib" .model NM nmos(Kp=20U Vto=1V lambda=0.01) .model PM pmos(Kp=10U Vto=-1V lambda=0.01) M1 1 4 3 2 PM l=10U w=36U M2 1 5 3 2 PM l=6U w=36U M3 2 1 4 4 NM l=6U w=36U M4 2 3 5 5 NM l=10U w=150U M5 4 6 7 7 NM l=10U w=150U M6 5 6 7 7 NM l=10U w=150U Vdd 2 0 DC 15V Vss 0 7 DC 15V V1 1 0 DC 0V V2 3 0 DC 0V Vc 6 7 DC 1V .DC LIN V1 -3V 3V 0.001 Vc 0 10 2 .PROBE .END OUTPUT
4.0mA

2.0mA

0A

-2.0mA

-4.0mA -3.0V I(V2)

-2.0V

-1.0V

0V V(1)

1.0V

2.0V

3.0V

OUTPUT R=1.12K at Vc=10V RESULT The three different types of resistors were simulated and the resistances were calculated using the graphs obtained.

51

Experiment no. 7
Aim: Simulate Linearized Four Quadrant MOS Multiplier
(i) To perform DC Analysis of the circuit with Vx varying from -2V to 2V and Vy varying from -3.5 to -2.5V (ii) To perform Transfer Function Analysis

Theory:
A Four Quadrant MOS Multiplier accepts both positive and negative swings of INPUT Voltages (VX and VY) over a certain defined range. The circuit shown here realizes a similar feature. The circuit consists of four n channel MOSFETS connected in the form of two differential pairs.Q1 Q3 form one differential pair and Q2 Q4 form the other. The MOSFETs are operating in the saturation region. VY is applied to the source of Q1 Q3 and inverted VY with an offset of 3V is applied to source of Q2 Q4. The offset has been included to allow the circuit to operate as a four quadrant multiplier. The other input V X has been applied to gate of Q1 Q2 and inverted VX to gate of Q3 Q4. The output is taken as the difference of voltages V (2) and V (3) and is proportional to VX and VY. The output of this circuit is given by I2 I3 = 4KVX (-6 2VY) VO = - (I2 I3) R = 4KVX (6 + 2VY) x 103 The DC analysis and transfer function analysis have been performed.

52

CIRCUIT DIAGRAM

FIGURE 11 MOS MULTIPLIER

53

DC ANALYSIS
* simulate linearized four quadrant MOS amplifier .lib "nom.lib" .model NM NMOS (KP=20u VTO=1 LAMBDA=0.01) M1 2 4 6 6 NM L=36U W=6U M2 3 4 7 7 NM L=36U W=6U M3 3 5 6 6 NM L=36U W=6U M4 2 5 7 7 NM L=36U W=6U R1 1 2 1K R2 1 3 1K R3 6 8 100K R4 8 7 100K R5 4 10 100K R6 10 5 100K VDD 1 0 DC 7V VP 11 0 DC 7V VN 0 12 DC 7V VS 0 9 DC 3V VX 4 0 DC 0V VY 6 0 DC 0V X1 9 8 11 12 7 UA741 X2 0 10 11 12 5 UA741 .DC LIN VX -2 2 .25 VY -3.5 -2.5 .25 .PROBE .END
15mV

10mV

5mV

0V

-5mV

-10mV

-15mV -2.0V -1.5V V(2)-V(3)

-1.0V

-0.5V

0V VX

0.5V

1.0V

1.5V

2.0V

54

Transfer Function Analysis

* simulate linearized four quadrant MOS amplifier .lib "nom.lib" .model NM NMOS (KP=20u VTO=1 LAMBDA=0.01) M1 2 4 6 6 NM L=36U W=6U M2 3 4 7 7 NM L=36U W=6U M3 3 5 6 6 NM L=36U W=6U M4 2 5 7 7 NM L=36U W=6U R1 1 2 1K R2 1 3 1K R3 6 8 100K R4 8 7 100K R5 4 10 100K R6 10 5 100K VDD 1 0 DC 7V VP 11 0 DC 7V VN 0 12 DC 7V VS 0 9 DC 3V VX 4 0 AC .1V VY 6 0 AC .2V X1 9 8 11 12 7 UA741 X2 0 10 11 12 5 UA741 .tf V (2, 3) VY *.tf V (2, 3) VX .PROBE .END

V (2, 3)/VY = -3.145E-05 INPUT RESISTANCE AT VY = 1.000E+05 OUTPUT RESISTANCE AT V (2, 3) = 1.999E+03

V (2, 3)/VX = 3.760E-02 INPUT RESISTANCE AT VX = 1.000E+05 OUTPUT RESISTANCE AT V (2, 3) = 1.999E+03

Result: The DC Analysis and Transfer Function Analysis of the linearized four quadrant
MOS multiplier has been carried out.

55

Experiment no. 8
Aim: Simulate the unbuffered CMOS op-amp to enumerate the following:
(1) Open-loop transfer characteristics(DC Analysis) (2)Gain-bandwidth product (3)CMRR (4) Slew-Rate (5)Power dissipation

Theory:
The circuit consists of 8 MOSFETs (both NMOS and PMOS). The circuit contains three stages Input stage This stage consists of the differential pair formed by the transistors M1, M2, M3 and M4. The gate voltages applied to M1 and M2 are Ev1 and Ev2 respectively, which are dependent voltage sources and their values depend upon voltage across resistance Rd. The MOSFETs M6 and M8 form a PMOS current mirror, which is used to provide the bias current for the differential pair. This current is same as Iref. Intermediate stage The intermediate stage consists of MOSFETs M5 and M7. M5 is working in common source configuration and M7 is acting as an active load for the circuit. Output stage There is no separate output stage and the final output is taken as voltage at the drain of MOSFET M5.

56

CIRCUIT DIAGRAM

FIGURE 12 CMOS OPERATIONAL AMPLIFIER

57

OPEN-LOOP TRANSFER CHARACTERISTICS (DC ANALYSIS)

.lib "nom.lib" .model NM NMOS(Level=3 Gamma=0 Delta=0 Eta=0 Theta=0 Kappa=0.2 Vmax=0 Xj=0 + Tox=100n Uo=600 Phi=.6 Rs=.1207 Kp=21.35u W=1.1 L=2u Vto=3.143 + Rd=64.68m Rds=600K Cbd=1.273n Pb=.8 Mj=.5 Fc=.5 Cgso=729.7p + Cgdo=310.4p Rg=5.839 Is=44.21f N=1 Tt=370n) .model PM PMOS(Level=3 Gamma=0 Delta=0 Eta=0 Theta=0 Kappa=0.2 Vmax=0 Xj=0 + Tox=100n Uo=300 Phi=.6 Rs=.1181 Kp=10.32u W=.93 L=2u Vto=-3.252 + Rd=.5495 Rds=888.9MEG Cbd=891.4p Pb=.8 Mj=.5 Fc=.5 Cgso=3.804n + Cgdo=90.23p Rg=.9239 Is=2.072p N=4 Tt=815n) M1 7 5 3 1 PM L=8U W=120U M2 8 6 3 1 PM L=8U W=120U M3 7 7 4 4 NM L=10U W=50U M4 8 7 4 4 NM L=10U W=50U M5 10 8 4 4 NM L=10U W=100U M6 3 2 1 1 PM L=10U W=150U M7 10 2 1 1 PM L=10U W=120U M8 2 2 1 1 PM L=10U W=150U IREF 2 4 DC 25U VDD 1 0 DC 5V VSS 0 4 DC 5V VCM 101 0 DC 0V EV1 101 5 100 0 0.5 EV2 6 101 100 0 0.5 RD 100 0 1K C1 9 10 10PF IC=0 R1 8 9 10K VD 100 102 DC 0V VDC 102 0 DC 0mV .DC LIN VD -4.0M 5.0M 0.1M .PROBE .END OUTPUT
5.0V

0V

-5.0V -4.0mV V(10)

-3.0mV

-2.0mV

-1.0mV

0V VD

1.0mV

2.0mV

3.0mV

4.0mV

5.0mV

GAIN BANDWIDTH PRODUCT

58 .lib "nom.lib" .model NM NMOS(Level=3 Gamma=0 Delta=0 Eta=0 Theta=0 Kappa=0.2 Vmax=0 Xj=0 + Tox=100n Uo=600 Phi=.6 Rs=.1207 Kp=21.35u W=1.1 L=2u Vto=3.143 + Rd=64.68m Rds=600K Cbd=1.273n Pb=.8 Mj=.5 Fc=.5 Cgso=729.7p + Cgdo=310.4p Rg=5.839 Is=44.21f N=1 Tt=370n) .model PM PMOS(Level=3 Gamma=0 Delta=0 Eta=0 Theta=0 Kappa=0.2 Vmax=0 Xj=0 + Tox=100n Uo=300 Phi=.6 Rs=.1181 Kp=10.32u W=.93 L=2u Vto=-3.252 + Rd=.5495 Rds=888.9MEG Cbd=891.4p Pb=.8 Mj=.5 Fc=.5 Cgso=3.804n + Cgdo=90.23p Rg=.9239 Is=2.072p N=4 Tt=815n) M1 7 5 3 1 PM L=8U W=120U M2 8 6 3 1 PM L=8U W=120U M3 7 7 4 4 NM L=10U W=50U M4 8 7 4 4 NM L=10U W=50U M5 10 8 4 4 NM L=10U W=100U M6 3 2 1 1 PM L=10U W=150U M7 10 2 1 1 PM L=10U W=120U M8 2 2 1 1 PM L=10U W=150U IREF 2 4 DC 25U VDD 1 0 DC 5V VSS 0 4 DC 5V VCM 101 0 DC 0V EV1 101 5 100 0 0.5 EV2 6 101 100 0 0.5 RD 100 0 1K C1 9 10 10PF IC=0 R1 8 9 10K VD 100 102 AC 0.5mV VDC 102 0 DC 1.1mV .AC DEC 20 1Hz 100KHz .PROBE .END OUTPUT
2 . 0K

1 . 5K

1 . 0K

0 . 5K

Gain = 1.6968k Bandwidth = 142 Hz GainBandwidth Product = 2.4E+05

1 0 Hz 3 0H z 1 00 Hz 30 0H z F re q ue nc y 1 . 0K Hz 3 .0 KH z 1 0K Hz 3 0K Hz 10 0K Hz

0 1. 0H z 3. 0H z v (1 0) / (V (1 00 ) -V (1 02 ))

CMRR
.lib

"nom.lib"

59 .model NM NMOS(Level=3 Gamma=0 Delta=0 Eta=0 Theta=0 Kappa=0.2 Vmax=0 Xj=0 + Tox=100n Uo=600 Phi=.6 Rs=.1207 Kp=21.35u W=1.1 L=2u Vto=3.143 + Rd=64.68m Rds=600K Cbd=1.273n Pb=.8 Mj=.5 Fc=.5 Cgso=729.7p + Cgdo=310.4p Rg=5.839 Is=44.21f N=1 Tt=370n) .model PM PMOS(Level=3 Gamma=0 Delta=0 Eta=0 Theta=0 Kappa=0.2 Vmax=0 Xj=0 + Tox=100n Uo=300 Phi=.6 Rs=.1181 Kp=10.32u W=.93 L=2u Vto=-3.252 + Rd=.5495 Rds=888.9MEG Cbd=891.4p Pb=.8 Mj=.5 Fc=.5 Cgso=3.804n + Cgdo=90.23p Rg=.9239 Is=2.072p N=4 Tt=815n) M1 7 5 3 1 PM L=8U W=120U M2 8 6 3 1 PM L=8U W=120U M3 7 7 4 4 NM L=10U W=50U M4 8 7 4 4 NM L=10U W=50U M5 10 8 4 4 NM L=10U W=100U M6 3 2 1 1 PM L=10U W=150U M7 10 2 1 1 PM L=10U W=120U M8 2 2 1 1 PM L=10U W=150U IREF 2 4 DC 25U VDD 1 0 DC 5V VSS 0 4 DC 5V VCM 101 0 AC 0.5mV EV1 101 5 100 0 0.5 EV2 6 101 100 0 0.5 RD 100 0 1K C1 9 10 10PF IC=0 R1 8 9 10K VD 100 102 AC 0mV VDC 102 0 DC 1.1mV .AC DEC 20 1Hz 1000KHz .PROBE .END OUTPUT
6 0 0m 5 0 0m

4 0 0m

3 0 0m

2 0 0m

1 0 0m

0 1 0z . H

30 z . H v1 )v 1 1 ( 0/ (0 )

1 H 0z

3H 0 z

1 0z 0 H

3 0 z 0H

1 0H . Kz F eun y rqe c

3 0 H .K z

1K z 0 H

3K z 0H

10 H 0 Kz

3 0H 0K z

10H .M z

Differential Mode Gain = ADM = V(10)/VD = 1.464E+03 Common Mode Gain = ACM = V(10)/VCM = 4.639E-04 Common Mode Rejection Ratio = CMRR = ADM /ACM = 3.16E+06

SLEW RATE

.lib "nom.lib" .model NM NMOS(Level=3 Gamma=0 Delta=0 Eta=0 Theta=0 Kappa=0.2 Vmax=0 Xj=0 + Tox=100n Uo=600 Phi=.6 Rs=.1207 Kp=21.35u W=1.1 L=2u Vto=3.143

60 + Rd=64.68m Rds=600K Cbd=1.273n Pb=.8 Mj=.5 Fc=.5 Cgso=729.7p + Cgdo=310.4p Rg=5.839 Is=44.21f N=1 Tt=370n) .model PM PMOS(Level=3 Gamma=0 Delta=0 Eta=0 Theta=0 Kappa=0.2 Vmax=0 Xj=0 + Tox=100n Uo=300 Phi=.6 Rs=.1181 Kp=10.32u W=.93 L=2u Vto=-3.252 + Rd=.5495 Rds=888.9MEG Cbd=891.4p Pb=.8 Mj=.5 Fc=.5 Cgso=3.804n + Cgdo=90.23p Rg=.9239 Is=2.072p N=4 Tt=815n) M1 7 5 3 1 PM L=8U W=120U M2 8 6 3 1 PM L=8U W=120U M3 7 7 4 4 NM L=10U W=50U M4 8 7 4 4 NM L=10U W=50U M5 10 8 4 4 NM L=10U W=100U M6 3 2 1 1 PM L=10U W=150U M7 10 2 1 1 PM L=10U W=120U M8 2 2 1 1 PM L=10U W=150U IREF 2 4 DC 25U VDD 1 0 DC 5V VSS 0 4 DC 5V VCM 101 0 DC 0mV EV1 101 5 100 0 0.5 EV2 6 101 100 0 0.5 RD 100 0 1K C1 9 10 10pF IC=0 R1 8 9 10K VD 100 102 PULSE(-2 2 1ns 1ns 1ns 1ms 2ms) VDC 102 0 DC 1.1mV .tran .01ms 5ms 0ms 0.01ms .PROBE .END OUTPUT
5.0V

0V

-5.0V 0s V(10) 0.5ms V(100)-V(102) 1.0ms 1.5ms 2.0ms 2.5ms Time 3.0ms 3.5ms 4.0ms 4.5ms 5.0ms

t1 = 1.15 ms , V1 = 4.68 V t2 = 1.25 ms , V2 = -5.0 V

Slew-rate = (V2 V1)/(t2 t1) = -9.68E04

POWER DISSIPIATION
.lib "nom.lib" .model NM NMOS(Level=3 Gamma=0 Delta=0 Eta=0 Theta=0 Kappa=0.2 Vmax=0 Xj=0 + Tox=100n Uo=600 Phi=.6 Rs=.1207 Kp=21.35u W=1.1 L=2u Vto=3.143 + Rd=64.68m Rds=600K Cbd=1.273n Pb=.8 Mj=.5 Fc=.5 Cgso=729.7p + Cgdo=310.4p Rg=5.839 Is=44.21f N=1 Tt=370n)

61 .model PM PMOS(Level=3 Gamma=0 Delta=0 Eta=0 Theta=0 Kappa=0.2 Vmax=0 Xj=0 + Tox=100n Uo=300 Phi=.6 Rs=.1181 Kp=10.32u W=.93 L=2u Vto=-3.252 + Rd=.5495 Rds=888.9MEG Cbd=891.4p Pb=.8 Mj=.5 Fc=.5 Cgso=3.804n + Cgdo=90.23p Rg=.9239 Is=2.072p N=4 Tt=815n) M1 7 5 3 1 PM L=8U W=120U M2 8 6 3 1 PM L=8U W=120U M3 7 7 4 4 NM L=10U W=50U M4 8 7 4 4 NM L=10U W=50U M5 10 8 4 4 NM L=10U W=100U M6 3 2 1 1 PM L=10U W=150U M7 10 2 1 1 PM L=10U W=120U M8 2 2 1 1 PM L=10U W=150U IREF 2 4 DC 25u VDD 1 0 DC 5V VSS 0 4 DC 5V VCM 101 0 AC 0mV EV1 101 5 100 0 0.5 EV2 6 101 100 0 0.5 RD 100 0 1K C1 9 10 10PF R1 8 9 10K VD 100 102 AC 0.5mV VDC 102 0 DC 1.1mV .tf V(10) VD .PROBE .END OUTPUT Total Power Dissipation = 7.00E-04 Watts

Result:
The analysis of unbuffered CMOS operational amplifier has been carried out.