Pipeline execution: IF: ID: EX: MA: WB: 1 : 2: 3: 4: 5: instruction fetch Instruction decode Instruction execution Memory access

to target address Write execution result to registers IF ID EX MA WB IF ID EX IF ID EX IF ID EX IF ID EX

Registers General registers: There are 16 general registers, R0 to R15. General registers R0 to R7 are banked registers which are switched by a processor mode change. System registers: Access to these registers does not depend on the processor mode. 1) Multiply-and-accumulate register high, MACH (32 bits, initial value undefined) 2) Multiply-and-accumulate register low, MACL (32 bits, initial value undefined) 3) Procedure register, PR (32 bits, initial value undefined) The return address is stored when a subroutine call using a BSR, BSRF or JSR instruction. PR is referenced by the subroutine return instruction (RTS) 4) Program Counter, PC (32 bits, initial value = H'A000 0000) Floating-point status/control register, FPSCR (32 bits, initial value = H'0004 0001) FR: Floating-point register bank SZ: Transfer size mode 0=32 bit, 1=32 bit pair PR: Precision mode, 0=single-precision 1=double-precision Rounding modes Control registers - 7 registers 1) Status register, SR (32 bits, privilege protection, initial value = 0111 0000 0000 0000 0000 00XX 1111 00XX (X: Undefined)) 31 30 29 28 27 16 15 14 10 9 8 7 6 5 4 3 2 1 0 MD RB BL FD M Q IMASK S T MD: Processor mode MD = 0: User mode, restricted mode MD = 1: Privileged mode RB: Specifies general register bank. (set to 1 by a reset, exception, or interrupt) RB = 0: R0_BANK0R7_BANK0 are accessed as general registers R0R7. (R0_BANK1 R7_BANK1 can be accessed using LDC/STC R0_BANKR7_BANK instructions.) RB = 1: R0_BANK1R7_BANK1 are accessed as general registers R0R7. (R0_BANK0 R7_BANK0 can be accessed using LDC/STC R0_BANKR7_BANK instructions.) BL: Exception/interrupt block bit (set to 1 by a reset, exception, or interrupt) BL = 1: Interrupt requests are masked. If a general exception other than a user break occurs while BL = 1, the processor switches to the reset state.

FD: FPU disable bit (cleared to 0 by a reset) FD = 1: An FPU instruction causes a general FPU disable exception, and if the FPU instruction is in a delay slot, a slot FPU disable exception is generated. M, Q: Used by the DIV0S, DIV0U, and DIV1 instructions. IMASK: Interrupt mask level External interrupts of a same level or a lower level than IMASK are masked. S: Specifies a saturation operation for a MAC instruction. T: True/false condition or carry/borrow bit. T bit in status register show result of compare 2) Saved status register, SSR (32 bits, privilege protection, initial value undefined): The current contents of SR are saved to SSR in the event of an exception or interrupt. 3) Saved program counter, SPC (32 bits, privilege protection, initial value undefined): The address of an instruction at which an interrupt or exception occurs is saved to SPC. 4) Global base register, GBR (32 bits, initial value undefined): GBR is referenced as the base address in a GBR-referencing MOV instruction. 5) Vector base register, VBR (32 bits, privilege protection, initial value = H'0000 0000): VBR is referenced as the branch destination base address in the event of an exception or interrupt. 6) Saved general register 15, SGR (32 bits, privilege protection, initial value undefined): The contents of R15 are saved to SGR in the event of an exception or interrupt. 7) Debug base register, DBR (32 bits, privilege protection, initial value undefined): When the user break debug function is enabled (BRCR.UBDE = 1), DBR is referenced as the user break handler branch destination address instead of VBR. Floating-point registers: There are thirty-two floating-point registers, FR0 FR15 and XF0XF15. FR0FR15 and XF0XF15 can be assigned to either of two banks (FPR0_BANK0 FPR15_BANK0 or FPR0_BANK1FPR15_BANK1). Memory mapped registers ??? control registers are double-mapped a) 0x1F00 0000-0x1FFF FFFF Accessed in address translation mode using TLB b) 0xFF00 0000-0xFFFF FFFF Access in user mode will cause error, can be access in address translation mode. Processor states 1) Reset state power-on reset and manual reset 2) program execution state 3) Exception-handling state

4) Power-down state Processor modes Determined by MD bit in status register (SR) Execution environment a) load/store instructions b) delayed branch, the instruction following the branch is executed before the branch destination instruction. Delayed branch, destination address calculation 1: IF ID EX 2: IF ID EX ------ > 3 cycles 3: IF ID EX 1: 2: 3: IF ID EX --- > 2 cycles IF ID EX IF ID EX

Addressing modes (not all) Register direct Rn effective address is register Rn Register indirect @Rn effective address is register Rn contents Register indirect @Rn+ effective address is register Rn contents and a constant is added according to operand with post increment Register indirect @-Rn effective address is Rn contents and is decremented with pre-decrement

Stack Terms: 1) Function 2) Leaf function 3) A frame is the stack space pushed for a function invocation. 4) Top of stack is the lowest used address on the stack 5) Bottom of stack is the highest used address in the stack 6) Stack Unwind 7) Position Independent Code (PIC) is code that can be loaded and will successfully execute anywhere in a programs virtual address space, i.e. the code contains no absolute code or data addresses.

Frame layout: 1) Register save area: used to save and restore the callee save registers. 2) Local variable: register spills and local variables (known at compile time) 3) Dynamic variable area: alloca 4) Argument area: needed to pass an argument list

Caller SAVE (Scratch): value is not preserved across function calls. Callee SAVE: value is guaranteed to be preserved across calls. Callee either will not modify or will save before modify and restore it. Registers used in ABI document R0-R3 Return value, caller save R2 Large struct return address, caller save R4-R7 Parameter passing, caller save R8-R13 Callee save R12 Global context pointer, GP, callee save R13 Callee save R14 Frame pointer, FP, callee save R15 Stack pointer, SP, callee save FR0-FR3 Return value, caller save FR4-FR11 Parameter passing, caller save FR12-FR15 Callee save

On entry (PROLOG) Create a stack frame. This is performed by decreasing SP. No accesses beyond SP are permitted. The decrement of SP may be performed by a single instruction, or by a number of instructions. Create a working register set. A function always has access to a set of scratch (caller-save) registers. If it needs further registers, it must save and use callee-save registers. Save the return address. Establish frame pointer if needed, by copying SP to the frame pointer register. Establish a global context pointer, GP, if needed, as an offset from the PC. On Exit (EPILOG) On exit from a function, the following tasks are performed: Restore the return address. Delete the stack frame by restoring SP. Again, the increment of SP may be performed by a number of instructions but after each of these increments, SP must be correctly aligned. Restore the callee save registers that were saved in the prolog code. Perform a return to the caller using the return address.