Architecture of 8085 Microprocessor

MRs. P.Janani, M.Sc., M.Phil

DMI - St. Eugene Unviersity, Lusaka, Zambia

8085A is a
40 pins device 8 bit general purpose microprocessor requires +5V single phase supply 3 MHz single phase clock

MRs. P.Janani, M.Sc., M.Phil

DMI - St. Eugene Unviersity, Lusaka, Zambia

The 8085 uses three separate busses to perform its operations

The address bus. The data bus. The control bus.

MRs. P.Janani, M.Sc., M.Phil

DMI - St. Eugene Unviersity, Lusaka, Zambia 4

 16 bits wide (A0 A1A15) Therefore, the 8085 can access locations with numbers from 0 to 65,536. Or, the 8085 can access a total of 64K addresses. Unidirectional. Information flows out of the microprocessor and into the memory or peripherals. When the 8085 wants to access a peripheral or a memory location, it places the 16-bit address on the address bus and then sends the appropriate control signals.
MRs. P.Janani, M.Sc., M.Phil DMI - St. Eugene Unviersity, Lusaka, Zambia 5

 8 bits wide (D0 D1D7) Bi-directional. Information flows both ways between the microprocessor and memory or I/O. The 8085 uses the data bus to transfer the binary information. Since the data bus has 8-bits only, then the 8085 can manipulate data 8 bits at-a-time only.

MRs. P.Janani, M.Sc., M.Phil

DMI - St. Eugene Unviersity, Lusaka, Zambia 6

 There is no real control bus. Instead, the control bus is made up of a number of single bit control signals.

MRs. P.Janani, M.Sc., M.Phil

DMI - St. Eugene Unviersity, Lusaka, Zambia 7

The internal architecture of 8085 includes

1.Arithmetic

Logic Unit 2.Timing and Control Unit 3.Instruction Register and Decoder 4.Register Array 5.Interrupt Control 6.Serial I/O Control

MRs. P.Janani, M.Sc., M.Phil

DMI - St. Eugene Unviersity, Lusaka, Zambia

Arithmetic Logic Unit

numerical

and logic operation such as add, subtract, AND, OR stores result of operation in Accumulator

MRs. P.Janani, M.Sc., M.Phil

DMI - St. Eugene Unviersity, Lusaka, Zambia

Timing and Control Unit

synchronizes

all the microprocessor

operations generates necessary signals for communication between peripherals and microprocessor

MRs. P.Janani, M.Sc., M.Phil

DMI - St. Eugene Unviersity, Lusaka, Zambia

Instruction Register/Decoder
temporarily

stores the current instruction

of a program. Latest instruction sent here from memory prior to execution Decoder then takes instruction and decodes or interprets the instruction

MRs. P.Janani, M.Sc., M.Phil

DMI - St. Eugene Unviersity, Lusaka, Zambia

Register Array
six

registers- B, C, D, E, H, L two 16-bit registers: the stack pointer and the program counter

MRs. P.Janani, M.Sc., M.Phil

DMI - St. Eugene Unviersity, Lusaka, Zambia

Accumulator
8-bit

register that is a part of arithmetic/logic unit (ALU) used to store 8-bit data and to perform arithmetic and logical operations result stored in the accumulator

MRs. P.Janani, M.Sc., M.Phil

DMI - St. Eugene Unviersity, Lusaka, Zambia

Flags

The

ALU includes five flip-flops Used to set or reset after the operation in the accumulator Zero if the accumulator content is zero this bit will set. Carry if the 8th bit of accumulator will generate a carry, this bit will set. Parity if accumulator has odd number of 1s it is odd parity, the parity flag will reset, if it has even number of 1s it is even parity, this flag will set. Auxillary Carry if the 4th bit of accumulator will generate a carry, this flag will set. Sign if accumulator generates a positive or negative value, this flag will set.
MRs. P.Janani, M.Sc., M.Phil DMI - St. Eugene Unviersity, Lusaka, Zambia

Stack Pointer (SP)

A

16-bit register It points to a memory location in R/W memory, called the stack The beginning of the stack is defined by loading 16-bit address in the stack pointer.

MRs. P.Janani, M.Sc., M.Phil

DMI - St. Eugene Unviersity, Lusaka, Zambia

Program Counter (PC)

16 bit register
Points

the memory address from which the next byte is to be fetched. When a byte (machine code) is being fetched, the program counter is incremented by one to point to the next memory location.

MRs. P.Janani, M.Sc., M.Phil

DMI - St. Eugene Unviersity, Lusaka, Zambia

Interrupt Control
8085

has five interrupt signals used to interrupt a program execution. The signals are TRAP, RST 7.5, RST 6.5, Input signals RST 5.5, INTR
INTA

signals.

is related to the 8085 interrupt (output)

DMI - St. Eugene Unviersity, Lusaka, Zambia

MRs. P.Janani, M.Sc., M.Phil

Serial I/O Ports

The

8085 has two signals to implement the serial transmission: SID (Serial Input Data) and SOD (Serial Output Data). Data transfer is controlled through the instructions: SIM and RIM.

MRs. P.Janani, M.Sc., M.Phil

DMI - St. Eugene Unviersity, Lusaka, Zambia

Pin Configuration

MRs. P.Janani, M.Sc., M.Phil

DMI - St. Eugene Unviersity, Lusaka, Zambia

Pin Configuration
The signals of the 8085 can be classified into seven groups according to their functions. I.Power supply and frequency signals II.Data bus and address bus III.Control bus (signals) IV.Interrupt signals V.Serial I/O signals VI.DMA signals VII.Reset signals

MRs. P.Janani, M.Sc., M.Phil

DMI - St. Eugene Unviersity, Lusaka, Zambia

Pin Configuration
I.Power supply and frequency signals 1. X1, X2 (Input) Crystal or R/C network connections to set the internal clock generator X1 can also be an external clock input instead of a crystal. The input frequency is divided by 2 to give the internal operating frequency. 2. CLK (Output) This signal is used as a system clock for other devices. Its frequency is half the oscillator frequency. 3. Vcc It requires a single +5 volt supply. 4. Vss Ground Reference.
MRs. P.Janani, M.Sc., M.Phil DMI - St. Eugene Unviersity, Lusaka, Zambia

Pin Configuration
I.Data bus and address bus 5. AD0 AD7 (Output 3 State)
The 8 bit data bus (D0 D7) is multiplexed with the lower half (A0 A7) of the 16 bit address bus. During first part of the machine cycle (T1), lower 8 bits of memory address bus. During first part of the machine cycle (T1), lower 8 bits of memory address or I/O address appear on the bus. During remaining part of the machine cycle (T2 and T3) these lines are used as a bi-directional data bus.

6. A8 A15 (Input / Output 3state) The upper half of the 16 bit address appears on the address lines A8 A15. These lines are exclusively used for the most significant 8 bits of the 16 bit address lines.

Pin Configuration
III. Control bus (signals)
7. ALE (Output) Address Latch Enable It occurs during the first clock cycle of a machine state and enables the address to get latched into the on chip latch of peripherals. The falling edge of ALE is set to guarantee setup and hold times for the address information.ALE can also be used to strobe the status information. ALE is never 3stated.

8. (Output 3state) READ

It indicates the selected memory or 1/0 device is to be read and that the Data Bus is available for the data transfer.

9. (Output 3state) WRITE

It indicates the data on the Data Bus is to be written into the selected memory or 1/0 location. Data is set up at the trailing edge of WR. Tristated during Hold and Halt modes.
MRs. P.Janani, M.Sc., M.Phil DMI - St. Eugene Unviersity, Lusaka, Zambia

Pin Configuration
10. IO/ (Output) indicates whether the Read/Write operation is with the memory or I/O device. 11. SO, S1 (Output) Data Bus Status. indicates the type of machine cycle in progress and the status of the bus cycle: S1 S0 O O HALT 0 1 WRITE 1 0 READ 1 1 FETCH S1 can be used as an advanced R/W status. 12. READY (Input) used by the microprocessor to sense whether a peripheral is ready or not for data transfer. If not, the processor waits. It is thus used to synchronize slower peripherals to the microprocessor.
MRs. P.Janani, M.Sc., M.Phil DMI - St. Eugene Unviersity, Lusaka, Zambia

Pin Configuration
IV. Interrupt signals
The 8085 has 5 hardware interrupt signals: RST 5.5, RST 6.5, RST 7.5, TRAP and INTA. The microprocessor recognizes interrupt requests on these lines at the end of the current instruction execution. TRAP Highest Priority RST 7.5 RST 6.5 RST 5.5 INTR Lowest Priority The signal is used to indicate that the processor has acknowledged an INTR interrupt.

V. Serial I/O signals

13. SID (Input) - Serial input data input signal is used to accept serial data, bit by bit from the external device. 14. SOD (output) - Serial output data. output signal which enables the transmission of serial data bit by bit to the external device.

MRs. P.Janani, M.Sc., M.Phil

DMI - St. Eugene Unviersity, Lusaka, Zambia

Pin Configuration
VI. DMA signals
indicates that another master is requesting for the use of address bus, data bus and control bus.

15. HOLD (Input)

->

16.

(Output) active signal is used to acknowledge HOLD request.

MRs. P.Janani, M.Sc., M.Phil

DMI - St. Eugene Unviersity, Lusaka, Zambia

Pin Configuration
VII. Reset signals 17. RESET IN (Input)
i.Reset sets the Program Counter to zero ii.Resets the Interrupt Enable and HLDA flipflops. iii.Affects the contents of processors internal registers randomly. iv.On reset, the PC sets to 0000H which causes the 8085 to execute the first instruction from address 0000h. for proper reset operation rest signal must be held low for atleast 3 clock cycles. The power on reset circuit can be used to ensure execution of first instruction from address 0000H.

18. RESET OUT (Output)

This active high signal indicates that processor is being reset. This signal is synchronized to the processor clock and it can be used to reset other devices connected in the system.

MRs. P.Janani, M.Sc., M.Phil

DMI - St. Eugene Unviersity, Lusaka, Zambia

Pin Configuration

MRs. P.Janani, M.Sc., M.Phil

DMI - St. Eugene Unviersity, Lusaka, Zambia

MRs. P.Janani, M.Sc., M.Phil