Synplify Pro

FPGA Synthesis with the Synplify Pro Tool
Winter - 2000
Introduction
Objectives
Review the course objectives Review the course schedule How to get help
Introduction
Course Objectives
This course introduces the new user to the Synplify Pro FPGA synthesis product. The topics covered will include:
Design flow and Synthesis Concepts Project Management SCOPE Windows - Graphical Constraints Entry Synthesis Optimization and User Control
Synplify Pro Tool Compiler optimizations Synplify Pro Tool Compiler directives Synplify Pro Tool Mapper optimizations Timing constraints and Attributes to control synthesis
Debugging with HDL Analyst RTL Debugging and Analysis Environment
Introduction
Course Schedule
Design Flow and Synthesis Concepts Project Management Lab 1 SCOPE Editor Lunch Synthesis Optimizations in the Compiler Lab 2 Synthesis Optimizations in the Mapper Debugging with the HDL Analyst Module Labs 3 & 4
Introduction
4
Getting Help
Online Help
Select Help->Help, or [F1] function key from Synplify Pro Software
Synplify Pro Tool User Guide

Pdf file found in <Synplify Pro Install Dir>/docs
Synplify Pro Tool Reference Guide

Pdf file found in <Synplify Pro S/W Install Dir>/docs
Synplicity Support
Synplify Online Support[SOS] and Synplify Newsgroup
http://www.synplicity.com/support/logon_news/log_news.html news://news.synplicity.com/Synplicity.Synplify
Synplify First Level Support

Can be accessed from S.O.S
Send email to support@synplicity.com Call the Technical Support Hotline at (408) 215-6000
Introduction
5
Design Flow and Synthesis Concepts

Design Flow and Synthesis Concepts Project Management Lab 1 SCOPE Lunch Compiler Lab 2 Mapper Debugging with the HDL Analyst feature Labs 3 & 4
6
HDL Design Methodology

Functional Spec RTL Coding Verilog/VHDL RTL Simulation
script files
constraints
Synthesis
timing analysis mapped netlist
FPGA Vendor
simulate mapped design
Place & Route
timing verification
post layout simulation
chip Design Flow and Synthesis Concepts

7
Why HDL Design Entry?

Technology independence
Versus vendor dependent schematic/HDL entry Common language for synthesis and simulation Better suited to design re-use
Higher level of design abstraction

Designer can focus on chip design goals Leave implementation to tools Improves time to market for complex designs
Synthesis in the Synplify Pro Tool

Verilog/VHDL
Compile
User Constraint File[.sdc] Technology independent RTL View netlist[.srs]
Technology Map
[Based on Device options] Technology view netlist[.srm] Post-synthesis simulation netlist [.vhm/.vm]
Forward annotated timing constraints[.acf,.ncf,.lp etc.] Technology-specific netlist[.edf, .xnf, .vqm, .edn etc.]
9
Input Files to the Synplify Pro Tool

RTL level source files
Verilog, VHDL or both
Constraint file
Define timing constraints such as clocks, input/output delays, timing exceptions User attributes to control synthesis
10
Synthesis Process in the Synplify Pro Tool

Compilation
Syntax checking of HDL Code Conversion of HDL code into technology-independent netlist B.E.S.TTM[Behavior Extraction Synthesis Technology] Algorithms
Extraction of high level structures
RAM ROM Arithmetic and Logical Operators, such as adders, multipliers, comparators FSMs
Finite State Machine(FSM) extraction and optimizations Resource sharing of arithmetic operators RTL optimizations
11
Synthesis Process in the Synplify Pro Tool

Mapping
Technology-independent netlist generated by compiler and constraints file taken as input Mapping to technology-specific structures, such as lookup tables[LUTs] and registers Behavior extraction and mapping to resources available in the specified technology [ B.E.S.T.] Timing driven synthesis and optimization
Logic Replication Buffering Structuring Critical Path re-synthesis
12
Output Files From the Synplify Pro Tool

Technology-specific netlist
EDIF for Virtex , vqm for Apex
Constraints file for the P & R tool

Forward annotated constraints and attributes specified in the Synplify Pro tool
.ncf for Virtex, .acf for Flex10k, .tcl for Apex, .lp for Orca families
Mapped VHDL or Verilog netlist for post synthesis simulation

.vm for Verilog, .vhm for VHDL
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Project Management
Project Management
14
Project Management Overview

How to invoke the Synplify Pro tool
PC Unix
How to specify project options in the the Synplify Pro s/w interface
Create a new project Add source files Select Target technology and specify device options Specify timing constraints through the SCOPE editor Select compiler and mapper options Specify result file options
Viewing Results
Log File Log Watch Window Tcl Window
Project Management
15
Invoking the Synplify Pro Tool

Invoking the Synplify Pro tool interactively
On a PC, select Programs->Synplicity->Synplify Profrom the Start button. On a UNIX workstation, type this at the command line:
synplify_pro
Invoking the Synplify Pro s/w in batch mode

On PC or UNIX, type
synplify_pro -batch <project_file_name>.prj
Project Management
16
Lab 1[Invoke the Synplify Pro Tool]

Design Flow and Synthesis Concepts Project Management Lab 1 The SCOPE Editor Lunch Synthesis Optimizations in the Compiler Lab 2 Synthesis Optimizations in the Mapper Debugging with the HDL Analyst Module Labs 3 & 4
Lab 1
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The Synplify Pro Tool Project File

Contains data needed for a design
Source files Device Options Constraint files Multiple Implementations Compiler and Mapper Options Result file options Global Frequency
Text file with Tcl commands
Project Management
18
A Sample Run -- Creating a New Project
Synplify Pro UI
Creates a new project Helpful for new users Project Management

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A Sample Run -- Adding Source Files
Filter on file types Project Management

20
A Sample Run -- Adding Source File

HDL Source files can be created using any editor The Synplify Pro tools editor has the following features
Full-Featured editor
Is context-sensitive
Keywords are blue, comments are green,etc
Allows block commenting of HDL lines of code Allows selecting and editing of columns Other standard features such as Find, Replace, Line numbers etc.
Integrated with the synthesis environment

Allows cross-probing with the log file Allows synthesis check and syntax check on the HDL source files Allows navigating through errors in a source file
Project Management
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A Sample Run -- HDL Source File

Comments are green
Keywords are blue

Project Management
Strings are red

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A Sample Run -- Select Device Options
Device mapping options
Project Management
23
A Sample Run Create a New Constraints File
Project Management
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A Sample Run Apply Basic Timing Constraints
Clock constraint of 100 MHz specified in the Clocks tab
Default Input and Output delay of 5 ns specified in Inputs/Outputs tab
Project Management
25
Selecting Constraint File & Output Files

Compiler and Mapper Options Implementation name
Global frequency
Project Management
Simulation files and constraint files
Result format
26
A Sample Run -- Run
The famous Run button!
Project Management
27
Lab 1[Run a Simple Project]

Design Flow and Synthesis Concepts Project Management Lab 1 The SCOPE Editor Lunch Synthesis Optimizations in the Compiler Lab 2 Synthesis Optimizations in the Mapper Debugging with the HDL Analyst Module Labs 3 & 4
Lab 1
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Viewing Results Log File

Log file
Detailed text file with the steps taken during synthesis
Project Management
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Viewing Results -- Log File

Several sections
Compiler report Mapper report Timing report Resource usage report
Warnings and errors can be cross-probed to the HDL code

Errors indicated by @E Warnings indicated by @W Notes indicated by @N
Project Management
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Log File -- Compiler Report

Compiler Report
System and Software Information
Compiler build date Date and time of run
Project Information
Source files compiled Top level module
Design Information
HDL syntax check & synthesis check Warnings on unused inputs Removal of redundant logic Latch inference warnings FSM extraction Inferred RAMs/ROMs Black box instantiations
Project Management
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Log File -- Mapper Report

Mapper Report
System and Software Information
Mapper build date Target Technology
SCOPE Editor Information

Constraint files read Attributes assigned
Design Information
Flattening( automatic dissolve )of the design Extraction of counters FSM Implementation Explicit and inferred clock nets Buffered nets Replication of logic Optimization of flip flops
Project Management
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Log File -- Timing Report

Timing report
Required and estimated clock frequencies for each of the clocks in the designs Required and estimated arrival times for all the inputs in the top level design Required and estimated arrival times of all the outputs in the top level design Bi-directional ports appear as input and output Critical paths
Project Management
33
Log File Resource Usage Report

Resource Usage Report
Number of inputs/outputs Number of lookup tables Number of registers that are packed in I/Os and number that are not Other technology-specific resources such as
RAMs and ROMs Carry chains Counters
Part and package used Percentage utilization
Project Management
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Lab 1[View Results in the Log File]

Lab 1
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Viewing Results Log Watch Window

Displays different parameters of the log file in tabular form
Requested Clock Frequency and Period Estimated Clock Frequency and Period Device selected
Can be configured to show results for multiple implementations Select View -> Log Watch Window from Synplify Pro Tool
Project Management
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Viewing Results -- Log Watch Window
Log parameters
Project Management
Implementation name
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Lab 1[View Results in Log Watch Window]

Lab 1
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Viewing Results -- Tcl Window

Displays project management commands Displays status of synthesis run Displays errors and warnings from a run and allows cross-probing to HDL source file Select View -> Tcl Window
Project Management
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TCL Window in the Synplify Pro Tool
TCL window
Project Management
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Viewing Results HDL Analyst Module

HDL Analyst Module
Graphical representation of the design
RTL view
Technology independent schematic of the design
Technology view
Technology dependent schematic of the design View of the critical path with timing and slack information
Project Management
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Viewing Results -- RTL View
Click here to bring up RTL View
Hierarchical list of ports, nets,components

Project Management
Hierarchical schematic View
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Cross-probing Between RTL View and HDL
RTL View
HDL Source Code Cross probing
Project Management
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Viewing Results -- Technology View
Click here to bring up Technology View Technology specific components
Technology specific schematic
Project Management
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Cross-probing Between Technology View and HDL
Technology View
HDL Source Code
Project Management
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Viewing Results -- Critical Path in Technology View
View Critical Path
Filter Critical Path
Technology View
Project Management
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Lab 1[Completion]
Lab 1
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SCOPE Editor
The SCOPE Editor
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Synthesis Constraints OPtimization Environment [SCOPE] Editor

Graphical, spread-sheet format to enter and manage timing constraints and attributes Has the capability of initializing clocks, inputs and outputs Has auto-fill capability in order to help in filling the constraints and attributes Filters out objects based on the constraint or attribute applied Filters attributes and constraints based on the object selected
The SCOPE Editor
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SCOPE Editor
Creating a new constraints file
The SCOPE Editor
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Objects & Auto Fill-in capability

Objects filled in automatically Allowed Values
Tab selected
The SCOPE Editor
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SCOPE Editor- The Clocks tab
Clocks in the design filled in automatically in the Clock column Value specified in MHz or ns Duty cycle also specified Enabled tab used to select /deselect constraints
The SCOPE Editor
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SCOPE Editor - The Inputs/Outputs tab
Inputs and Outputs of the design automatically filled in the Port column Value specified in ns Enabled column used to select or deselect constraints Comment column
The SCOPE Editor
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SCOPE Editor - The Multi-cycle Paths tab
Specify Multi-cycle paths in the design Types of Multi-cycle paths include -from, -to and through Applied on registers[-from, -to] or nets[-through] Value specified in cycles Enabled column used to select or deselect constraints Comment column
The SCOPE Editor
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SCOPE Editor - The Attributes tab

Attributes pull-down Menu
Objects pull-down Menu
Selecting an object filters the Attributes pull-down menu to allowable attributes only Selecting an attribute filters the Objects pull-down menu to allowable objects only Value column lists allowed values for an attribute Enabled column used to select or deselect attributes Comment column
The SCOPE Editor
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More about the SCOPE Editor

Synplify Pro tool allows dragging and dropping of objects from HDL Analyst Module to SCOPE editor SCOPE editor also uses specific abbreviation in order to distinguish same names for different objects
v: module or view n: net p : port i: instance b: bit slice
The SCOPE Editor
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Synthesis Optimizations in the Compiler

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Compiler Overview
B.E.S.T.[Behavior Extraction Synthesis Technology] Algorithms Supported Verilog and VHDL constructs in the Synplify Pro tools Recommended coding styles
Flip-flops RAM ROM FSM
Compiler Options and Directives

FSM Compiler Resource Sharing
Synthesis issues
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What is B.E.S.T[Behavior Extraction Synthesis Technology] Algorithms

B.E.S.T. algorithms in Synplify Pro tool has the following components:
Conservation of abstraction Integrated module generation and mapping Automatic hierarchy optimization
Benefits of B.E.S.T. algorithms

Infers high level structures such as RAMs, ROMs, operators, FSMs etc. and keeps them abstract for as long in the synthesis process as possible. This allows for the use of technology specific resources to implement these structures. Linear Compile times
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Conservation of Abstraction
High-level structure is preserved throughout optimization and mapping to get best results
Design Abstraction Behavior RTL Gates
Language Compilation Logic Optimization Technology Mapping
Synplify Pro Tool start Others
S Y N T H E S I S
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Supported Verilog Constructs

Supported Verilog HDL language constructs
Synplify Pro Tool supports a synthesizable subset of Verilog95 (IEEE 1364). All operators
(+, -, *, /, %, <, >, <=, >=, ==, !=, ===, !==, &&, ||, !, ~, &, ~&, |, ~|, ^~, ~^, ^, <<, >>, ?:, {}, {{}}) [Note: / and % supported for compile-time constants and constant powers of 2]
Behavioral statements
if-else-if, case, casex, casez, for, repeat, while, forever, begin, end, fork, join
Procedural assignments
=, <= [Note: '<=' cannot be mixed with '=' for the same register]
Compiler directives
`define, ìfdef, èlse, èndif, ìnclude
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Supported Verilog Constructs

Supported Verilog HDL language constructs
Parameter override using # and defparam (down one module sqrterr(e, a); level of hierarchy only)
Using # to override parameter
module sqrtb(z,a); parameter asize=4; output [(asize-1):0] z; input [(asize-1):0] a; endmodule module sqrterr(e, a); output [7:0] e; input [7:0] a; output [7:0] e; input [7:0] a; sqrtb #(8) sq1(.z(e), .a(a));
Using defparam to override parameter
sqrtb sq1(.z(e), .a(a)); defparam sq1.asize = 8;
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Supported VHDL Constructs

Synplify Pro tool supports a synthesizable subset of VHDL93 (IEEE 1076), and the following IEEE library packages:
std_logic_1164 numeric_std std_logic_unsigned std_logic_signed std_logic_arith
Note : The VHDL compiler follows the VHDL93 coding style, this
should be remembered especially during post synthesis simulations.
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Supported VHDL HDL Language Constructs
Inputs , outputs and inouts of the following types std_logic, std_logic_vector, integer, positive, signed, unsigned, records, arrays & user-defined types All operators
Logical
AND, NAND, OR, NOR, XOR, XNOR
Arithmetic
+, -,*, **, /, rem, mod
Relational
>, <, =, >=, /=, <=
Shift Operators
Shift_Left, Shift_right, Rotate_Left, Rotate_right,SHL, SHR, SHL, SHR
Behavioral statements
if-else-if, case, if-generate, for-loop, for-generate, when
Assignments
<=[for signals], :=[for variables]
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Generics
entity sqrterr is entity sqrtb is generic (asize : integer := 4); port( z : out bit_vector(asize-1 downto 0); a : in bit_vector(asize-1 downto 0)); end sqrtb; architecture arch1 of sqrtb end arch1; end arch2; architecture arch2 of srterr is begin sq1 : sqrtb generic map (asize => 8) port map( z => e, a => a); port( e : out bit_vector(7 downto 0); a : in bit_vector(7 downto 0)); end sqrterr;
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Mixed Verilog/VHDL
Synplify Pro tool 6.1 supports mixed HDL design Can add both Verilog and VHDL files to project The top module/entity name has to be specified in the UI If a Verilog file instantiates a VHDL design, the Verilog language rules apply. Similarly if a VHDL file instantiates a Verilog design, the VHDL language rules apply Current limitations
Generics or parameters cannot be passed across language boundaries VHDL User defined types for ports cannot be used across language boundaries
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Mixed HDL Designs
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Coding Style -- Flip Flops with Asynchronous Reset

always @(posedge clk or posedge reset) begin if (reset == 1b1) q = 1b0; else if (enable == 1b1) q = data; end
RTL View
Always probe synchronous signals inside rising edge/falling clock edge condition check. Do not list the enable condition in the event expression of the always block, because it should not trigger the always block to execute upon changing.
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Coding Style -- Flip Flops with Synchronous Reset

always @(posedge clk) begin if (reset == 1b1) q = 1b0; else if (enable == 1b1) q = data; end
RTL View
Always probe synchronous signals inside rising edge/falling clock edge condition check. Do not list the enable condition in the event expression of the always block, because it should not trigger the always block to execute upon changing. Do not include the reset signal in the event expression for a synchronous reset flip-flop
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RAM Coding Styles - Single Port RAM

RTL View
reg [7:0] mem[0:127]; always @(posedge clk) if (we) mem[addr] <= din; assign dout = mem[addr];
The write process has to be synchronous for the RAM to be inferred by the compiler The read process can either be synchronous or asynchronous Resets on the memory are not yet supported The address must be at least 2 bits wide for the compiler to infer a RAM
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RAM Coding Styles - Dual Port RAM

reg [7:0] mem[0:127]; reg [6:0] raddr_reg; always @(posedge clk) begin raddr_reg <= raddr; if (we) mem[waddr] <= din; end assign dout = mem[raddr_reg];
RTL View
The write process has to be synchronous for the RAM to be inferred by the compiler The read process can either be synchronous or asynchronous Resets on the memory are not yet supported The address must be at least 2 bits wide for the compiler to infer a RAM
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Coding Style -- ROM

module rom(z, a); output [3:0] z; input [4:0] a; reg [3:0] z; always @(a) begin case (a[4:1]) 4'b0000: z = 4'b1000; 4'b0001: z = 4'b0101; 4'b0010: z = 4'b0011; 4'b0011: z = 4'b1010; 4'b0111: z = 4'b1000; 4'b1000: z = 4'b0101; 4'b1001: z = 4'b0011; 4'b1011: z = 4'b1010; 4'b1100: z = 4'b1000; 4'b1101: z = 4'b0101; 4'b1110: z = 4'b0011; 4'b1111: z = 4'b1010; default: z = 4'bx; endcase end endmodule
RTL View
ROM Table View
The ROM must be at least half full for it to be inferred. The address must be at least 2 bits wide for the compiler to infer a ROM
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Coding Style -- FSM

Recommended Guidelines for FSM Coding Style
Separate always block / process for sequential and combinatorial portions
Easier to read - Obvious what is being registered Better control over type of register element used - synchronous or asynchronous reset
Represent States by defined labels / enumerated types

Easier to read - Less prone to make errors during coding
Assign default values to outputs derived from the FSM before the case statement
Easier to read - less clutter from signals that are assigned rarely Avoids unwanted latches
Assign state to X in the default clause of the case statement

Avoids mismatches between simulation of pre and post synthesis versions
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Coding Style -- FSM

module FSM1 (clk, rst, enable, data_in, data_out, state0, state1, state2); input clk, rst, enable; input [2:0] data_in; output data_out, state0, state1, state2; parameter deflt=2'bxx; parameter idle=2'b00; parameter read=2'b01; parameter write=2'b10; idle : if (enable) begin state0 <= 1'b1; data_out <= data_in[0]; next_state <= read; end else begin next_state <= idle; end read : if (enable) begin state1 <= 1'b1; data_out <= data_in[1]; next_state <= write; end else begin next_state <= read; end write : if (enable) begin state2 <= 1'b1; data_out <= data_in[2]; next_state <= idle; end else begin next_state <= write; end default : next_state <= deflt; endcase end endmodule
Defined labels for states
reg data_out, state0, state1, state2; reg [1:0] state, next_state; always @(posedge clk or negedge rst) if (!rst) state <= idle; else state <= next_state;
Always block with combinatorial portion
Always block with sequential portion
always @(state or enable or data_in) begin state0 <= 1'b0; Default values for state1 <= 1'b0; state2 <= 1'b0; outputs of FSM data_out <= 1'b0; case (state)
Assign X to state in default case
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Coding Style -- FSM

RTL View
FSM Viewer
Transition Table
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Compiler Options -- Symbolic FSM Compiler

Symbolic FSM Compiler
Option set in the project file Allows compiler to recognize, extract and optimize state machines Decides the best encoding for the state machine based on the number of states in the FSM FSM Synthesis includes:
Reachability Analysis Transition logic minimization
Equivalent Compiler directive: syn_state_machine
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Compiler Options -- Symbolic FSM Compiler
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Compiler Directive -- syn_state_machine

Enables Symbolic FSM Compiler optimization on an individual basis. Apply to state register declarations Compiler Directive equivalent to Symbolic FSM Compiler Project option Example:
Verilog
module prep3(CLK, RST, IN, OUT); input CLK, RST; input [7:0] IN; output [7:0] OUT; reg [7:0] OUT; reg [7:0] current_state /* synthesis syn_state_machine=1 */;
VHDL
signal current_state : std_logic_vector(7 downto 0); attribute syn_state_machine : boolean; attribute syn_state_machine of current_state : signal is true;
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Compiler Directive -- syn_encoding

Symbolic FSM Compiler implements state machines with different encodings depending on the number of states in the FSM
1-4 states : sequential 5-24 states : onehot > 24 states : gray
Over-ride default encoding of FSM Compiler with syn_encoding Applied on an individual register Example:
Verilog
reg [7:0] current_state /* synthesis syn_encoding = sequential */;
VHDL
signal current_state : std_logic_vector(7 downto 0); attribute syn_encoding : string; attribute syn_encoding of current_state : signal is sequential;
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Compiler Directive -- syn_encoding

Allowed values for syn_encoding
sequential onehot gray safe : forces the state machine to the reset state, if an invalid state is reached
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Compiler Options -- Resource Sharing

Resource Sharing
Option set in project file Allows compiler to share arithmetic operators, such as adders, subtractors, incrementors etc., over mutually exclusive statements, such as branches of a case statement Reduces area of design Equivalent Compiler directive: syn_sharing
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82

Resource sharing ON
module res_share (a, b, c, d, e, f, c1, c2, y); input a, b, c, d, e, f; input c1, c2; output y; reg y; always@(a or b or c or d or e or f or c1 or c2) begin if (c1) y = a + b; else if (c2) y = c + d; else y = e + f; end endmodule
Adders shared with Resource Sharing ON
More Adders used with Resource Sharing OFF
Resource sharing OFF
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Compiler Directives -- syn_sharing

Enables ("on") or disables ("off") the resource sharing of operators inside of the module during synthesis. The default value is "on". Applied to modules individually or globally Compiler Directive equivalent to the Resource Sharing Project option Example:
Verilog
module alu(out, opcode, a, b) /* synthesis syn_sharing = "off" */;
VHDL
architecture rtl of top is attribute syn_sharing : string; attribute syn_sharing of rtl : architecture is off;
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Compiler Directive parallel_case(Verilog only)

parallel_case
Use to force a parallel multiplexed structure rather than a priority encoded structure With parallel_case directive Only used in Verilog Example:
always @(select or a or b or c or d) begin casez (select) /* synthesis parallel_case */ 4'b???1: out = a; 4'b??1?: out = b; 4'b?1??: out = c; 4'b1???: out = d; default: out = 'bx; endcase end
Without parallel_case directive

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Compiler Directive full_case(Verilog only)

full_case
Used with a case, casex, or casez statement Indicates that all possible values have been defined, and that no additional hardware is needed to preserve signal values. With full_case directive Example:
Without full_case directive, latch generated
always @(select or a or b or c or d) begin casez (select) /* synthesis full_case */ 2'b00: out = a; 2'b01: out = b; 2'b10: out = c; endcase end
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Compiler Directive translate_on/off

Portion of HDL code between translate_off and translate_on ignored by compiler Used to ignore simulation-specific or behavioral code Every translate_off should be followed by a translate_on statement. These directives can not be nested. Example:
module ckt(s1, s2, a, b); output s1, s2; input a, b; assign s1 = a & b; /* synthesis translate_off */ assign s2 = a | b; /* synthesis translate_on */ endmodule Compiler ignores statements between translate_on and translate_off, s2 is unassigned.
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Without translate_on/translate_off statements
Compiler Directive -- syn_black_box

Used to define a module or component as a black box
Only the interface is specified, and the behavior is ignored.
syn_black_box used to instantiate:

Vendor primitives and macros (including I/Os). User-designed macros whose functionality was defined in a schematic editor, or another input source
Example:
Verilog
module OBUF(O, I) /* synthesis syn_black_box */;
VHDL
component OBUF port( O : out std_logic; I : in std_logic); end component; attribute syn_black_box : boolean; attribute syn_black_box of OBUF : component is true; Synthesis Optimizations in the Compiler
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Compiler Directive -- syn_keep

Maintains a net throughout synthesis
During synthesis, nets may not be maintained in order to create an optimized circuit
Applied to wires in Verilog and signals in VHDL Nets can be preserved to:
Probe their value during simulation Prevent certain optimizations, such as clock enable optimization
Example
VHDL
signal q_tmp : std_logic; attribute syn_keep : boolean; attribute syn_keep of q_tmp : signal is true;
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Compiler Directive -- syn_keep

Example
Use syn_keep to specify en1 as clock enable
module clken(d, en1, en2, clk, rst, q); input d; input clk, rst, en1, en2; output q; reg q; wire q_tmp /* synthesis syn_keep = 1 */; assign q_tmp = en2 ? d : q; always @(posedge clk or posedge rst) if (rst) q <= 0; else if(en1) q <= q_tmp; endmodule
Clock enable signal
Without syn_keep, compiler optimizes en1&en2 as the clock enable

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Asynchronous Loads
always @(posedge clk or posedge load ) begin if (load) q = d0; else q = d; end
Synplify Pro Tool Warning:

Register q with async load is being synthesized in compatibility mode. A synthesis/simulation mismatch is possible.
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Asynchronous Loads
To avoid simulation mismatches, change the RTL code as shown below
wire tmp_set = load & d0; wire tmp_rst = load & ~d0; always @(posedge clk or posedge tmp_rst or posedge tmp_set ) begin if (tmp_rst) q = 0; else if (tmp_set) q = 1; else q = d; end
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Latch generation
module newmux (out, a, b, c, select); input a, b, c; output out; input[1:0] select; reg out; always@(a or b or c or select) begin if (select ==2'b10) out = a; else if (select == 2'b01) out = b; else if (select == 2'b11) out = c; end endmodule Latch generated because of missing if condition, select = 2b00
Synplify Pro Tool Warning:

Latch generated from always block for signal out, probably caused by a missing assignment in if or case statement.
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Priority Encoding vs Parallel Case

Priority encoding inferred from if-then-else or case construct Use case statement with parallel_case attribute to infer no priority
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module if_else(a, b, c, d, e, clk); output b; input a, b, c, d, e, clk; reg b; always @(posedge clk) begin if (a) b = c; else if (d) b = e; else b = bx; end endmodule
b gets e only when d=1b1 and a != 1b1. This is the implicit priority of an if-then-else construct
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Consider the previous example, if inputs a and d are mutually exclusive, use a case statement and the parallel_case directive
module case_parallel(a, b, c, d, e, clk); input a, c, d, e, clk; output b; reg b; always @(posedge clk) begin casez({d, a}) /* synthesis parallel_case */ 2'b?1: b = c; 2'b1?: b = e; default: b = 'bx; endcase end endmodule
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Warning - Incomplete sensitivity list
Synplify Pro Tool Warning :

Incomplete sensitivity list - assuming completeness Referenced variable B is not in sensitivity list
A Y B
Dynamic Truth Table

module nand2(A,B,Y1); input A,B; output Y1; reg Y1; always @(A) begin Y1 = !(A & B); end endmodule
A 0 1 1 0
B 0 1 0 1
Y1 1 0 0 1
Y2 1 0 1 1
module nand2(A,B,Y2); input A,B; output Y2; reg Y2; always @(A or B) begin Y2 = !(A & B); end endmodule
97
Asynchronous State Machines

An asynchronous state machine has states, and combinational loops, but no clearly defined clock Do not use synthesis tools to design asynchronous state machines; the synthesis tool might remove hazard-suppressing logic. Synplify Pro tool will gives a "Found combinational loop" warning message for an asynchronous state machine when it detects combinational loops in continuous assignment statements, always blocks, and built-in gate-primitive logic.
98
Asynchronous State Machines

Example:
module async1 (out, g, d); output out; input g, d; assign out = g & d | !g & out | d & out; endmodule ____________________ module async2 (out, g, d); output out; input g, d; reg out; always @(g or d or out) begin out = g & d | !g & out | d & out; end endmodule
99
Unused Inputs
Inputs driving logic that do not drive outputs directly or indirectly are flagged as unused
module dff(q1, data1, data2, clk); output q1; input data1, data2, clk; reg q1, q2; always @(posedge clk) begin q1 = data1; end always @(posedge clk) begin q2 = data2; end endmodule
Synplify Pro Tool Warning :

@W:c:\design\dff.v":4:13:4:17|Input data2 is unused
Data2 does not have a path to a primary output.
100
Optimization Removal of Redundant Logic

Compiler removes redundant logic, by default
module dff(q1, q2, q3, q4, data1, clk); output q1, q2, q3, q4; input data1, clk; reg q1, q2, q3, q4; always @(posedge clk) begin q1 = data1; q2 = data1; q3 = data1; q4 = data1; end endmodule
Registers q1, q2, q3, and q4 are identical. Hence, the compiler optimizes 3 of the 4 registers away.
Synplify Pro Tool Warning

Removing sequential element q4
101
Lab 2
Lab 2
102
Synthesis Optimizations in the Mapper

103
Mapper Overview
How the Mapper works Timing Constraints Attributes to control synthesis
104
How the Mapper Works

Inputs to the Mapper
Technology independent netlist[.srs] created by the compiler Target Technology specified in the project file Timing Constraints and attributes specified in the constraints file[.sdc]
Goal
To fit the design into the smallest programmable device AND to operate the device at the fastest frequency
In order to achieve optimal results, the mapper uses the following components:
B.E.S.T Algorithms
Integrated Module Generation and Mapping
Hierarchy Optimization
Hierarchy Flattening and Reconstructing
Technology Independent Optimizations

Area Minimization Timing Optimization
Direct mapping to technology primitives Critical Path Re-synthesis

105
B.E.S.T. Algorithms
Integrated Module Generation & Mapping
Maintains inferred components(adders, multipliers, memory) at an abstract level Automatically combines these extracted components with associated logic
Benefit
Takes maximum advantage of the resources available in the target technology
Adder Module Control Logic
Synplify Pros Integrated Module Generation Data path & Control Integrated into one logic block
106
Logic Block
Module Generation Example

if (cond) z = a+1; else z = b; b[3:0] a[3] carry a[2]
cond b[3] a[3]
F G
clb
F G
z[3]
a[2] b[2] cond
F
carry
z[3]
z[2]
G
clb
z[2]
a[1] carry a[0] cond
F G
clb
F G
cond b[1] a[1]
z[1]
a[0] b[0] cond
F
carry
z[1]
z[0]
G
clb
z[0]
Synplify Pro Tools Integrated Module Generation
The Traditional Approach
107
Mapper starts with the original hierarchy Performs global analysis and optimizes hierarchy by creating new structures, if needed Rebuilds hierarchy by keeping existing boundaries or creating new ones Provides timing budget for each hierarchical block Converges on the timing goal by making an area/time tradeoff
108
Logic implemented in one lookup table with hierarchical boundary optimization
module and2_x(a, b, c); input a, b; output c; assign c = a & b; endmodule module top(a0, a1, b, c); input a0, a1, b; output c; and2_x an1(a0, a1, an1_out); and2_x an2(an1_out, b, c); endmodule
Two levels of logic generated without hierarchical boundary optimization
109
Technology Independent Optimization

Area Minimization
Boolean equation simplification Mapping the abstract RTL components to gates
Mux decomposition FSM decomposition Constant propagation Buses to bits(i.e. One 8-bit reg object to 8 individual flip-flops)
Mux Decomposition
Constant Propagation
110
Technology Independent Optimization

Timing Optimization:
Gate level timing model
Intrinsic gate delay Fanout dependent
Delay = intrinsic gate delay + T[FO]
Timing constraints
User Specified Controls levels of logic between two registers
111
Direct Mapping to Technology Primitives

a b sel[0] sel[1] c d sel[0] sel[1] sel[1]
LUT LUT
z
cascade
Altera Flex 10K

sel[1] a b c d sel[0]
o o o o o o o
case sel is when 00 => z <= a; when 01 => z <= b; when 10 => z <= c; when 11 => z <= d; when others => z <= (others => X); end case;
a b sel[0] z PFUMUX
c d sel[0]
Lucent
a
a b sel[0] z
F H G
CLB
z
b z c d
sel[1]
c d sel[0]
o o
sel[0] sel[1]
QuickLogic
Xilinx XC4000
Actel
112
Mapping to Special Components In Selected Vendors

Xilinx
MUXF5/F6, Shift Register LUT, RAMs, ROMs, Carry Chains
Altera
Logic Element with Cascade , Quick-feedback counter, EABs and ESBs
Actel
CM8
Lucent
RAM, Counters, PFU Muxes
113
MUX8x1(Xilinx Virtex)
module mux8x1(din, sel, dout); input [7:0] din; input [2:0] sel; output dout; assign dout = din[sel]; endmodule
Slice A
Slice View in Virtex
Slice B
114
Shift Register LUT(Xilinx Virtex)
module srltest(z1, z2, a, en, clk); output z1, z2; input a; input clk, en; reg [10:0] dataa, datab; always @(posedge clk) dataa = {dataa[9:0], a}; always @(posedge clk) if (en) datab = {datab{9:0], a}; assign z1 = dataa[10]; assign z2 = datab[10]; endmodule
115
Logic Element with Cascade (Altera APEX)
module cascade_ex(din, dout); output dout; input [7:0] din; reg dout; assign dout = &din; endmodule
116
Quick Feedback Counter (Altera APEX)
module cntr(clk, q, aclr); output [3:0] q; input clk, aclr; reg [3:0] q; always @(posedge clk or posedge aclr) if (aclr) q <= 0; else q <= q + 1; endmodule
117
CM8 (Actel)
module module_d(a, b, sum, clk, rst); output [7:0] sum; input clk, rst; input [7:0] a, b; reg [7:0] sum; reg [7:0] a_int, b_int; always @(posedge clk or posedge rst) if (rst) begin a_int <= 0; b_int <= 0; sum <= 0; end else begin a_int <= a; b_int <= b; sum <= a_int + b_int; end endmodule
118
RAM (Lucent)
module ramtest(address, data_in, data_out, clk, we); output [0:0] data_out; input clk, we; input [0:0] data_in; input [2:0] address; reg [0:0] data[0:7]; reg [7:0] a_int, b_int; always @(posedge clk) begin if (we) data[address] <= data_in; data_out <= data[address]; end endmodule
RAMs are also inferred for Xilinx, Altera, Quicklogic and Cypress Technologies
119
Critical Path Re-synthesis

Reconstruct critical path logic
Incremental optimization targeting new critical path
Critical Path is from register A to register C
120
Timing Constraints
Apply timing constraints to drive synthesis Basic timing constraints include:
Clock frequency Input/Output delay Multi-cycle path False path
121
Static Timing Analysis Types of Paths

Input to Register Register to Register Output to Register
Input to Output
122
Timing Constraints
Essential for achieving the performance goal
define_input_delay
Delay
Big Delay
define_multicycle_path define_clock D Q
Delay
Delay
define_output_delay
123
Clock Frequency
Clock Period
If the equation Tco + Tcomb + Tsu < clock period is valid, data transfers from register to register
The Tcomb value guides the mapper to synthesize the combinational logic and reduce the levels of logic between the registers.
124
Input and Output Delay

Input Delay Output Delay
Chip
Chip
If Tindelay or Toutdelay= 0, it means that a fictitious register exists at the input or output port.
125
Effect of Applying Timing Constraints
126
Multi-cycle Path
Impacts:
1. 2.
More logic is used Timing report is inaccurate

127
False Path
False Paths are of two types
Architectural false paths
Designer is aware that such paths exist
Code introduced false paths

Identify false paths after analyzing the schematic Use false path attributes to make Synplify Pro ignore these paths Is this path possible for x = 1 0 1 d 0 1
x
b
x
c
0 1
z x
128
Attributes
User Defined
Generic
syn_hier, syn_noclockbuf, syn_maxfan, syn_useioff
Technology-specific
Xilinx and Altera
syn_ramstyle, syn_romstyle
Can be applied in SCOPE editor or HDL code
129
syn_maxfan
Applied on an input or register Takes an integer value Specifies maximum fanout for an input or register Results in replication
module test(a, clk, rst, din, q); input [3:0] a; input [31:0] din; input clk, rst; output [31:0] q; reg [31:0] q; reg en /* synthesis syn_maxfan = 10 */; always @(posedge clk or posedge rst) begin if (rst) begin en <= 0; q <= 0; end else begin en <= &a; if (en) q <= din; end end
With syn_maxfan
Without syn_maxfan
endmodule
130
Automatic Flattening (syn_hier)

Can maintain boundary of a module by using syn_hier = hard Applied on modules/architectures Takes a string value
module inc(a_in, a_out) /* synthesis syn_hier = "hard" */; input [3:0] a_in; output [3:0] a_out; assign a_out = a_in + 1; endmodule module reg4(clk, rst, d, q) /* synthesis syn_hier = "hard" */; input [3:0] d; input clk, rst; output [3:0] q; reg [3:0] q; always @(posedge clk or posedge rst) if(rst) q <= 0; else q <= d; endmodule module top(clk, rst, q); input clk, rst; output [3:0] q; wire [3:0] a_in; inc i1(q, a_in); reg4 r1(clk, rst, a_in, q); endmodule
With syn_hier = hard
Automatic flattening, counter inferred

131
syn_noclockbuf
Turns off clock resource usage Used on ports or entire modules Takes a boolean value
module simpledff(clk, d, q); input [3:0] d; input clk /* synthesis syn_noclockbuf = 1 */; output [3:0] q; reg [3:0] q; always @(posedge clk) q <= d; endmodule
With syn_noclockbuf
Without syn_noclockbuf
132
syn_useioff
With syn_useioff
Used to control I/O register packing Can be applied on ports or entire modules Takes a boolean value
module dff(q, d, clock, reset); input d; input clock, reset; output q /* synthesis syn_useioff = 1*/; reg temp, q; always @(posedge clock or posedge reset) begin if (reset) begin tmp <= 0; q <= 0; end else begin tmp <= d; q <= tmp; end end endmodule
Without syn_useioff
133
syn_ramstyle
Determines the RAM implementation Applied on the RAM primitive Takes a string value
module ram_test(q, addr, data, we, clk); input [1:0] d; input clk, we; Input [2:0] addr; output [1:0] q; reg [1:0] mem[7:0] /* synthesis syn_ramstyle = registers */; always @(posedge clk) if (we) mem[addr] <= data; assign q = mem[addr]; endmodule
Without syn_ramstyle
With syn_ramstyle=registers
134
syn_romstyle
With syn_romstyle = block_rom
module romz(z,a); output [3:0] z;; input [4:0] a; reg [3:0] z /* synthesis syn_romstyle = logic */; always @(a) case (a) 5b00000 : z = 4b1011; 5b00001 : z = 4b0001; 5b00100 : z = 4b0011; 5b00110 : z = 4b0010; 5b00111 : z = 4b1110; 5b01001 : z = 4b0111; 5b01010 : z = 4b0101; 5b01101 : z = 4b0100; 5b10000 : z = 4b1100; 5b10001 : z = 4b1101; 5b10010 : z = 4b1111; 5b10011 : z = 4b1110; 5b11000 : z = 4b1010; 5b11010 : z = 4b1011; 5b11110 : z = 4b1001; 5b11111 : z = 4b1000; default : z = 4b0000; endcase end endmodule
With syn_romstyle = logic

135
Guidelines for Attribute Usage

Attributes can guide mapper to obtain optimal synthesis result Attributes are application-specific
i.e. syn_ramstyle/romstyle can be tailored to meet design needs
Guideline using Attributes:

Let the mapper decide how to synthesize the design Analyze the synthesis result in technology schematic Use the appropriate attribute to guide and control the mapper
136
Debugging with the HDL Analyst Module

137
Overview
Common features used in the HDL Analyst module
Cross-probing Filtering
HDL Analyst module - RTL View

B.E.S.T. Algorithms FSM Viewer
HDL Analyst module - Technology View

Critical Path analysis Cross-probing from Place and Route timing files
Putting it all together

138
Useful Features
Hierarchical and Flattened views
Allows users to see the hierarchy created in a design making design easier to look at. Also allows users to flatten the design. This makes it easier to see the overall flow of the design.
Cross-probing
Cross-probe between HDL code and RTL View or Technology view. Can also cross-probe between a Place and Route timing report file and the Technology View
139
Cross-probing in the HDL Analyst Module

Unique RTL View Analyze a technologyindependent schematic
Language Sensitive Editor Describe the design functionality
Technology View View post-mapped schematic with annotated timing
Bi-directional cross-probing between all three views

140
Useful Features (cont.)

Advanced filtering options
Allows a user to select and filter on one specific component or a group of components. From there, signals can be traced to sources or to all of the instances that the signal is attached to. Can also select two different components and show everything between these components.
Useful to locate critical paths reported after Place and Route Typically the start and end points are known and components between them can be viewed in the HDL Analyst module
141
Filtering in the HDL Analyst Module

No Filtering User can select the components of interest After Filtering Only those components are now shown
142
Filtering in HDL Analyst Module (cont.)

Select Net Driver User can inspect the driver of a specific net OR Select Net Instances Show everything that is connected to the net
143
Filtering in HDL Analyst Module (cont.)

Select Two Components Filter the selected components THEN Expand Paths Shows everything that is between the two components
144
RTL View
What is it?
Graphical representation of the HDL source code. Everything shown before any technology specific optimization.
Benefits
Allows users to see exactly what was written.
Novice designers can make sure that what they have written is what they want Expert designers can look for ways to improve their code
RTL code is kept at a high level of abstraction to make it easier to read.
145
RTL View
Schematic of what is in the source code No technology specific optimizations
146
Behavior Extraction Synthesis Technology Algorithms

B.E.S.T. Algorithms
Keeps synthesis at a higher level for a longer time Creates faster compile times. Makes the RTL view easier to look at and debug
High-Level Structure
a[3:0]
Low (Gate) Level Structure

[3:0 ]
[3]
IB U F
I
O
[3]
a _ib uf [3 ]
[0 ] [1 ] [2 ] [3 ]
R O M 16X 1
A0 A1 A2 A3
O
[3 ]
[3]
OBUF
I
O
[3]
[3:0]
z[3:0]
z _ o b uf [3 ]
ro m o ut.I_ 1 2
[2]
IB U F
I
O
[2]
a[3:0]
[3:0] [3:0]
rom
A[3:0] DOUT[3:0]
a _ib uf [2 ]
[3:0] [3:0]
z[3:0]
IB U F
I
O
[0 ] [1 ] [2 ] [3 ]
R O M 16X 1
A0 A1 A2 A3
O
[1 ]
[2]
OBUF
I
O
[2]
z _ o b uf [2 ]
romout[3:0]
ro m o ut.I_ 1 1
[1]
[1]
a _ib uf [1 ]
[1]
OBUF
I
O
[1]
z _ o b uf [1 ]
[0 ] [1 ] [2 ] [3 ]
[0]
R O M 16X 1
A0 A1 A2 A3
O
[2 ]
[0]
IB U F
I
O
a _ib uf [0 ]
ro m o ut.I_ 1 0
[0]
OBUF
I
O
[0]
z _ o b uf [0 ]
[0 ] [1 ] [2 ] [3 ]
R O M 16X 1
A0 A1 A2 A3
O
[0 ]
ro m o ut.I_ 9
147
FSM Viewer
State Machines shown as onehot encoding in RTL View
No decoding needed, onehot is easier to interpret.
FSM Viewer invoked by pushing into State Machine primitive in RTL View
Has three tabs
State Transition Diagram RTL Encoding
Shows state machine as onehot encoding
Mapped Encoding
Shows exactly how the mapper implemented state machine Direct link between state registers and HDL code
148
FSM Viewer (cont.)
RTL View with state machine primitive[onehot representation]
FSM Viewer State Transition Diagram and Transition Table
149
FSM Viewer (cont.)

Pushing down into state machine shows the transition table
150
FSM Viewer (cont.)

The RTL Encoding tab shows the onehot table for the RTL view
151
FSM Viewer (cont.)

The Mapped Encoding tab shows how the state machine was finally implemented
152
Technology View
What is it?
Graphical representation of the optimized and mapped design. Contains the exact components that make up the target architecture (RAMs, ROMs, LUTs, LABs .).
Benefits
Allows users to see exactly how their design was implemented. Critical paths can be looked at directly and can suggest ways of improving delay.
153
Technology View
(cont.)
Shows the design after completion Shows architecture specific components
154
Critical Path Analysis
View Critical Path
Filter Critical Path
Technology View
155
Cross-probing with Place and Route

After place and route, fitting tools generate timing reports with critical path information
This information can be imported into the Synplify Pro tool to show the paths that the Place and Route tool is reporting on. Any text file that lists the components in a path can be crossprobed into HDL Analyst module.
Steps to cross-probe
Open the RTL View Open the Flattened Technology View
This facilitates viewing the entire critical path
Open the Place and Route timing report file in the Synplify Pro tool Select the critical path Cross-probe to HDL Analyst module
156
Cross-probing (cont.)
Place and Route timing report File with Critical Path selected Technology View showing the selected critical path
157

Test case
Hierarchical design Two lower level modules
Design has gone through Place and Route

Requested frequency is 80 MHz Result is 69 MHz
Try cross-probing between timing report file and Technology View

Technology view shows many levels of logic between start and end point of critical path
Try cross-probing between Technology View and RTL View

Select the start and end point of critical path in Technology View Cross-probe to RTL View Expand paths between the start and end point in the RTL View
158

Tech view Start and end points RTL view Flatten RTL and choose Expand Path
159
RTL view Expand the output to see what is there
160
RESULTS 82 MHz!!!!
161
Labs 3 & 4
Labs 3 & 4
162

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FPGA Synthesis with the Synplify Pro Tool

Debugging with HDL Analyst RTL Debugging and Analysis Environment

Synplify Pro Tool User Guide

Synplify Pro Tool Reference Guide

Synplify First Level Support

Design Flow and Synthesis Concepts

HDL Design Methodology

simulate mapped design

Place & Route

post layout simulation

chip Design Flow and Synthesis Concepts

Why HDL Design Entry?

Higher level of design abstraction

Design Flow and Synthesis Concepts

Synthesis in the Synplify Pro Tool

Input Files to the Synplify Pro Tool

Design Flow and Synthesis Concepts

Synthesis Process in the Synplify Pro Tool

Design Flow and Synthesis Concepts

Synthesis Process in the Synplify Pro Tool

Design Flow and Synthesis Concepts

Output Files From the Synplify Pro Tool

Constraints file for the P & R tool

Mapped VHDL or Verilog netlist for post synthesis simulation

Design Flow and Synthesis Concepts

Project Management Overview

Invoking the Synplify Pro Tool

Invoking the Synplify Pro s/w in batch mode

Lab 1[Invoke the Synplify Pro Tool]

The Synplify Pro Tool Project File

Text file with Tcl commands

A Sample Run -- Creating a New Project

Creates a new project Helpful for new users Project Management

A Sample Run -- Adding Source Files

Filter on file types Project Management

A Sample Run -- Adding Source File

Integrated with the synthesis environment

A Sample Run -- HDL Source File

Keywords are blue

Strings are red

A Sample Run -- Select Device Options

Device mapping options

A Sample Run Create a New Constraints File

A Sample Run Apply Basic Timing Constraints

Clock constraint of 100 MHz specified in the Clocks tab

Default Input and Output delay of 5 ns specified in Inputs/Outputs tab

Selecting Constraint File & Output Files

Simulation files and constraint files

A Sample Run -- Run

The famous Run button!

Lab 1[Run a Simple Project]

Viewing Results Log File

Viewing Results -- Log File

Warnings and errors can be cross-probed to the HDL code

Log File -- Compiler Report

Log File -- Mapper Report

SCOPE Editor Information

Log File -- Timing Report

Log File Resource Usage Report

Part and package used Percentage utilization

Lab 1[View Results in the Log File]

Viewing Results Log Watch Window