04 RTL Design

Register Transfer Level Design with Verilog
Adapted from Z. Navabi

Portions Copyright Z. Navabi, 2006
CSE 467
Verilog Digital System Design

2.1 RT Level Design 2.1.1 Control/data partitioning 2.1.2 Data part 2.1.3 Control part 2.2 Elements of Verilog 2.2.1 Hardware modules 2.2.2 Primitive instantiations 2.2.3 Assign statements 2.2.4 Condition expression 2.2.5 Procedural blocks 2.2.6 Module instantiations
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2.3 Component Description in Verilog 2.3.1 Data components 2.3.2 Controllers 2.4 Testbenches 2.4.1 A simple tester 2.4.2 Tasks and functions 2.5 Summary
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RT Level Design
RT level design: Taking a high level description of a design Partitioning Coming up with an architecture Designing the bussing structure Describing and implementing various components of the architecture Steps in RT level design: Control/Data Partitioning Data Part Design Control Part Design
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RT Level Design
RT Level Design Control/data Partitioning
Data Part
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Control Part
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Control/Data Partitioning
RT Level Design
Control/data Control/data Partitioning Partitioning
Data Part
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Control Part
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Control/Data Partitioning
RT Level Design
DataPath Reg Flags & status Control
Data Inputs
Control Outputs
Opcode Data flow Control signals
Data Outputs
Control Inputs
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Data Part
RT Level Design
Control/data Partitioning
Data Part Data Part
Control Part
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Data Part
DataPath Reg Flags & status
Data Inputs
Opcode Data flow Control signals
Data Outputs
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Data Part
module DataPath Going to the control (DataInput, DataOutput, Flags, Opcodes, part, provide flags ControlSignals); and status of the data input [15:0] DataInputs; Control Signals: output [15:0] DataOutputs; Inputs to data part, output Flags, ...; sent to the data output Opcodes, ...; components and input ControlSignals, ...; busses // instantiation of data components // ... // interconnection of data components // bussing specification Control Signals for the endmodule busses: Select the sources DataPath Module
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Output Signals:
and routing of data from one data component to another

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Data Part
module DataComponent (DataIn, DataOut, ControlSignals); DataIn, DataOut, input [7:0] DataIn; DataIn; output [7:0] DataOut; DataOut; input ControlSignals; // Depending on ControlSignals // Operate on DataIn and // Produce DataOut endmodule Partial Verilog Code of a Data Component
Data Component: Shows how the component uses its input control signals to perform various operations on its data inputs
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Control Part
RT Level Design
Control/data Partitioning
Data Part
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Control Part Control Part
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Control Part
Control Flags & status Opcode Data flow Control signals
Control Outputs
Control Inputs
Consists of one or more state machines to keep the state of the circuit.
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Makes decisions as to when and what control signals to issue depending on its state.
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Control Part
module ControlUnit (Flags, Opcodes, ExternalControls, ControlSignals); input Flags, ...; Takes control input Opcodes, ...; inputs from the Data Part input ExternalControls, ...; output ControlSignals; // Based on inputs decide : // What control signals to issue, // and what next state to take endmodule Outline of a Controller
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Elements of Verilog
We discuss basic constructs of Verilog language for describing a hardware module.
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Elements of Verilog
Hardware Modules Primitive Instantiations Condition Expression Assign Statements Procedural Blocks
Module Instantiations
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Hardware Modules
Hardware Modules Modules Primitive Instantiations Condition Expression Assign Statements Procedural Blocks
Hardware Modules
Keyword module module : The Main Component of Verilog
module module-name Variables, wires, and List of ports; module parameters Declarations are declared. ... Functional specification of module ... Keyword endmodule endmodule Module Specifications
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Hardware Modules

There is more than one way to describe a Module in Verilog. May correspond to descriptions at various levels of abstraction or to various levels of detail of the functionality of a module. Descriptions of the same module need not behave in exactly the same way nor is it required that all descriptions describe a behavior correctly. We discuss basic constructs of Verilog language for a hardware module description. We show a small example and several alternative ways to describe it in Verilog.
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Primitive Instantiations
Hardware Modules Primitive Primitive Instantiations Condition Expression Assign Statements Procedural Blocks
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a s_bar s b b_sel a_sel
Logic Gates called Primitives
A Multiplexer Using Basic Logic Gates
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module MultiplexerA (input a, b, s, output w); (input wire a_sel, b_sel, s_bar; a_sel, b_sel, not U1 (s_bar, s); Instantiation and U2 (a_sel, a, s_bar); (a_sel, of Primitives and U3 (b_sel, b, s); (b_sel, or U4 (w, a_sel, b_sel); a_sel, b_sel); endmodule Primitive Instantiations
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Assign Statements
Hardware Modules Primitive Instantiations Condition Expression Assign Assign Statements Statements Procedural Blocks
Assign Statements
Continuously drives w with the right hand side expression
module MultiplexerB (input a, b, s, output w); (input assign w = (a & ~s) | (b & s); endmodule Assign Statement and Boolean
Using Boolean expressions to describe the logic
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Condition Expression
Hardware Modules Primitive Instantiations Condition Condition Expression Assign Statements Procedural Blocks
Condition Expression
Can be used when the operation of a unit is too complex to be described by Boolean expressions
module MultiplexerC (input a, b, s, output w); (input assign w = s ? b : a; endmodule Assign Statement and Condition Operator
Useful in describing a behavior in a very compact way Very Effective in describing complex functionalities
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Procedural Blocks
Procedural Blocks
always statement Sensitivity list
module MultiplexerD (input a, b, s, output w); (input reg w; always @(a, b, s) begin if (s) w = b; else w = a; Can be used when the end if-else operation of a unit is endmodule statement Procedural Statement
too complex to be described by Boolean or conditional expressions
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Module Module Instantiations

module ANDOR (input i1, i2, i3, i4, output y); (input ANDOR assign y = (i1 & i2) | (i3 & i4); module is endmodule defined // module MultiplexerE (input a, b, s, output w); (input wire s_bar; not U1 (s_bar, s); ANDOR U2 (a, s_bar, s, b, w); ANDOR endmodule module is Module Instantiation
instantiated
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a s b
i1 i2 i3 i4
ANDOR y w
Multiplexer Using ANDOR

Component Description in Verilog

Component Description
Data Components
Controllers
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Data Components
Data Data Components Components
Controllers
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Data Components
Data Components Multiplexer Counter Shift-Register Interconnections
Flip-Flop Full-Adder ALU
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Multiplexer
Multiplexer
Defines a Time Unit of 1 ns and Time Precision of 100 ps. ps.
`timescale 1ns/100ps module Mux8 (input sel, input [7:0] data1, data0, (input sel, output [7:0] bus1); assign #6 bus1 = sel ? data1 : data0; endmodule
A 6-ns Delay Octal 2-to-1 MUX is specified for all values assigned to bus1 Selects its 8-bit data0 or data1 input depending on its sel input.
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Flip-Flop
Flip-Flop
`timescale 1ns/100ps
Synchronous reset input input Flip-Flop The Body of always triggers on statement is module Flop (reset, din,the , qout); clk, qout); clk falling edge of Aexecuted at the as a Signal declared input reset, din, clk; ; clk clk Input reg to be capable negative edge of of output qout; qout; holding its values the clk signal reg qout; qout; between clock edges
Flip-Flops are A Software-Like used in data part forProceduraldata flags and Coding Style storage
always @(negedge clk) begin @(negedge clk) if (reset) qout <= #8 1'b0; else qout <= #8 din; end A Non-blocking endmodule Flip-Flop Description
An 8-ns Delay Assignment
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Counter
A 4-bit modulo-16 Counter
Counter
4-bit `timescale 1ns/100ps Register Counter4 (input reset, clk, module (input clk,
Counters are used in data part for registering data, accessing memory or queues and register stacks
output [3:0] count); Constant reg [3:0] count; Definition always @(negedge clk) begin @(negedge clk) if (reset) count <= #3 4'b00_00; else count <= #5 count + 1; end When count endmodule reaches 1111, Counter Verilog Code
the next count taken is 10000
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Full-Adder
Full-Adder
A combinational circuit All Changes Occur after `timescale 1ns/100ps 5 ns Full-Adders are used in data part for building Carry-Chain adders
module fulladder (input a, b, cin, output sum, cout); (input cin, cout); assign #5 sum = a ^ b ^ cin; cin; assign #3 cout = (a & b)|(a & cin)|(b & cin); cin); endmodule All Changes One delay for Verilog Code Full-Adder
every output: tPLH and tPHL Occur after 3 ns
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Shift-Register
2 Mode inputs m[1:0] form a `timescale 1ns/100ps 2-bit number
Shift-Register
An 8-bit Universal Shift Register
module ShiftRegister8 (input sl, sr, clk, input [7:0] ParIn, sl, sr, clk, Case Statement ParIn, input [1:0] m, output4 reg [7:0] ParOut); ParOut); With case-alternatives always @(negedge clk) begin @(negedge clk) case (m) m=0 : Does Nothing 0: ParOut <= ParOut; ParOut; 1: ParOut <= {sl, ParOut [7:1]}; {sl, 2: ParOut <= {ParOut [6:0], sr}; m=1,2: Shifts Right {ParOut sr}; m=1,2: and Left 3: ParOut <= ParIn; ParIn; default: ParOut <= 8'bX; default: endcase m=3 : Loads its Parallel end input into the register endmodule
and default Value
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Shift-Register (Continued)
`timescale 1ns/100ps module ShiftRegister8 (input sl, sr, clk, input [7:0] ParIn, sl, sr, clk, ParIn, input [1:0] m, output reg [7:0] ParOut); ParOut);
always @(negedge clk) begin @(negedge clk) case (m) 0: ParOut <= ParOut; ParOut; 1: ParOut <= {sl, ParOut [7:1]}; {sl, 2: ParOut <= {ParOut [6:0], sr}; {ParOut sr}; 3: ParOut <= ParIn; ParIn; default: ParOut <= 8'bX; default: Shifting the endcase ParOut to the left end endmodule
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Shift Right: The SL input is concatenated to the left of ParOut
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ALU
Flip-Flop Full-Adder ALU ALU
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ALU
`timescale 1ns/100ps module ALU8 (input [7:0] left, right, 2-bit mode Input to (input select one of its 4 input [1:0] mode, functions output reg [7:0] ALUout); ALUout); always @(left, right, mode) begin case (mode) 0: ALUout = left + right; Add 1: ALUout = left - right; Subtract 2: ALUout = left & right; AND 3: ALUout = left | right; OR default: ALUout = 8'bX; default: endcase end endmodule An 8-bit ALU
ALU (Continued) The Declaration of

`timescale 1ns/100ps module ALU8 (input [7:0] left, right, (input input [1:0] mode, output reg [7:0] ALUout); ALUout); always @(left, right, mode) begin Blocking case (mode) Assignments 0: ALUout = left + right; 1: ALUout = left - right; 2: ALUout = left & right; 3: ALUout = left | right; default alternative default: ALUout = 8'bX; default: puts all Xs on ALUOut Xs endcase if mode contains contains end anything but 1s and 0s 0s endmodule An 8-bit ALU
ALUout both as output and reg: reg: Because of assigning it within a Procedural Block
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Interconnections
Interconnections
Inbus Aside Bside
8
select_source
Mux8 and ALU examples forming a Partial Hardware
8
ABinput Function
8
Outbus
Partial Hardware Using MUX8 and ALU

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Interconnections
Instantiation of ALU8 and MUX8 A Set of parenthesis enclose port connections to the instantiated modules
ALU8 U1 ( .left(Inbus), .right(ABinput), .mode(function), .ALUout(Outbus) ); Mux8 U2 ( .sel(select_source), .data1(Aside), .data0(Bside), .bus1 (ABinput)); (ABinput));
and u2 u1Verilog: Code of The Partial Hardware Example Instance Names
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Interconnections
An Alternative format of port connection The actual ports of the instantiated components are excluded
ALU8 U1 ( Inbus, ABinput, function, Outbus ); Inbus, ABinput, Mux8 U2 ( select_source, Aside, Bside, ABinput ); select_source, Bside, Ordered Port Connection
The list of local signals in the same order as their connecting ports
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Controllers
Data Components
Controllers Controllers
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Controllers
Decisions Based on :Inputs , Outputs ,State
Issue Control Signal
Set Next State
Go to Next State
Controller Outline
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Controllers
Controller: Is wired into data part to control its flow of data. The inputs to it controller determine its next states and outputs. Monitors its inputs and makes decisions as to when and what output signals to assert. Keeps the history of circuit data by switching to appropriate states. Two examples to illustrate the features of Verilog for describing state machines: Synchronizer Sequence Detector
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Controllers
Controllers
Synchronizer
Sequence Detector
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Synchronizer
Controllers
Synthesizer Synchronizer
Sequence Detector
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Synchronizer
Clk
adata synched
Synchronizing adata
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Synchronizer
`timescale 1ns/100ps module Synchronizer (input clk, adata, (input clk, adata, output reg synched); always @(posedge clk) @(posedge clk) if (adata == 0) synched <= 0; (adata If a 1 is Detected on adata on the rising else synched <= 1; edge of clock, synched endmodule A Simple Synchronization Circuit
becomes 1 and remains 1 for at least one clock period
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Sequence Detector
Controllers
Synthesizer
Sequence Sequence Detector Detector
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Sequence Detector
Searches on its a input it for the 110 Sequence When the sequence is detected, the w Output becomes 1 and stays 1 for a complete clock cycle
If 110 is detected on a, then w gets 1, else w gets 0.
clk
State Machine Description
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Sequence Detector
A Moore Machine Sequence Detector States are named: s0 , s1 , s2 , s3
reset 0 1 S0 0 0 S1 0 1 1 S2 0 1 0 S3 1
The State in which the 110 sequence is detected.
Initial State
Sequence Detector State Machine
It Takes at least 3 clock periods to get to the s3 state
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Sequence Detector
module Detector110 (input a, clk, reset, output w); (input clk, parameter [1:0] s0=2'b00, s1=2'b01, s2=2'b10, s3=2'b11; reg [1:0] current; always @(posedge clk) begin @(posedge clk) if (reset) current = s0; else case (current) s0: if (a) current <= s1: if (a) current <= s2: if (a) current <= s3: if (a) current <= endcase end
s1; s2; s2; s1;
else else else else
current current current current
<= <= <= <=
s0; s0; s3; s0;
assign w = (current == s3) ? 1 : 0; endmodule
Verilog Code for 110 Detector

Behavioral Sequence Detector Description of the State Machine
module Detector110 (input a, clk, reset, output w); (input clk, parameter [1:0] s0=2'b00, s1=2'b01, s2=2'b10, s3=2'b11; reg [1:0] current;
A 2-bit Register Parameter declaration defines constants s0, s1, s2, s3 s0, s1, s2,
always @(posedge clk) begin @(posedge clk) if (reset) current = s0; else ........................... ........................... Verilog Code for 110 Detector
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Sequence Detector
........................... ........................... always @(posedge clk) begin @(posedge clk) if (reset) current = s0; else case (current) At the s0: if (a) current <= s1; Absence of a 1 on reset s1: if (a) current <= s2; s2: if (a) current <= s2; s3: if (a) current <= s1; endcase end Verilog Code for 110 Detector
if-else statement checks for reset
else else else else
current current current current
<= <= <= <=
s0; s0; s3; s0;
The 4 Case-alternatives each correspond to a state of state machine
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Sequence Detector
s1 0 a=1 s2 0 a=0 s0 0 s1: if (a) current <= s2; else current <= s0;
State Transitions on Corresponding Verilog Code

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Sequence Detector
end ............................ ............................ assign w = (current == s3) ? 1 : 0; endmodule Verilog Code for 110 Detector
Outside of the always Block: A combinational circuit
Assigns a 1 to w output when Machine Reaches to s3 State
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Testbenches
Testbenches
A Simple Tester
Tasks And Functions
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A Simple Tester
Testbenches
A Simple Tester
Tasks And Functions
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A Simple Tester
`timescale 1ns/100ps module Detector110Tester; reg aa, clock, rst; aa, rst; wire ww; ww; Detector110 UUT (aa, clock, rst, ww); (aa, rst, ww); initial begin aa = 0; clock = 0; rst = 1; end initial repeat (44) #7 clock = ~clock; initial repeat (15) #23 aa = ~aa; ~aa; initial begin #31 rst = 1; #23 rst = 0; end always @(ww) if (ww == 1) @(ww) (ww $display ("A 1 was detected on w at time = %t", $time); $time); endmodule
Testbench for Detector110

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A Simple Tester
Begins with the module keyword
`timescale 1ns/100ps
Unlike other descriptions doesnt have input doesn or output ports
module Detector110Tester; Outputs reg aa, clock, rst; are aa, rst; Inputs are Declared as reg declared as wire wire ww; ww; Detector110 UUT (aa, clock, rst, ww); (aa, rst, ww); ......................... ......................... Instantiation of The
Detector110 Module
Testbench for Detector110
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initial statement drives test values into the variables connected to the inputs.
A Simple Tester
An initial statement: A sequential statement that runs once and stops when it reaches its last statement
.......................... .......................... initial begin aa = 0; clock = 0; rst = 1; end initial repeat (44) #7 clock = ~clock; initial repeat (15) #23 aa = ~aa; ~aa; initial begin #31 rst = 1; #23 rst = 0; end Testbench for Detector110
All Initial Blocks Start at Time 0 and Run Concurrently
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A Simple Tester
Repeats 44 times of complementing the .......................... For Initializing input with 7ns clock .......................... the Input Signals delay, generates a initial begin periodic signal aa = 0; clock = 0; rst = 1; on clock end initial repeat (44) #7 clock = ~clock; initial repeat (15) #23 aa = ~aa; ~aa; initial begin Signal aa is also #31 rst = 1; assigned a periodic #23 rst = 0; signal, with a end
Testbench for Detector110 Waits 31 ns before

assigning 1 to rst
different frequency
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A Simple Tester
Reports the Times at which .......................... the ww Variable .......................... becomes 1 always Block Wakes up when ww Changes
always @(ww) if (ww == 1) @(ww) (ww $display ("A 1 was detected on w at time = %t", $time); $time); endmodule Testbench for Detector110
A Verilog System Task This Note Will Appear in the Simulation Environments Environment Window: Console or Console Transcript Transcript
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Tasks And Functions

Testbenches
A Simple Tester
Tasks And Functions
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Tasks And Functions
Verilog Tasks and Functions: System tasks for Input, Output, Display, and Timing Checks User defined tasks and functions Tasks: Can represent a sub module within a Verilog module Begins with a task keyword Its body can only consist of sequential statements like if-else and case Functions: Can be used for corresponding to hardware entities May be used for writing structured codes Applications: Representation of Boolean functions, data and code conversion, and input and output formatting
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Funky parallelism
Hardware
is inherently parallel
FPGA = Fine-grained massively parallel computer Verilog = Funky parallel programming language
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Verilog tips and traps
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Constants: 32 bits, decimal

wire [7:0] foo = 127; // synthesis warning! wire [7:0] foo = 8d127; 8 wire [7:0] foo = 8b11111111; 8 wire [7:0] foo = 8hff; 8 wire [7:0] foo = 8hFF; 8 watch out: 1010 looks like 4b1010! 4
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Truncation

wire [7:0] a = 8hAB; 8 wire b; // oops! forgot width wire [7:0] c; assign b = a; // synthesis warning if lucky. assign c = a;
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reg vs. wire

wire f; reg g, h; assign f = a & b; always @(posedge clk) @(posedge clk) g <= a & b; always @(*) h = a & b;
(blocking)
= vs. <= (non-blocking)
Simple rule:
If you want sequential logic, use always @(posedge clk) with <=. (non-blocking) @(posedge clk) If you want combinational logic, use always @(*) with =. (blocking)
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(blocking)
begin f <= a + b; g <= f + c; end
= vs. <= (non-blocking)

always@(posedge clk) always@(posedge clk)
begin f2 <= f1; f3 <= f2; f4 = f3; f5 = f4; // f5 = f3 !! f7 = f6; f6 = f5; end
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always @(posedge clk) @(posedge clk)
always @(posedge clk) @(posedge clk)

begin f = a + b; g = f + c; // a + b + c end
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Verilog Stratified Event Queue [1]
Region 1: Active Events

Most events except those explicitly in other regions Includes $display system tasks Processed after all active events #0 delay events (bad!) (bad!) Evaluation previously performed Update is after all active and inactive events complete Caused by $monitor and $strobe system tasks Occurs at some future simulation time Includes future events of other regions Other regions only contain events for CURRENT simulation time
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Region 2: Inactive Events

Region 3: Non-blocking Assign Update Events

Region 4: Monitor Events
Region 5: Future Events

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Verilog Stratified Event Queue [2]
within a block, blocking assignments, are in order
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Incomplete sensitivity lists
always @(a or b) // its or, not || it f = a & b; always @(a) f = a & b; always f = a & b; Just use always@(*) for combinational logic
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Blocking and non-blocking assignments
Blocking assignments (Q = A)

Variable is assigned immediately New value is used by subsequent statements Variable is assigned after all scheduled statements are executed Value to be assigned is computed but saved for later
Non-blocking assignments (Q <= A)

Example: Swap
always @(posedge CLK) begin temp = B; B = A; A = temp; end always @(posedge CLK) begin A <= B; B <= A; end
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Blocking and non-blocking assignments

reg B, C, D; always @(posedge clk) begin B = A; C = B; D = C; end reg B, C, D; always @(posedge clk) begin B <= A; C <= B; D <= C; end
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Swap
The following code executes incorrectly

One block executes first Loses previous value of variable

always @(posedge CLK) begin A = B; end always @(posedge CLK) begin B = A; end
Non-blocking assignment fixes this
Both blocks are scheduled by posedge CLK

always @(posedge CLK) begin A <= B; end always @(posedge CLK) begin B <= A; end
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Parallel versus serial execution
assign statements are implicitly parallel

= means continuous assignment Example

assign E = A & D; assign A = B & C;
B C
A and E change if B changes always @(posedge clock) @(posedge = is a blocking assignment (sequential) <= is a nonblocking assignment (parallel) <= Examples of procedures: always, function, etc. always, function,
E D
always blocks execute in parallel
Procedural block internals not necessarily parallel

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04 RTL Design

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04 RTL Design

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Register Transfer Level Design with Verilog

Adapted from Z. Navabi

Verilog Digital System Design

Register Transfer Level Design with Verilog

Verilog Digital System Design

Register Transfer Level Design with Verilog

Verilog Digital System Design

Verilog Digital System Design

Verilog Digital System Design

Verilog Digital System Design

Opcode Data flow Control signals

Verilog Digital System Design

Data Part Data Part

Verilog Digital System Design

Opcode Data flow Control signals

Verilog Digital System Design

and routing of data from one data component to another

Verilog Digital System Design

Control Part Control Part

Verilog Digital System Design

Verilog Digital System Design

We discuss basic constructs of Verilog language for describing a hardware module.

Verilog Digital System Design

Verilog Digital System Design

Verilog Digital System Design

A Multiplexer Using Basic Logic Gates

Verilog Digital System Design

Verilog Digital System Design

Verilog Digital System Design

Verilog Digital System Design

too complex to be described by Boolean or conditional expressions

Verilog Digital System Design

Module Module Instantiations

Verilog Digital System Design

Multiplexer Using ANDOR

Component Description in Verilog

Verilog Digital System Design

Data Data Components Components

Verilog Digital System Design

Flip-Flop Full-Adder ALU

Flip-Flop Full-Adder ALU

Verilog Digital System Design

Flip-Flop Full-Adder ALU

Verilog Digital System Design

Flip-Flop Full-Adder ALU

A 4-bit modulo-16 Counter

Verilog Digital System Design

Flip-Flop Full-Adder ALU

Verilog Digital System Design

Flip-Flop Full-Adder ALU

2 Mode inputs m[1:0] form a `timescale 1ns/100ps 2-bit number

An 8-bit Universal Shift Register

and default Value

Shift Right: The SL input is concatenated to the left of ParOut

Flip-Flop Full-Adder ALU ALU

ALU (Continued) The Declaration of

Flip-Flop Full-Adder ALU

Mux8 and ALU examples forming a Partial Hardware

Partial Hardware Using MUX8 and ALU

Verilog Digital System Design

Verilog Digital System Design

Verilog Digital System Design

Issue Control Signal