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Lecture 060 – Push-Pull Output Stages (1/11/04) Page 060-1 LECTURE 060 – PUSH-PULL OUTPUT STAGES
Lecture 060 – Push-Pull Output Stages (1/11/04)
Page 060-1
LECTURE 060 – PUSH-PULL OUTPUT STAGES
(READING: GHLM – 362-384, AH – 226-229)
Objective
The objective of this presentation is:
Show how to design stages that
1.) Provide sufficient output power in the form of voltage or current.
2.) Avoid signal distortion.
3.) Be efficient
4.) Provide protection from abnormal conditions (short circuit, over temperature, etc.)
Outline
• Push-Pull MOS (Class B)
• Push-Pull BJT (Class B)
• Summary
ECE 6412 - Analog Integrated Circuits and Systems II
© P.E. Allen - 2002
Lecture 060 – Push-Pull Output Stages (1/11/04)
Page 060-2
PUSH-PULL MOS OUTPUT STAGES (Class AB and B)
Push-Pull Source Follower
Can both sink and source
V
V
DD
DD
V
DD
M6
M1
current and provide a slightly
lower output resistance.
V
GG
M5
M1
V
SS
V
V
Bias
SS
i
V
OUT
v
i
SS
IN
OUT
v
OUT
V
v
Bias
OUT
V
V
R
DD
M4
M2
DD
R
L
L
V
M2
DD
Efficiency:
v
IN
M3
Depends on how the
transistors are biased.
V SS
Fig. 060-01
V SS
V SS
• Class B - one transistor has current flow for only 180° of the sinusoid (half period)
v
OUT (peak) 2
P
2R L
v
OUT (peak)
RL
π
∴ Efficiency =
=
2v OUT (peak)
P VDD =
1
2
V DD -V SS
(V DD -V SS )
2
πR L
 
Maximum efficiency occurs when v OUT (peak) =V DD and is 78.5%
Class AB - each transistor has current flow for more than 180° of the sinusoid.
Maximum efficiency is between 25% and 78.5%
ECE 6412 - Analog Integrated Circuits and Systems II
© P.E. Allen - 2002
Lecture 060 – Push-Pull Output Stages (1/11/04) Page 060-3 Illustration of Class B and Class
Lecture 060 – Push-Pull Output Stages (1/11/04)
Page 060-3
Illustration of Class B and Class AB Push-Pull, Source Follower
Output current and voltage characteristics of the push-pull, source follower (R L = 1kΩ):
2V
1mA
2V
1mA
v
G1
v G1
i
D1
i
D1
1V
1V
0V
0mA
0V
0mA
v
v
out
G2
v
v
out
G2
-1V
-1V
i
D2
i D2
-2V
-1mA
-2V
-1mA
-2
-1
0
1
2
-2
-1
0
1
2
V
in (V)
V
in (V)
Class B, push-pull, source follower
Class AB, push-pull, source follower
Fig. 060-02
Comments:
• Note that v OUT cannot reach the extreme values of V DD and V SS
• I OUT + (max) and I OUT - (max) is always less than V DD /R L or V SS /R L
• For v OUT = 0V, there is quiescent current flowing in M1 and M2 for Class AB
• Note that there is significant distortion at v IN =0V for the Class B push-pull follower
ECE 6412 - Analog Integrated Circuits and Systems II
© P.E. Allen - 2002
Lecture 060 – Push-Pull Output Stages (1/11/04)
Page 060-4
Small-Signal Performance of the Push-Pull Follower
Model:
v
gs1
+
-
+
+
C
1
v
in
r
v
ds1
r ds2
R L
C
out
2
g
g
m1 v gs1
g mbs1 v bs1
mbs2 v bs2
-
g m2 v gs2
-
v
gs1
+
-
+
+
C
1
1
v
in
R
v
L
C
out
g
2
m2
g
g
g
r
g
g
m1 v in
g
r
m1 v out
mbs1 v out
ds1
m2 v
in
m2 v out
-
mbs2 v out
ds2
-
Fig. 060-03
v
out
g m1 + g m2
=
g
v in
ds1 +g ds2 +g m1 +g mbs1 +g m2 +g mbs2 +G L
1
R
out =
g ds1 +g ds2 +g m1 +g mbs1 +g m2 +g mbs2 (does not include R L )
If
V DD = -V SS = 2.5V, V out = 0V, I D1 = I D2 = 500µA, and W/L = 20µm/2µm, A v = 0.787
(R L =∞) and R out = 448Ω.
A
zero and pole are located at
= -(g m1 +g m2 )
-(g ds1 +g ds2 +g m1 +g mbs1 +g m2 +g mbs2 +G L )
z
p =
.
C 1
C 1 +C 2
These roots will be high-frequency because the associated resistances are small.
ECE 6412 - Analog Integrated Circuits and Systems II
© P.E. Allen - 2002
Lecture 060 – Push-Pull Output Stages (1/11/04) Page 060-5 Push-Pull, Common Source Amplifiers Similar to
Lecture 060 – Push-Pull Output Stages (1/11/04)
Page 060-5
Push-Pull, Common Source Amplifiers
Similar to the class A but can operate as class B providing higher efficiency.
V
DD
M2
V
TR2
i
OUT
v
v
IN
OUT
V
TR1
M1
C L
R L
V
SS
Fig. 060-04
Comments:
• The batteries V TR 1 and V TR 2 are necessary to control the bias current in M1 and M2.
• The efficiency is the same as the push-pull, source follower.
ECE 6412 - Analog Integrated Circuits and Systems II
© P.E. Allen - 2002
Lecture 060 – Push-Pull Output Stages (1/11/04)
Page 060-6
Practical Implementation of the Push-Pull, Common Source Amplifier – Method 1
V
DD
M5
M6
M1 M3
V
GG3
i
OUT
v
v
IN
OUT
M2 M4
V
GG4
C L
R L
M7
M8
V
Fig. 060-05
SS
V GG3 and V GG4 can be used to bias this amplifier in class AB or class B operation.
Note, that the bias current in M6 and M8 is not dependent upon V DD or V SS (assuming
V GG 3 and V GG 4 are not dependent on V DD and V SS ).
ECE 6412 - Analog Integrated Circuits and Systems II
© P.E. Allen - 2002
Lecture 060 – Push-Pull Output Stages (1/11/04) Page 060-7 Practical Implementation of the Push-Pull, Common
Lecture 060 – Push-Pull Output Stages (1/11/04)
Page 060-7
Practical Implementation of the Push-Pull, Common Source Amplifier – Method 2
V
DD
M5
I=2I b
I
M7
b
v
+
in
M1
M8
M3 M4
M9
v
in -
M2
M6
I=2I b
I
M10
b
V
SS
Fig. 060-055
In steady-state, the current through M5 and M6 is 2I b . If W 4 /L 4 = W 9 /L 9 and W 3 /L 3 =
W 8 /L 8 , then the currents in M1 and M2 can be determined by the following relationship:
 W 1 /L 1
 
W
2 /L 2
I 1 = I 2 = I b
  W 7 /L 7
  = I b
W 10 /L 10
If v in + goes low, M5 pulls the gates of M1 and M2 high.
M4 shuts off causing all of the
current flowing through M5 (2I b ) to flow through M3 shutting off M1. The gate of M2 is
high allowing the buffer to strongly sink current. If v in - goes high, M6 pulls the gates of
M1 and M2 low. As before, this shuts off M2 and turns on M1 allowing strong sourcing.
ECE 6412 - Analog Integrated Circuits and Systems II
© P.E. Allen - 2002
Lecture 060 – Push-Pull Output Stages (1/11/04)
Page 060-8
Illustration of Class B and Class AB Push-Pull, Inverting Amplifier
Output current and voltage characteristics of the push-pull, inverting amplifier (R L =
1kΩ):
v
G2
2V
2mA
2V
2mA
v
G2
i
D1
v
v
G1
G1
1V
1mA
1V
1mA
i
i
D2
i
D1
D1
i
D1
0V
0mA
0V
0mA
i
i
D2
D2
-1V
-1mA
-1V
-1mA
i
v
v
D2
OUT
OUT
-2V
-2mA
-2V
-2mA
-2V
-1V
0V
1V
2V
-2V
-1V
0V
1V
2V
v
v
IN
IN
Class B, push-pull, inverting amplifier.
Class AB, push-pull, inverting amplifier.
Fig.060-06
Comments:
• Note that there is significant distortion at v IN =0V for the Class B inverter
• Note that v OUT cannot reach the extreme values of V DD and V SS
• I OUT + (max) and I OUT - (max) is always less than V DD /R L or V SS /R L
• For v OUT = 0V, there is quiescent current flowing in M1 and M2 for Class AB
ECE 6412 - Analog Integrated Circuits and Systems II
© P.E. Allen - 2002
Lecture 060 – Push-Pull Output Stages (1/11/04) Page 060-9 Use of Negative, Shunt Feedback to
Lecture 060 – Push-Pull Output Stages (1/11/04)
Page 060-9
Use of Negative, Shunt Feedback to Reduce the Output Resistance
Concept:
V
DD
M2
Error
Amplifier
-
+
i
OUT
v
v
IN
OUT
-
+
Error
Amplifier
C L
R L
M1
Fig. 060-07
V
SS
r
ds 1 ||r ds 2
R out =
1+Loop Gain
Comments:
• Can achieve output resistances as low as 10Ω.
• If the error amplifiers are not balanced, it is difficult to control the quiescent current in
M1 and M2
• Great linearity because of the strong feedback
• Can be efficient if operated in class B or class AB
ECE 6412 - Analog Integrated Circuits and Systems II
© P.E. Allen - 2002
Lecture 060 – Push-Pull Output Stages (1/11/04)
Page 060-10
Simple Implementation of Neg., Shunt Feedback to Reduce the Output Resistance
V
DD
M2
i
R 1
R 2
OUT
v
v
IN
OUT
C L
R L
M1
Fig. 060-08
V
SS
R
g
1
m1 +g m2
Loop gain ≈
R
1 +R
g
2
ds1 +g ds2 +G L˚
r
ds
1 ||r ds 2
R out =
R
g
1
m1 +g m2
1+
R
g
1 +R 2
ds1 +g ds2 +G L
Let R 1 = R 2 , R L = ∞, I Bias = 500µA, W 1 /L 1 = 100µm/1µm and W 2 /L 2 = 200µm/1µm.
Thus, g m1 = 3.316mS, g m2 = 3.162mS, r ds1 = 50kΩ and r ds2 = 40kΩ.
50kΩ||40kΩ
22.22kΩ
(R out = 5.42kΩ if R L = 1kΩ)
R out =
 3316+3162
= 1+0.5(143.9) = 304Ω
1+0.5
 25+20
ECE 6412 - Analog Integrated Circuits and Systems II
© P.E. Allen - 2002
Lecture 060 – Push-Pull Output Stages (1/11/04) Page 060-11 What about the use of BJTs
Lecture 060 – Push-Pull Output Stages (1/11/04)
Page 060-11
What about the use of BJTs in CMOS Technology?
V
V
V
DD
DD
DD
M3
Q1
M2
i
v
v
B
out
out
i
B
M2
Q1
C
M3
C
L
L
V
SS
V
V
SS
SS
p-well CMOS
n-well CMOS
Fig. 060-09
Comments:
• Can use either substrate or lateral BJTs.
• Small-signal output resistance is 1/g m which can easily be less than 100Ω.
• Unfortunately, only PNP or NPN BJTs are available but not both on a standard CMOS
technology.
• In order for the BJT to sink (or source) large currents, the base current, i B , must be
large. Providing large currents as the voltage gets to extreme values is difficult for
MOSFET circuits to accomplish.
• If one considers the MOSFET driver, the emitter can only pull to within v BE +V ON of the
power supply rails. This value can be 1V or more.
ECE 6412 - Analog Integrated Circuits and Systems II
© P.E. Allen - 2002
Lecture 060 – Push-Pull Output Stages (1/11/04)
Page 060-12
PUSH-PULL BJT OUTPUT STAGES (Class AB and B)
Simple Class B Output Stage
v
OUT
V
CC
Q1 Saturates
V
CC -V BE1
Q1
Slope ≈ 1
Q1 on
Q2 off
V
BE (on)
V
BE (on)
+
V
EE +V BE2 +V CE1 (sat)
R
v
L
v
IN
v
IN
Q2
OUT
V
CC +V BE1 -V CE1 (sat)
-
V
EE
Slope ≈ 1
Q1 off
Q2 on
Q2 Saturates
V
Fig. 060-10
EE +V BE2
Class B operation: Two active devices are used to deliver the power instead of one. Each
device conducts for alternate half cycles.
Efficiency can approach 78.5%
Can suffer from crossover distortion - the transition from one device to the other.
ECE 6412 - Analog Integrated Circuits and Systems II
© P.E. Allen - 2002
Lecture 060 – Push-Pull Output Stages (1/11/04) Page 060-13 Class AB Output Stage v OUT
Lecture 060 – Push-Pull Output Stages (1/11/04)
Page 060-13
Class AB Output Stage
v
OUT
Q1 Saturates
V
CC -V BE1
V
CC
V
CC
I
Q
Q1
Slope ≈ 1
Q3
v
IN
Q4
+
R
L
v
V
BE (on)
Q2
OUT
-
v
IN
V
EE
Q2 Saturates
V
Fig. 060-11
EE +V EB2
I Q sets up the bias current in Q1 and Q2 when there is no input signal.
Each transistor is biased so that there is a region in the middle where both are on (Class
AB)
ECE 6412 - Analog Integrated Circuits and Systems II
© P.E. Allen - 2002
Lecture 060 – Push-Pull Output Stages (1/11/04)
Page 060-14
Power Considerations in the Class B Output Stage
Voltage and current waveforms for a Class B amplifier:
v
in
2T
t
V
T
CC
V
CC
Q1
v
I
out
Q
i
c1
V
out (peak)
Q3
Q4
+
2T
t
T
R
v
L
out
i
c2
Q2
-
v
in
i
c1
V
I
c1 (peak)
EE
2T
t
T
i
c2
2T
t
T
I
c2 (peak)
Fig. 060-12
ECE 6412 - Analog Integrated Circuits and Systems II
© P.E. Allen - 2002
Lecture 060 – Push-Pull Output Stages (1/11/04) Page 060-15 Efficiency Considerations of the Class-B Push-Pull
Lecture 060 – Push-Pull Output Stages (1/11/04)
Page 060-15
Efficiency Considerations of the Class-B Push-Pull Output Stage
Load line for one device in a class-B stage:
i
C1
Load Line
V
CC
R
L
Peak device
dissipation
Constant Power Curve
V
CE1 (sat)
Load Line
Quiescent Point
v
CE1
0.5V CC
2V CC -V CE1 (sat)
0 0
V
CC
Fig. 060-13
Efficiency:
1
[V
out (peak)] 2
P L =
2
R
L
T
1
I
c (peak)
2
V
and
i
C (t)dt
 2V CC 
CC
=
=
V out (peak)
P supply = 2V CC I supply = 2V CC
T
π
π
R L
0
P
π
V
out (peak)
L
π
η =
= 78.6%
4
η max =
4
P supply =
V CC
π
V CC -V CE (sat)
Max. efficiency for the above class-B push-pull output stage is η max =
4
V
CC
ECE 6412 - Analog Integrated Circuits and Systems II
© P.E. Allen - 2002
Lecture 060 – Push-Pull Output Stages (1/11/04)
Page 060-16
709 Output Stage
4
V
CC
10
V
CC
R L = 10kΩ
I
Q
5
Q1
2
3
+
0
Q2 R L
v
R L = 1kΩ
1
OUT
Q3
-
v
-5
IN
V
5
EE
-10
Fig. 060-14
0.6
0.61
0.62
0.63
0.64
0.65
0.66
0.67
v
IN
709 Output Stage Voltage Transfer Function
.MODEL BJTN NPN IS=1E-14 BF=100 VAF=50
.MODEL BJTP PNP IS=1E-14 BF=50 VAF=50
Q1 4 3 2 BJTN
Q2 5 3 2 BJTP
Q3 3 1 5 BJTN
VCC 4 0 DC 10V
VEE 5 0 DC -10V
VIN 1 5
RL 2 0 1KILOHM
R1 4 3 20KILOHM
.DC VIN 0.60 0.67 0.001
.PRINT DC V(2)
.PROBE
.END
This stage assumes that feedback will be used around the amplifier which will linearize
the nonlinearity of the output stage.
ECE 6412 - Analog Integrated Circuits and Systems II
© P.E. Allen - 2002
v
OUT
Lecture 060 – Push-Pull Output Stages (1/11/04) Page 060-17 741 Output Stage 7 V CC
Lecture 060 – Push-Pull Output Stages (1/11/04)
Page 060-17
741 Output Stage
7
V
CC
15
Q13B
6
Q13C
Q13A
5
10
Q14
Q19
5
0.22mA
2
4
Q18
R
+
10 =
0
R
40kΩ
L
v
OUT
3
Q20
-
-5
1
Q23
9
Q17
-10
v
IN
-15
8
V
Fig. 060-15
EE
0.62
0.63
0.64
0.65
0.66
0.67
v
IN
741 Output Stage Voltage Transfer Function - RL =
1Kilohm
.MODEL BJTN NPN IS=1E-14 BF=100 VAF=50
.MODEL BJTP PNP IS=1E-14 BF=50 VAF=50
Q23 8 1 3 BJTP
Q20 8 3 2 BJTP
Q14 7 5 2 BJTN
Q17 1 9 8 BJTN
Q18 5 4 3 BJTN
Q19 5 5 4 BJTN
Q13A 5 6 7 BJTP
Q13B 1 6 7 BJTP 3.0
Q13C 6 6 7 BJTP
VCC 7 0 DC 15V
VEE 8 0 DC -15V
IBIAS 6 0 220UA
VIN 9 8 DC 0.645
R10 4 3 40KILOHM
RL 2 0 1KILOHM
.DC VIN 0.625 0.665 0.0005
.PRINT DC V(2)
.PROBE
.END
ECE 6412 - Analog Integrated Circuits and Systems II
© P.E. Allen - 2002
Lecture 060 – Push-Pull Output Stages (1/11/04)
Page 060-18
Quasi-Complementary Output Stages
Quasi-complementary connections are used to improve the performance of the PNP or
PMOS transistor.
Composite connections:
E
E
S
S
+
I
+
V
E
+
+
EB
V
I
SG
E
V
V
EB
SG
B
-
-
-
-
Q1
B
G
M1
G
I
C1
I
D1
Q2
I
Q2
I
C
D
I
C
D
C
I
D
C
D
Fig. 060-16
PNP Equivalent:
PMOS Equivalent:
V
EB
K
’W 1
P
I C = (1+β 2 ) I C1 = (1+β 2 ) I s exp
I D = (1+β 2 ) I D1 = (1+β 2 )
(V
V
2L 1
GS -V T ) 2
t
The composite has the beta of an
∴ The composite has an enhanced K’
NPN
ECE 6412 - Analog Integrated Circuits and Systems II
© P.E. Allen - 2002
v
OUT
Lecture 060 – Push-Pull Output Stages (1/11/04) Page 060-19 Overload Protection For circuits that can
Lecture 060 – Push-Pull Output Stages (1/11/04)
Page 060-19
Overload Protection
For circuits that can provide large amounts of output current, it is necessary to provide
short-circuit current protection.
Example:
i
OUT
V
CC
R Lim = 0
i
i
B1
C1
Q1
i
C2
R Lim ≠ 0
i
i
Q2
I
Lim
R
Lim
i
OUT
Short-Circuit
Fig. 060-17
i
i
0 0
i OUT = i C1 +i C2 ≈ i C1
i OUT = β 1 i B1 = β 1 (i i -i C2 )
v
BE2
i
C1 R Lim
But i C2 ≈ I s2 exp
≈ I s2 exp
 V t
V t
i
C1 R Lim
i OUT = β 1 i i - I s2 exp
V t
As i OUT increases, Q2 turns on and pulls base current away from Q1 limiting the output
current.
ECE 6412 - Analog Integrated Circuits and Systems II
© P.E. Allen - 2002
Lecture 060 – Push-Pull Output Stages (1/11/04)
Page 060-20
SUMMARY
Requirements of Output Stages
• The objectives are to provide output power in form of voltage and/or current.
• In addition, the output amplifier should be linear and be efficient.
• Low output resistance is required to provide power efficiently to a small load resistance.
• High source/sink currents are required to provide sufficient output voltage rate due to
large load capacitances.
• Types of output stages considered:
Class B or AB stage with push-pull (maximum efficiency was 78.6%)
• Quasi-complementary devices help improve the performance of the p-type devices
• Protection circuits prevent large currents from flowing in the output devices
• For large load capacitors all that is required from an output stage is large current, the
output resistance does not have to be small
ECE 6412 - Analog Integrated Circuits and Systems II
© P.E. Allen - 2002