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Department of Computer Science and Engineering, IIT Madras MS/PhD Entrance Test - November 2008 Exam duration is one hour. Each question is worth two marks. There are 25 questions. Part I - Digital Logic and Computer Organization 1. The rst expedition to Mars found only the ruins of a civilization. From the artifacts and pictures, the explorers deduced that the creatures who produced this civilization were fourlegged beings with a tentacle that branched out at the end with a number of grasping ngers. After much study, the explorers were able to translate Martian mathematics. They found the following equation: 5x2 50x + 125 = 0 with the indicated solutions x = 5 and x = 8. The value x = 5 seemed legitimate enough, but x = 8 required some explanation. Then the explorers reected on the way in which Earths number system developed, and found evidence that the Martian system had a similar history. How many ngers would you say the Martians had? (a) 10 (b) 13 (c) 40 (d) 25 2. Let a function F be self-dual if F = F D , where F D is the dual of function F . How many self-dual logic functions of n variables are there? (a) 2n (b) 2n (c) 22 (d) 22
n1 n

3. Let x and y be Boolean variables. If xy = 0, then which of the following statements is correct: (a) x = y (b) x y = x + y (c) x y = x (d) x y = y 4. Which of the following expressions represents the minimal expression for ABC + AB + A ? (a) (ABC) (b) A + C (c) A B C (d) AB + AC + BC 5. To transmit data bits 1101, the correct even parity seven bit Hamming Code is

Your name: (a) 1100110 (b) 1101101 (c) 0101101 (d) 1100010

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6. The instruction M OV AX, [BX][DI] + 2 represents the following addressing mode: (a) register indirect (b) index relative (c) base relative (d) base indexed 7. Part of the operating system is usually stored in ROM so that it can be used to boot up the computer. ROM is used instead of RAM because (a) RAM is not big enough to store operating systems (b) ROM is faster than RAM (c) ROM is non-volatile (d) ROM is cheaper than RAM 8. A given memory chip has 16 address pins and 10 data pins. It has the following number of memory locations: (a) 210 (b) 216 (c) 226 (d) 232 9. Suppose that a bus has 32 data lines and requires 4 cycles of 250ns each to transfer data. The bandwidth of the bus would be 2M B/s. If the cycle time of the bus is reduced to 125ns and the number of cycles required to transfer stayed the same, what would be the bandwidth of the bus? (a) 1M B/s (b) 0.5M B/s (c) 4M B/s (d) Bandwidth does not depend on the cycle time 10. Which of the following statements is wrong: (a) Conict miss rate is less for 4-way set-associative cache as compared to the same sized 2-way set-associative cache. (b) Capacity miss rate increases with reducing cache size. (c) Cold miss rate is high for direct mapped caches as compared to the same sized setassociative caches (keeping the block size constant). (d) Working set can determine cache miss rate.

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11. What is the precision with which the numbers having a true exponent of 25 are represented in IEEE standard 754 single precision oating point format? (a) 22 (b) 22 (c) 223 (d) 225 12. Consider a 2-way set-associative cache with a word legnth of 4 bytes, a block size of 8 words, and a capacity of 128KB. What are the lengths of TAG, SET and WORD elds for the 30-bit physical address of a word to be accessed by the cache? (a) 20 bits, 7 bits, 3 bits (b) 18 bits, 9 bits, 3 bits (c) 16 bits, 11 bits, 3 bits (d) 14 bits, 13 bits, 3 bits 13. Which of the following statemments is true for a processor with load-store architecture? (a) Only the LOAD and STORE instructions can be executed by the processor (b) All the instructions can refer to a memory operand (c) An arithmetic instruction can refer to only one memory operand (d) Only the LOAD and STORE instructions can refer to a memory operand 14. The target throughput of a 5-stage pipelined processor is (a) 5 instructions per clock cycle (b) 1 instruction per clock cycle (c) 1 instruction per 5 clock cycles (d) None of the above 15. Which of the following statements is false for a microprogrammed control unit? (a) Each machine instruction is a sequence of microinstructions (b) Each microinstruction is a set of control words (c) Each control word is a set of active control signals (d) None of the above 16. The basic cells used to build the main memory unit and cache memory unit respectively are (a) SRAM, SRAM (b) SRAM, DRAM (c) DRAM, SRAM (d) DRAM, DRAM Part II - Programming and Mathematical Foundations 17. Consider the following structure in C and the function GetRollNumberName:

Your name: typedef struct { char *firstName; char *lastName; char *rollNumber; }STUDENT;

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void GetRollNumberName (STUDENT s) { scanf ("%s %s %s", s.rollNumber, s.firstName, s.lastName); } /* End of GetRollNumberName End of GetRollNumberName */

The function is supposed to read the values of firstName, lastName, rollNumber and store the same in the structure s and return the same to the calling program. Does the function work as expected? If not, correct it.

18. Assume that array is an array of n integers. What is the output of the following function: void DoSomething(int *array, int n) { int i = 0; int j, tmp; while (i < n) { while (array[i] == 0) i++; j = i + 1; if (array[j] == 0) { tmp = array[j]; array[j] = array[i]; array[i] = tmp; i++; } else

Your name: j++; } }

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19. Write the recurrence equation for computing the GCD of two numbers.

20. How would you choose the pivot element to ensure that Quicksort has an average running time of O(nlogn)?

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21. Evalute the following recurrence equation:

T(1) = O(1) T(n) = T(n/2) + O(1)

22. Show that k(k + 1)/2 l(l + 1)/2 is not divisible by m = 2n for any k, l {0..m 1} if k = l.

23. Given that P r[Xi > 2lgn] 1/n2 for each of a set of random variables {Xi , i = 1 . . . n}. Show that if X = max1in Xi , then P r[X > 2lgn] 1/n.

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24. Show that for Harmonic numbers dened by the equation: HN =

1kN

1 k

the following identity is true: Hk = (N + 1)(HN +1 1)

1kN

25. The set of all subsets of is an uncountable set. Is this statement true or false? Dene a countable set.

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