MANCHEstER

1824
The University of Manchester

Coprocessors

t Outline: r the ARM coprocessor interface r oating-point support r MOVE coprocessor r CP15, CP14

 hands-on: system software - semaphores

2005 PEVEIT Unit ARM System Design

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MANCHEstER
1824
The University of Manchester

Coprocessors

t Outline: the ARM coprocessor interface r oating-point support r MOVE coprocessor r CP15, CP14

 hands-on: system software - semaphores

2005 PEVEIT Unit ARM System Design

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MANCHEstER
1824
The University of Manchester

Coprocessors

t ARM supports a generic extension of its instruction set

through coprocessors
r coprocessors have:
private registers and data types their own interpretation of instructions

r Example coprocessors:
hardware oating point - the VFP10 on-chip cache and MMU control application specic (e.g. MOVE)

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MANCHEstER
1824
The University of Manchester

Coprocessor instructions

t follow the ARM load/store model: r coprocessor data processing instructions

operate on values in coprocessor registers

r coprocessor data transfer instructions

move values between memory and coprocessor registers

t and in addition: r coprocessor register transfers

move values between ARM and coprocessor registers

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MANCHEstER
1824
The University of Manchester

Coprocessor instructions

t Coprocessor data processing instructions 31 28 27 24 23 20 19 16 15 12 11 8 7 5 4 3 0 cond 1 1 1 0 Cop1 CRn CRd CP# Cop2 0 CRm
CDP{<cond>} Pcp, Cop1, CRd, CRn, CRm, Cop2

t CP# species the coprocessor number: r it performs the operation specied by Cop1 and Cop2 on data in CRn and CRm, putting the result in CRd r other interpretations are possible!

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MANCHEstER
1824
The University of Manchester

Coprocessor instructions

t Coprocessor data transfer instructions 31 28 27 25 24 23 22 21 20 19 16 15 12 11 8 7 0 cond 1 1 0 P U N W L Rn CRd CP# 8-bit offset

source/destination register base register load/store write-back (auto-index) data size (coprocessor dependent) up/down pre-/post-index

LDC{<cond>}{L} Pcp, CRd, <addressing mode> STC{<cond>}{L} Pcp, CRd, <addressing mode>
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MANCHEstER
1824
The University of Manchester

Coprocessor instructions

t Coprocessor register transfer instructions 31 28 27 24 23 21 20 19 16 15 12 11 8 7 5 4 3 0 cond 1 1 1 0 Cop2 L CRn Rd CP# Cop2 1 CRm
load from coprocessor/store to coprocessor

MRC{<cond>} Pcp, Cop1, Rd, CRn, CRm{, Cop2} MRC{<cond>} Pcp, Cop1, Rd, CRn, CRm{, Cop2}

r move a 32-bit value between the coprocessor and ARM

e.g.: oating-point FIX, FLOAT and compare if Rd = r15, load is to CPSR (ags only)

2005 PEVEIT Unit ARM System Design

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MANCHEstER
1824
The University of Manchester

Coprocessor instructions

t Coprocessor register transfer instructions 31 28 27 21 20 19 16 15 12 11 8 7 4 3 0 cond 1 1 0 0 0 1 0 L Rn Rd CP# Cop1 CRm

load from coprocessor/store to coprocessor

r move a 64-bit value between the coprocessor and ARM r e.g. FMDRR Dm, Rd, Rn
Floating point 64-bit move Rd := lower half of Dm Rn := upper half of Dm

note: registers are specied independently

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MANCHEstER
1824
The University of Manchester

Coprocessor instructions

t Later ARMs (from v5) also have: r CDP2 r LDC2/STC2 r MCR2/MCR2 r MCRR2/MRCC2 t These are the same as above except: r they use the former NV (1111) condition r they are always, unconditionally, executed

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MANCHEstER
1824
The University of Manchester

Coprocessor mnemonics

r Generic coprocessor mnemonics specify the elds in the instructions

e.g.

MCR

p10, 0, R1, CR2, 0

r Sometimes more informative forms exist!

FMSR S4, R1 ; FP Move R1 to S2

p10 is the (single precision) oating point coprocessor

r Other classes or operations have similar syntax

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MANCHEstER
1824
The University of Manchester

Coprocessor interface

t Coprocessors are attached to the ARM memory bus.

They:
r watch the instruction trafc on the bus r copy instructions into a pipeline
which mimics ARMs instruction pipeline

r execute those instructions with the right CP#

though they may also decline to do so

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MANCHEstER
1824
The University of Manchester

Coprocessor interface

t Issues: r not all instructions entering the ARM pipeline are executed
those following a branch are not

r coprocessor instructions are conditionally executed r the coprocessor may be absent

if present, it may be busy

r the coprocessor controls the data types

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MANCHEstER
1824
The University of Manchester

Coprocessor interface
coprocessor instruction ARM has identied a coprocessor instruction and wishes to execute it

r ~CPI - from ARM to all coprocessors

r CPA - from the coprocessor(s) to ARM

coprocessor absent no coprocessor present can execute it

r CPB - from the coprocessor(s) to ARM

coprocessor busy a coprocessor can execute it, but not yet

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MANCHEstER
1824
The University of Manchester

Coprocessor interface

t Interface timing r shows coprocessor busy, then available mclk ~CPI CPA CPB sample copro. busy
~CPI 1 0 0 0 CPA 1 0 0 CPB 1 0 Meaning Not a (taken) coprocessor operation. No coprocessor recognises this operation Coprocessor may accept instruction in future Coprocessor committed to operation

copro. commit
Action Do nothing Illegal instruction trap Stall pipeline Coprocessor operation
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2005 PEVEIT Unit ARM System Design

MANCHEstER
1824
The University of Manchester

Coprocessors

t Outline: r the ARM coprocessor interface oating-point support r MOVE coprocessor r CP15, CP14

 hands-on: system software - semaphores

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MANCHEstER
1824
The University of Manchester

Floating-point data types

0 fraction

t single precision: 31 30 28 23 22 S exponent

r value = (-1)S x 1.fraction x 2(exponent-127) t double precision: 31 30 S 31 fraction (least signicant part) 20 19 exponent fraction (most signicant part) 0 0

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1824
The University of Manchester

Floating point support

t Floating-point instructions r map into the coprocessor instruction space r will use coprocessor if present r otherwise trap into software emulator t Floating-point library r will not use coprocessor even if present r faster than software emulator r can be called from Thumb code
Thumb has no coprocessor instructions
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MANCHEstER
1824
The University of Manchester

Floating point support

t VFP10 r vector oating-point unit

includes vector instructions that perform multiple operations

r exploits ARM1020Es 64-bit cache interface

and later

r can deliver 800 MFLOPS at 400 MHz

one load/store and one arithmetic operation per clock cycle (in vector mode)

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MANCHEstER
1824
The University of Manchester

Floating point support

t VFP10 is coprocessor number 10 r also CP11 if double precision implemented t IEEE 754 subset r supports single (32-) and (possibly) double (64-) bit fp formats r most functions in hardware
does not support remainder binary decimal round-to-integer

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1824
The University of Manchester

VFP architecture
S0 S2 S4 S6 S8 S10 S12 S14 S16 S18 S20 S22 S24 FPSID FPSCR FPEXC S26 S28 S30 S1 S3 S5 S7 S9 S11 S13 S15 S17 S19 S21 S23 S25 S27 S29 S31 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D variants

r 32 single precision registers

may overlap 16 double precision registers (bit mappings vary)

r Each S register can hold: a single precision oat or a 32-bit integer r Can process short vectors as well as scalars
up to 8 single precision up to 4 double precision

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1824
The University of Manchester

VFP system registers

r Floating point system ID register (FPSID) 31 24 23 22 21 20 19 16 15 8 7 4 3 0 implementor SW format SNG architecture part number variant revision r Floating point status and control register (FPSCR) 31 30 29 28 27 25 24 23 22 21 20 19 18 16 15 13 12 11 10 9 8 7 5 4 3 2 1 0 N Z C V 0 0 0 FZ RMODE STRIDE 0 len 0 0 0 IXE UFEOFE DZE IOE 0 0 0 IXC UFCOFC DZC IOC
ags, rounding, vector length, exception control

r Floating point exception register (FPEXC) 31 30 29 EXEN implementation dened

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MANCHEstER
1824
The University of Manchester

Example VFP instructions

t Load and store from/to memory r includes some multiple register moves t Transfers from/to ARM registers t Copy/negate/absolute value

Add/subtract/multiply/divide/square root
r single values or short vectors t Comparisons t Floating point/integer conversion

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1824
The University of Manchester

Example VFP instructions

t Floating point Add, Single precision

FADDS{<cond>} <Sd>, <Sn>, <Sm>

31 28 27 24 23 20 19 16 15 12 11 8 7 4 3 0 cond 1 1 1 0 0 D 1 1 Sn Sd 1 0 1 0 N 0 M 0 Sm r {D, N, M} are LSBs of register speciers t Floating point Divide, Double precision
FDIVD{<cond>} <Dd>, <Dn>, <Dm>

31 28 27 24 23 20 19 16 15 12 11 8 7 4 3 0 cond 1 1 1 0 1 0 0 0 Dn Dd 1 0 1 1 0 0 0 0 Dm
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MANCHEstER
1824
The University of Manchester

Example VFP instructions

t Floating point Load, Single precision

FLDS{<cond>} <Sd>, [<Rn>, #offset*4]

31 28 27 24 23 22 21 20 19 16 15 12 11 8 7 cond 1 1 0 1 U D 0 1 Rn Sd 1 0 1 0

0 offset

t Floating point Load Multiple, Double precision

FLDM<mode>D{<cond>} Rn{!}, <registers>

31 28 27 25 24 23 22 21 20 19 16 15 12 11 8 7 cond 1 1 0 P U 0 W 0 Rn Dd 1 0 1 1

0 offset

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1824
The University of Manchester

Example VFP instructions

FMSR{<cond>} <Sn>, <Rd>

t Floating point Move, Single precision from Register

31 28 27 24 23 20 19 16 15 12 11 8 7 6 5 4 3 0 cond 1 1 1 0 0 0 0 0 Sn Rd 1 0 1 0 N 0 0 1 0 0 0 0

t Floating point Move to Register from System Register

FMRX{<cond>} <Rd>, <reg>

31 28 27 24 23 20 19 16 15 12 11 8 7 6 5 4 3 0 cond 1 1 1 0 1 1 1 1 reg Rd 1 0 1 0 0 0 0 1 0 0 0 0 r <reg> = {FPSID, FPSCR, FPEXC}

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MANCHEstER
1824
The University of Manchester

Coprocessors

t Outline: r the ARM coprocessor interface r oating-point support MOVE coprocessor r CP15, CP14

 hands-on: system software - semaphores

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MANCHEstER
1824
The University of Manchester

MOVE

coprocessor

t A video encoding acceleration coprocessor r to accelerate Motion Estimation (e.g. MPEG) r implements an 8 x 8 byte block buffer r major function is SAD (Sum of Absolute Differences)
compare 8 x 8 pixel blocks

r has own mnemonics (starting with U)

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MANCHEstER
1824
The University of Manchester

Coprocessors

t Outline: r the ARM coprocessor interface r oating-point support r MOVE coprocessor CP15, CP14

 hands-on: system software - semaphores

2005 PEVEIT Unit ARM System Design

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MANCHEstER
1824
The University of Manchester

CP15, CP14

t These two coprocessors are interfaces to system

functions
r outside the memory space t CP15 is the system control coprocessor r cache, MMU, paging, etc. control and status r more details in Memory Hierarchy Support section t CP14 is the debug coprocessor r breakpoint, watchpoint, etc. control and status r more details in System Development section
2005 PEVEIT Unit ARM System Design Coprocessors v4 29

MANCHEstER
1824
The University of Manchester

Hands-on: System Software Semaphores

t Look further into ARM system software issues r Use a semaphore to perform atomic I/O

 Follow the Hands-on instructions

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