Birla Institute of Technology and Science, Pilani Work-Integrated Learning Programmes Division Second Semester 2011-2012 Course Handout

Course Number Course Title Instructors Course Description: Programmer model of CPU; Basic concept of buses and interrupts; Memory subsystem organization; I/O organization; Instruction Set and its characteristics; Processor Structure and its functions, Instruction cycle, Instruction Pipeline; Concept of assembler, linker & loader; Types of operating systems; Concept of process; OS functions: Process scheduling, Memory Management, I/O management and related issues. Scope and Learning Objectives of the Course: This course introduces the students to systems aspects involved in software development. In particular, it focuses on basic hardware architectural issues that affect the nature and performance of software as well as those features of an operating system with which most systems software have to interact. At the end of this course, a student must not only be aware of various aspects of architecture and operating systems but also must be in a position to evaluate the effects of the same on high level software. In particular, students must be able to correlate environmental and performance related issues of high-level software with system level features of the architecture or an operating system. Prescribed Text Book (S) T1. Stallings William, Computer Organization & Architecture, Pearson Education, 8th Ed., 2010 T2. A. Silberschatz, Abraham and others, Operating Systems Concepts, Wiley Student Edition, 8 th Edition, 2008. Reference Book (S) R1. J. Hennessy and D. Patterson. Computer Architecture A Quantitative Approach, Morgan Kaufman, 1990. R2. William Stallings, Operating Systems Internals and Design Principles. Prentice Hall of India, 2001. Reference Books from 24x7 R3. C. Madana Kumar Reddy, Operating Systems Made Easy Laxmi Publications, India, 2009 R4. Nirmala Sharma, Computer Architecture Laxmi Publications, India, 2009 : SS ZG516 : Computer Organization and Software Systems : Virendra S Shekhawat

SS ZG516 (Course Handout) Plan of Self-Study Topics Lect.

Second Semester 2011-2012 Learning Objectives To understand a general purpose computers organization and architecture and the interconnection among those components this facilitates the information and control exchange. Learn the hierarchy of memory subsystems with an overview of type, technology, performance and cost factors. Cache, Internal and External memory are discussed in sequence. Read/Write performance improvement using multiple memory banks (i.e. Memory Interleaving). Secondary memory types with emphasis on Magnetic Disk and its performance parameters. Learn various I/O Techniques, along with the interface requirements from OS and the external world Learn the designers and programmers view of the computer system with the help of machines instruction set and to discuss characteristics of instruction sets. Types of possible operations, addressing modes are discussed here. x86 Operation Types and Addressing modes will serve as an example. Learn the processor organization in detail with detail register organization, instruction cycle. Learn the common technique used in the speed up of instruction execution known as Pipelining along with the associated issues w.r.t. implementation To understand the sequence of sub-steps (known as cycles) that the computer go through in executing an instruction and to get into details of implementing them using hardwired and micro programmed approaches.

Page 2 Chapter/Section Reference to Text Book(s) T1. Sec. 1.1-1.2, 3.1-3.5

No. 1
Introduction: Computer Components, Functions, Interconnection Structures Computer Memory System Overview, Cache Memory Principles, Cache memory Design Considerations Internal Memory Characteristics and Design (e.g. DRAM), External Memory (e.g. Magnetic Disk), RAID Input/Output: I/O Modules, Programmed I/O, Interrupt driven I/O, DMA Instruction Sets Characteristics and Functions: Types of operands, Data Types, Type of Operations, Instruction Sets Addressing modes and Formats: Addressing, Addressing modes, Instruction formats Intel x86 will be an example Processor Structure and Function: Processor and Register Organization, Instruction Cycle, Instruction pipelining Micro operations and Micro Instructions, Control Unit Design: Micro-programmed Control, Hardwired Control

2-3

T1. Ch. 4.1-4.4 T1. Sec. 5.1, 5.3, 6.1-6.2

5 6

T1. Sec. 7.1-7.5 T1. Sec. 10.110.5, 11.1-11.4

T1. Sec.12.1-12.4

T1.Sec. 15.115.3,16.1-16.3

9 10 11

Review Session Syllabus for Mid-Semester Test (Closed Book): Topics covered in Week No. 1 to 9 Structure of an Operating To understand the basic structure of a system, T2. Ch. 1 and 2 System need of operating system for a computing machine and the structure of an OS. Processes & Threads To understand the notion of a process and to T2. Ch. 3 and 4 understand the view of the system as if consisting of OS processes. Also benefits of having Multithreaded process and various multi threading models.

SS ZG516

(Course Handout)

Second Semester 2011-2012

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Plan of Self-Study

Week No.
12 13

Topics Process Scheduling Process Synchronization

Learning Objectives Basic concepts in CPU scheduling, and algorithms are discussed To learn various mechanisms to ensure the orderly execution of cooperating processes that share logical address space. Critical section problem and various software and hardware solutions to it are discussed here. Various methods to deal with deadlock viz deadlock prevention, deadlock avoidance & deadlock detection are discussed. To understand various ways of managing the memory along with the hardware support and to understand virtual memory systems which allows the execution of a process which is completely not in the memory. To understand the physical structure of mass storage, disk scheduling mechanisms and its management.

Chapter/Sectio n Reference to Text Book(s) T2. Ch. 5 T2. Ch. 6

14-15 16

Deadlocks Memory Management & Virtual Memory Mass Storage

T2. Ch. 7 T2. Ch. 8 and 9

17 18

T2. Ch.12

Review Session Syllabus for Comprehensive Exam (Open Book): All topics given in the Plan of Self Study

Evaluation Scheme: EC No. EC-1 EC-2 EC-3 Evaluation Component & Type of Examination Assignment/Quiz Mid-Semester Test (Closed Book)* Comprehensive Exam (Open Book)* Duration ** Details to be announced on LMS Taxila website by Instructor 2 Hours 3 Hours Weightage 10% 30% 60% Day, Date, Session,Time ** Details to be announced on LMS Taxila website by Instructor Sunday, 12/02/2012 (AN)* 2 PM 4 PM Sunday, 08/04/2012 (AN)* 2 PM 5 PM

SS ZG516

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Second Semester 2011-2012

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** Please check the details by January 2nd Week on LMS Taxila web site. * Legend: AN: AfterNoon Session; FN: ForeNoon Session Closed Book Test: No reference material of any kind will be permitted inside the exam hall. Open Book Exam: Use of any printed / written reference material (books and notebooks) will be permitted inside the exam hall. Loose sheets of paper will not be permitted. Computers of any kind will not be allowed inside the exam hall. Use of calculators will be allowed in all exams. No exchange of any material will be allowed. Note: It shall be the responsibility of the individual student to be regular in maintaining the self study schedule as given in the course handout, attend the online/on demand lectures as per details that would be put up in the BITS LMS Taxila website www.taxila.bits-pilani.ac.in and take all the prescribed components of the evaluation such as Assignment (Course Page on LMS Taxila), Mid Semester Test and Comprehensive Examination according to the Evaluation Scheme given in the respective Course Handout. If the student is unable to appear for the Regular Test/Examination due to genuine exigencies, the student must refer to the procedure for applying for Make-up Test/Examination, which will be available through the Important Information link on the BITS WILP website on the date of the Regular Test/Examination. The Make-up Tests/Exams will be conducted only at selected exam centres on the dates to be announced later. Instructor-in-Charges