The FlexRay Protocol for Automotive Applications

Marco Sacchi FAE Technical Manager January 24, 2008

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FlexRay Introduction
FlexRay is an open, common, scalable network architecture for automotive applications. FlexRay is meant to enable next-generation, high-bandwidth control applications, including powertrain and body systems and ultimately targeting by-wire solutions for active chassis management, braking systems and steering.

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The FlexRay Consortium

The FlexRay Consortium

The FlexRay Communications System

The FlexRay Products

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Consortium Motivation
Market need for an industry wide standard scalable communications system Support distributed control systems

Funct. A Funct. B ECU ECU

Funct. C Funct. A ECU

Physical Layer Distributed system. Funct. A Funct. B ECU Funct. C Funct. D ECU Physical Layer Networked system. Funct. E Funct. F ECU

Communications system with high data rate Deterministic and fault-tolerant communication system

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Consortium Goals
FlexRay defines
a communication system comprising the specification of a communications protocol and a physical layer for future generation high-speed control applications in vehicles.

FlexRay is defined

in the context of an industry consortium since 2000

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Consortium Structure
Consortium organized in three membership shells

Differences are in rights and obligations

Associate Members Premium Associate Core Members

Details (and applications) via the Consortium Administrator through http://www.flexray.com

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Consortium Members (per Q4 2005)

Continental Teves AG

Premium Associate Members

Delphi Corporation Denso Corporation Fiat Auto S.p.A. Ford Motor Company Honda Motor Company Hyundai-Kia Motors Motorola Nissan Motor Company PSA Peugeot Citroen Automobiles Renault Technocentre Toyota Motor Corporation Tyco Electronics Corporation

BMW Group

Core Members

Bosch DaimlerChrysler General Motors Freescale Semiconductor Philips Volkswagen AG

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Consortium Members (per Q4 2005)

ADAC AISIN Alpine AMI Atmel austriamicrosystems Avidyne Berata Bertrandt Calsonic Kansei EADS ELMOS EPCOS ESG Esterel Eurospace Fujitsu Fujitsu TEN Haldex Hella Hitachi Cable Hitachi Hyundai Autonet IAV Infineon

IPETRONIK IROC ISUZU Motors Mitsubishi Electric Tata Elxsi Murata TDK Electronics NEC TI Nihon ThyssenKrupp NIPPON SEIKI Tokai Rika NSK Toyota Tsushu Okaya TRW OKI Pacifica Group Techn. TUEV Nord Valeo Porsche Verifica Preh Visteon Renesas Volke Consulting Eng. Scania Wuerth Elektronik eiSos SiemensVDO Xilinx SKF Industrie Yamaha SP Swedish Nat. Testing ST Microelectronics Yazaki Yokogawa Subaru Sumitomo Sunny Giken Suzuki

3SOFT ARC Seibersdorf Berner&Matter C&S Group Cadence CANway CapeWare Cardec Cbb software CRST Dearborn DECOMSYS dSpace ETAS FTZ Gigatronik Gpel electronic Hitex IMD Intrepid Control Systems IXXAT K2L Kleinknecht Automotive Lauterbach

Micron MicroSys Mirabilis Design Mission Level Design National Instruments NSI proTime SEDES Softing SystemA Tecwings Textronix Toyota Macs TTAutomotive TZM Vector Informatik Volcano Warwick Weise

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FlexRay Protocol Specification Roadmap

FlexRay Protocol Specifications
FlexRay Consortium founded PS V0.8 PS V0.6 PS V1.0 PS V1.9 PS V0.4.3 2001 2002 2003 MFR 4100 PS V2.0 PS V2.1A PS V2.1 2004 2005 2006 MCU Products MFR 4300

2000

Freescale Semiconductor Communication Controllers Philips Semiconductors Physical Layer Bus Driver

FPGA V4 FPGA V5

MFR 4200 FPGA V9

TJA1080

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The FlexRay Communications System

The FlexRay Consortium

The FlexRay Communications System

The FlexRay Products

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FlexRay Requirements
Physical Layer Requirements Non fault-tolerant properties Communications Protocol Requirements Requirements

Requirements

Fault-tolerant properties

Requirements Interconnection architectures, functional properties of physical layer

Requirements Communication phases, services and functions within each communication phase

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Interconnection Architectures

Optional BG Single channel

Bus

Multiple star

@ 10MBit reduced wire-harness, experience, cost tolerates one faulty channel

Dual channel mixed topologies passive medium, most experience, cost efficient allows for high data rates, increases error containment

electrical & optical physical layer

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Mixed Topology Example

Active Star
Node 1

Node 2

Node 3

Node 4 Node 5

Active Star

Linear Passive Bus

Node 6

Node 7

Passive Star

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Data Exchange in a Nutshell

Communication cycle (driven by synchronized time base) Static segment TDMA based MAC (bounded latency and small latency jitter communication, deterministic communication static bandwidth requirements) Channel A Dynamic segment flexible TDMA based MAC (ad-hoc communication, varying bandwidth requirements,)

NIT

3a

1a

3c

4a

1c

4b

3d

6a
t

Channel B

7 8

13

3b

5d

2a

3c

1c

3e

1d

2b
t

Example of a FlexRay communication cycle showing the static and the dynamic segment.

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Integration Property
1 2 3 4 5 6 7 8 9

Channel A
1 2

1a
3 4 5

4a
6

1c

4b
t
7 89 13

Channel B

1b

2a

1c

1d

2b
t

Channel A
1

3a
2 3 4

3c
5

4a
6

4b
7 8 9

3d
t
13

Channel B

3b

2a

3c

3e

2b
t

Channel A
1

3a
2

1a
3 4

3c
5

4a
6

1c

4b
7 8 9

3d
t
13

Channel B

3b

1b

2a

3c

1c

3e

1d

2b
t

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Frame Format
Payload preamble indicator

Sync frame indicator

Reserved bit

Startup frame indicator

Null frame indicator

Header CRC Covered Area

Frame ID

Payload length

Header CRC

Cycle count

Data 0 Data 1 Data 2 0 ... 254 Bytes Payload Segment

Data n

CRC

CRC 24 bits

CRC

11 bits 11111

7 bits

11 bits

6 bits

Header Segment

Trailer Segment

FlexRay Frame 5 + (0 ... 254) + 3 Bytes

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Synchronization

Node A Communication Network

Node B

Means for exchanging deviations

Explicit exchange versus implicit exchange Physical reference clock versus virtual reference clock Offset correction versus rate correction

Some form of reference clock An adjustment policy

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Synchronization Principle
Exchanging Deviations

Implicit exchange of clock deviations via exchange of (sync) frames

1:00 2:00 3:00

Node x

Send frame A

Receive frame B

Send frame C

2:00 (expected time of arrival) 2:05 (actual time of arrival) (0:05) (measured deviation)

Virtual reference clock

Receive frame B

No single physical reference clock exists Nodes calculate deviation in respect to virtual reference clock Virtual reference clock established using distributed fault-tolerant clock synchronization algorithm (fault-tolerant midpoint)

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Synchronization Principle (cont.)

Adjustment policy - Offset correction

Periodically measure phase deviation to a reference clock Adjust clock according to measured deviation Example:

Adjustment policy - rate correction

Periodically measure frequency deviation to a reference clock Adjust clock according to measured deviation Example 1: Example 2:

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Timing Hierarchy

communication cycle level static segment arbitration grid level static slot macrotick level macrotick microtick level microtick action point minislot dynamic segment symbol network window idle time

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Node Architecture

Host
Controller Host Interface

Communication Controller
MAC

POC

PHY

PHY

Clock Sync

FSP

Coding

Decoding

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Partitioning

To actuator

From sensor

Application

Controller host interface (CHI)

Message buffer management Control / status / config data

Control interface

Config interface

Message interface

Status interface

Controller host interface services

Transparent to protocol
Timer service Filtering services (e.g. Message ID filtering) Network management service

Communications protocol
From communication channels

To communication channels

Allows extensions

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FlexRay Application Domains

Chassis Other Powertrain

Backbone

Driver Assistance

High-speed communication

By-wire systems

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Automotive Networking Overview

Channels Speed Time Triggered Arbitration Devices available from Freescale today

LIN Single 20 Kbit/s No Master Yes

CAN Single <= 1 Mbit/sec No CSMA Yes

FlexRay Single / Dual 10 Mbits/sec Yes TDMA Yes

Freescale is a leader in defining next generation communications specifically for Automotive.

Freescale is a founding member of the LIN Consortium Freescale is a founding member of the FlexRay Consortium

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Decision Criteria for FlexRay

Criteria Bandwidth CAN Busload on different CAN sub-buses at limit Multiple gateways cause unacceptable delays

FlexRay Net data rate 5MBit/s at gross 10 MBit/s Flexible use of bandwidth

Topologies

CAN requires bus with dominant / recessive state Non-deterministic behavior of CAN at high bus loads results in poor quality of service System integration can cause strange side effects by increasing bus load Underlying operating concept does not consider application level fault-tolerance

Star topology provides improved electrical characteristics & fault isolation Flexible topologies

Deterministic communication System integration Fault-tolerance

Deterministic latencies (guaranteed transmission time for frames in static segment) System integration does not change any timing Underlying operating concept considers application level fault-tolerance (redundant channel, fault-tolerant clock synchronization) Synchronization of application tasks through synchronized time base

Application level replica determinism

Synchronization of application tasks requires additional communication

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The FlexRay Products

The FlexRay Consortium

The FlexRay Communications System

The FlexRay Products

Freescale and the Freescale logo aretrademarksof Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. Freescale Semiconductor, Inc. 2006.

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FlexRay Roadmap
32-bit MCU with embedded FlexRay

Application Performance / Integration

Tiger 2M MPC5567 Lance 1M MPC5561 512K-1.5M Flash Up to 80MHz, ECC, IOP, MOST, EBI, MPU 144 LQFP, 208 MAPBGA

1M MPC5516G 512K MPC5514G S12XF512 S12XF384 S12XF256 S12XF128

1.5M MPC5517G

16-bit MCU with embedded FlexRay

128K-512K Flash Up to 50 MHz, XGATE, ECC, PMF 64 LQFP, 112 LQFP

Standalone FlexRay controller

MFR4200 MFR4100
Proto Spec 0.8

S12XFR128 Replaced by S12XF128 MFR4310

In Production In Execution Planned Proposed

MFR4300 Replaced by MFR4310

Proto Spec 2.1

FlexRay IP Version

Proto Spec 1.9

2004

2005

2006

2007

2008

2009

2010

TM Freescale and the Freescale logo aretrademarksof Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. Freescale Semiconductor, Inc. 2006. This document contains forward-looking statements based on current expectations, forecast and assumptions of Freescale that involves risk and uncertainties. Forward looking statements are subject to risk and uncertainties associated with Freescale business that could cause actual results to vary materially from those stated or implied by such forward-looking statements.

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MFR4310: Standalone FlexRay Controller

Description

Standalone FlexRay Controller Enables MCUs without embedded FlexRay controllers to connect to a FlexRay network Eases integration of FlexRay into existing designs

Voltage Regulator Oscillator Asynchronous Interface Clk+Res Mod Ext Clk Int S12 Interface

Key Features

Conforms to FlexRay Communications System Protocol Specification V2.1A Variable bit rate support: 2.5, 5, 8, or 10 Mb/s 128 configurable message buffers Message buffer header, status and payload data are stored in 6 KB of on-chip system memory Two independent message buffer segments with configurable size of payload data section Transmit message buffers configurable with state/event semantics Individual message buffer reconfiguration supported Two independent receive FIFOs 4 configurable slot error counters 4 dedicated slot status indicators 1 absolute timer 1 timer that can be configured to absolute or relative

FlexRay Host Interface

Receiver A Transmitter A TCU

Receiver B Transmitter B Debug

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S12XF: 16-bit embedded FlexRay MCU

S12XF Description The 16-bit family of integrated FlexRay Microcontrollers from the widely adopted S12X architecture based on Freescales 0.18u process technology. It provides the right level of size, performance & functionality to enable customers to build sensors and actuators modules on the FlexRay Network. KEY BENEFITS Dual-channel FlexRay Controller High performance S12X+XGATE architecture Pulse width modulator with Fault detection module for motor control High-quality and reliable 0.18u technology Hardware and software compatibility and wide portfolio offer Flexible internal EEPROM remove the need for external EEPROM chip
IO ECT 8Ch
S12X BUS

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External Bus Interface

S12X 16-bit CISC CPU

Single-wire BDM Debug Module 4AB/2DB 512B TB

VREG Reset & Test FMPLL VREG ACLPP FDP Oscillator

XGATE 16-bit RISC Core

Interrupt Controller

EEPROM RAM Flash 32K Flash 470K RAM

Clock Mon COP API EPIT

DataFlash

CAN

SCI/LIN 2 Ports

SPI

SCC2

FlexRay 2Ch

PMF 6Ch

ATD 16Ch

XGATE BUS

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MPC5561: 32-bit Adv Safety and Driver Assistance MCU with FlexRay
Core
40-132MHz Power Technology e200z6 Core
Integer binary user mode compatible with RCPU(MPC500) New SIMD module for DSP and floating point features

Memory
1M byte RWW Flash with ECC 224k Total SRAM with ECC (including cache memory)
192k Data SRAM with ECC 32k unified-cache (with line locking)

Interrupt
Controller

Power Technology e200z6

SIMD
DSP & Floating point

JTAG

Nexus
IEEE-ISTO 5001-2003

I/O
8ch eMIOS with unified channels 1 x FlexRay Controller 2 x FlexCAN - compatible with TouCAN, 64 buffers each 4 x eSCI 2 x DSPI 16 bits wide up to 6 chip selects each

MMU

eDMA

32 KB Cache

Flexray Controller

External Master Interface

16/32 bit External Bus Interface

Standard SPI with continuous mode and DMA support Pin serialization (similar to PPM) 40 channel Dual ADC - up to 12 bit and up to 1.25s conversions, 6 queues with triggering and DMA support.

5 x 5 Crossbar Switch + PDI

I/O Bridge Flash 1 MB SRAM 192 KB I/O Bridge Cal Bus Interface

PDI Interface for external analog sensors

SIU

System
FM-PLL 64 Channel DMA Controller 308 Source Interrupt Controller Nexus IEEE-ISTO 5001-2003 Class 3+ MPC500 compatible External Bus Interface supporting
classic and burst external flash.

Boot Assist Module

eMIOS
8 Channel

2x
FlexCAN

4x eSCI

2x DSPI

2x A/D

5/3.3V IO, 5V ADC, 3.3V/1.8V bus, 1.5V core (from internal

regulator controller) 324 PBGA package

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MPC5567: 32-bit Chassis and Engine Management MCU with FlexRay

Core
40-132MHz Power Technology e200z6 Core + VLE
Binary User mode compatible with RCPU (MPC500) and e200z6/3

Memory
2Mbyte RWW Flash with ECC 80k SRAM 8k cache Interrupt Controller Power Technology e200z6
SIMD
DSP & Floating point

JTAG

Nexus
IEEE-ISTO 5001-2003

I/O
56 Timed I/O Channel 32 channel ETPU 24 channel EMIOS with unified channels FlexRay Controller Dual Channel (10MB/s) Fast Ethernet Controller MMI Interface 5 x FlexCAN - compatible with TouCAN, 64 buffers each 2 x eSCI 3 x DSPI 16 bits wide up to 6 chip selects each
Standard SPI with continuous mode and DMA support Pin serialization (similar to PPM)

VLE

MMU FEC FlexRay Controller

External Master Interface

eDMA

8 KB Cache

16/32 bit External Bus Interface

5 x 5 Crossbar Switch
Flash 2 MB SRAM 80 KB

40 channel Dual ADC - up to 12 bit and up to 1.25s

conversions, 6 queues with triggering and DMA support.

I/O Bridge

SIU

Boot Assist Module

I/O Bridge

Cal Bus Interface

System
FM-PLL 32 Channel DMA Controller 281 Source Interrupt Controller Nexus IEEE-ISTO 5001-2003 Class 3+ Second EBI for calibration (16bit, not pinned out of BGA) 5/3.3V IO, 5V ADC, 3.3V logic supply, 1.5V core (from internal regulator
controller)

eTPU
32 Channel

eMIOS
24 Channel

Data RAM 2.5 KB Code RAM 12 KB

5x
FlexCAN

2x eSCI

3x DSPI

2x A/D

324 PBGA package (No FEC) 416 PBGA package

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MPC5516G: 1Mb Gateway controller w/ FlexRay

CORE
Power Technology e200z1 core running 66-80MHz VLE ISA instruction set for superior code density Vector interrupt controller e200z0 I/O Processor support for peripherals Memory Protection Unit with 16 regions, 32byte granularity

System Integration
VReg Osc/PLL Interrupt Controller

Crossbar Masters
Power Technology
e200z1 Core

Debug
JTAG Nexus Class 2+
e200z0 Core

MEMORY
1Mbyte embedded program Flash Up to 80MHz single cycle non-sequential access ECC-enabled array with error detect/correct Small Flash block support for EEPROM Emulation 64Kbyte SRAM (single cycle access, ECC-enabled)

eDMA

VLE MMU

FlexRay Controller

COMMUNICATIONS
6x enhanced FlexCAN (64 Message Buffers each, full CAN 2.0 spec) Dual channel FlexRay Controller (64 Message Buffers each, full FR 2.1) I/O Processor sharing on-chip memory External bus interface (optional) 6x eSCI with LIN state machine 3x DSPI, 8-16 bits wide & chip selects IC

CROSSBAR SWITCH
Memory Protection Unit (MPU)

I/O Bridge

1Mb Flash w/ ECC

64K SRAM w/ ECC

External Bus

Boot Assist Module (BAM)

ANALOG
5V ADC (16 channels, 12-bit resolution) 16-bit eMIOS-lite module

Crossbar Slaves
Communications I/O System
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TIMED I/O 8 dual action PWM, 8 single action capture compare OTHER
Real Time Counter clocked by external 32kHz crystal Debug: Nexus 2+ I/O: 5V I/O, high GPIO pin count Packages: 144LQFP, 208MAPBGA

eMIOSLite 16 ch.

6x eFlexCAN

6x eSCI

3x DSPI

1x I2C

16 ch 12-bit ADC

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Looking to set up a FlexRay network quickly and easily?

S12XFSTARTERKITE contains everything required to set up a 2-node FlexRay network in less than an hour.
S12XFSTARTERKITE Contents
2 x EVB9S12XF512E (S12XF512 evaluation boards) 2 x Power supply with interchangeable prongs (America, Europe, Australia) 2 x CAN Cable 4 x FlexRay Cables 1 x P&E USB BDM Multilink with documentation 1 x Freescale Documentation CD including FlexRay driver and application examples 1 x CodeWarriorTM Development Studio Special Edition (included in documentation CD) 1 x Printed Quick Start Guide 1 x Decomsys Designer Pro information CD

S12XF Starter Kit

NOTE: the EVB9S12XF512E evaluation board comes assembled with the 112 LQFP. This board is designed to also
support the PC9S12XF512MLH (64 LQFP package). Order a separate samples for customers requesting 64pin version.

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Freescale and the Freescale logo aretrademarksof Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. Freescale Semiconductor, Inc. 2006.