PART A-(10*2=20marks)

1)What is BiCMOS devicse? 2)What are the factors that contribute for the threshold voltage of MOSFET? 3)What is the super buffer?Give an applicatipn. 4)What do you understand by lamda based rules? 5)Sketch the NOR implementaion of an NMOS 4 to 1 MUX. 6)Compare static CMOS and Dynamic CMOS in terms of its application. 7)What are the logics used in the implementation of NMOS PLA? 8)When does a PLA become Finite State Machine(FSM)? 9)What is entity?Give an example. 10)State the difference between the transport delay and inertial relay? PART B-(5*16=80marks) 11)(a)Derive expression for drain current in saturation and lineor regions(16) or (b)(i)Draw and explain the small signal model f MOS transistor.(6) (ii)Explain the fabrication process of NMOS device.(10) 12)(a)Draw and explain passive load NMOS inverter and active load NMOS inverter.Draw their stick diagrams. or (b)(i)Draw the diagram of NMOS superbuffer and explainm(8) (b)Draw the circuit of BiCMOS inverter and explain.(8) 13)(a)(i)Draw the circit of 2input NAND gate using static CMOS design and explain.(8) (ii)What is the barrel shifter?Also explain its working with a neat circuit of 4*4 barrel shifter.(8) or (b)(i)Draw the circuit of dynamic CMOS logic and explain its operation.(8) (ii)Write a note on Tally circuits.(8) 14)(a)With a neat diagram,explain the architecture of any FPGA device with its programmable interconnect.(16) or (b)(i)Draw and expain the dynamic logic array(DLA).compare its with PLA.(8) (ii)Sketch the structure of PLA and explain.(8) 15)(a)Write a structural level program for 4bit adder using VHDL.(16) or (b)Explain the various signal assignment staements in VHDL.(16)

Part-A (10*2=20) 1. What are the advantages of BiCMOS technology? 2. What is meant by hot electrons effect? 3. Draw the stick diagram of an NMOS inverter. 4. What are the problems encountered in driving large capacitive loads? 5. Compare the number of MOS transistors required by the conventional CMOS and dynamic CMOS approaches for implementing a gate of M pulse. 6. Distinguish absolute clock skew and relative clock skew. 7. What factors determine the overall size of a PLA? 8. What are the advantages and disadvantages of PLDs? 9. Write the VHDL entity for an RS flip-flop. 10. Distinguish the EXIT and NEXT statements of VHDL. Part-B (5*16=80 11.(a)(i) Explain the different steps of n-well CMOS fabrication process with neat diagrams.(10) (ii) Compare the construction, operation and characteristics of NMOS enhancement and depletion transistors.(6) Or (b)(i) Consider an NMOS transistor with the following parameters: gate oxide thickness=10nm, relative permittivity of gate oxide =3.9, electron mobility = 520cm2/V-sec, threshold voltage=0.7V, permittivity of free space=8.85*10power14 F/cm and (W/L)=8. Calculate the drain current for the two cases of (Vgs=2V and Vds=2V) and (Vgs=2V and Vds=1.2V). . Note that W and L refer to the width and length of the channel respectively.(10) (ii) Explain the significance of threshold voltage of MOS transistors with necessary equations.(6) 12.(a) (i) Derive the pull up to pull down ratio required for an NMOs inverter driven by another NMOS inverter.(8) (ii) Draw and explain the lambda based rules for NMOS transistor region and contact cuts.(8) Or (b)Draw and explain the operation of (i)Inverting and noninverting NMOS super buffers.(10) (ii)BiCMOS two input NOR gate(6) 13.(a)(i) Describe the operation of dynamic CMOS, precharged-high, two input NOR

and NAND gates with neat diagrams.(8) (ii) Explain the different CMOS implementation of 4 to 1 multiplexer.(8) Or (b)(i) Draw a 4*4 band shifter based on NMOS transistors and explain its operation and applications.(8) (ii) Draw and explain the different exclusive-OR structures with neat circuit and stick diagrams.(8) 14.(a)(i) Explain the NMOS NAND-NAND PLA realization with a neat stick diagram(8) (ii) Write a brief note on PLA based finite state machine.(8) Or (b)(i) Draw and explain the clocked FPLA structure and compare it with PROM.(8) (ii) Explain the different types of programmable interconnects used in FPGA.(8) 15.(a)(i) Write the VHDL entity and behavioral description of a 1 to 4 demultiplexer(8) (ii) Explain the concurrent and sequential assignments in VHDL with suitable diagrams (8) Or (b)(i) Write a VHDL function to convert an integer into a binary number(8) (ii) Explain a simple test bench for a bit comparator with necessary VHDL code(8)

http://www.scribd.com/full/2599657?access_key=key-c0ol3hnjfmjqeyuq1y8