1.

ABSTRACT

A robot is an apparently human automation, intelligent and obedient but impersonal machine. Basically, a robot is a machine designed to do a human job (excluding research robots) that is tedious, slow or hazardous. It is only relatively recently that robots have started to employ a degree of Artificial Intelligence (AI) in their work - many robots required human operators, or precise guidance throughout their missions. Slowly, robots are becoming more and more autonomous. The difference between robots and machinery is the presence of autonomy, flexibility and precision. Indeed, many robots are mere extensions of machinery, but as the field advances more and more, the current 'fine line' will widen more and more.

2. INTRODUCTION
Now a day's every system is automated in order to face new challenges. In the present days Automated systems have less manual operations, flexibility, reliability and accurate. Due to this demand every field prefers automated control systems. Especially in the field of electronics automated systems are giving good performance. and we can implement a system in which a robot direction can be controlled wirelessly with respect to the commands given by the user through PC using Zigbee technology. In this project Unmanned Intelligent Military Robot For Using Zigbee transceiver and in receiver side. DC motor share configured in many types and sizes, including brush less, servo, and gear motor types. A motor consists of a rotor and a permanent magnetic field stator. The magnetic field is maintained using either permanent magnets or electromagnetic windings. DCmotorsare most commonly used in variable speed and torque. Communication: Communication refers to the sending, receiving and processing of information by electric means. As such, it started with wire telegraphy in the early 80s, developing with telephony and radio some decades later. Radio communication became the most widely used and refined through the invention of and use of transistor, integrated circuit, and other semi-conductor devices. Most recently, the use of satellites and fibres optics has made communication even more wide spread, with an increasing emphasis on computer and other data communications. A modern communications system is first concerned with the sorting, processing and storing of information before its transmission. The actual transmission then follows, with further processing and the filtering of noise. Finally we have reception, which may include processing steps such as decoding, storage and interpretation.

3.BLOCK DIAGRAM

3.1 RECEIVER MODULE:

Power supply

PC

UART

ZigBee

Fig.1 Receiver Module

3.2 TRANSMITTER BLOCK:

Power Object sensor Supply

Interfacing Circuit

Driver Circuit Driver Circuit

Motor1

Buzzer CAM

Micro Controller

Motor2

Fig. 2 Transmitter Block

4. HARDWARE ARCHITECTURE

4.1 POWER SUPPLY UNIT A power supply (sometimes known as a power supply unit or PSU) is a device or system that supplies electrical or other types of energy to an output load or group of loads. The term is most commonly applied to electrical energy supplies, less often to mechanical ones, and rarely to others.

Transformer

Rectifier

Filter

Regulator

Fig. 3 Block Diagram of Power Supply

345V (PEAK TO PEAK) TRANSFOR MER

173V PEAK (PULSATING DC)

110VDC (AVERAGE VOLTAGE WITH AC ROPPLE) REGULATO R

110VDC

RECTIFIER BRIDGE

FILTER

115VAC

Fig. 4 Processing of power supply The transformer steps up or steps down the input line voltage and isolates the power supply from the power line. The RECTIFIER section converts the alternating current input signal to a pulsating direct current. However, as you proceed in this chapter you will learn that pulsating dc is not desirable. For this reason a FILTER section is used to convert pulsating dc to a purer, more desirable form of dc voltage. The final section, the REGULATOR, does just what the name implies. It maintains the output of the power supply at a constant level in spite of large changes in load current or input line voltages. Now that you know what each section does, let's trace an ac signal through the power supply. At this point you need to see how this signal is altered within each section of the power supply.

4.1.1 SIMPLE 5V POWER SUPPLY FOR DIGITAL CIRCUITS

Brief description of operation: Gives out well regulated +5V output, output current capability of 100 mA Circuit protection: Built-in overheating protection shuts down output when regulator IC gets too hot Circuit complexity: Very simple and easy to build Circuit performance: Very stable +5V output voltage, reliable operation Availability of components: Easy to get, uses only very common basic components Design testing: Based on datasheet example circuit, I have used this circuit successfully as part of many electronics projects Applications: Part of electronics devices, small laboratory power supply Power supply voltage: Unregulated DC 8-18V power supply Power supply current: Needed output current + 5 mA Component costs: Few dollars for the electronics components + the input transformer cost

4.2 CIRCUIT DESCRIPTION This circuit is a small +5V power supply, which is useful when experimenting with digital electronics. Those transformers are easily available, but usually their voltage regulation is very poor, which makes then not very usable for digital circuit experimenter unless a better regulation can be achieved in some way. The following circuit is the answer to the problem. This circuit can give +5V output at about 150 mA current, but it can be increased to 1 A when good cooling is added to 7805 regulator chip. The circuit has over overload and terminal protection.

4.3 INTERFACING THE SERIAL / RS232 PORT The Serial Port is harder to interface than the Parallel Port. In most cases, any device you connect to the serial port will need the serial transmission converted back to parallel so that it can be used. This can be done using a UART. On the software side of things, there are many more registers that you have to attend to than on a Standard Parallel Port (SPP). So what are the advantages of using serial data transfer rather than parallel? Serial Cables can be longer than Parallel cables. The serial port transmits a '1' as -3 to -25 volts and a '0' as +3 to +25 volts where as a parallel port transmits a '0' as 0v and a '1' as 5v. Therefore the serial port can have a maximum swing of 50V compared to the parallel port which has a maximum swing of 5 Volts. Therefore cable loss is not going to be as much of a problem for serial cables as they are for parallel. You don't need as many wires as parallel transmission. If your device needs to be mounted a far distance away from the computer then 3 core cable (Null Modem Configuration) is going to be a lot cheaper that running 19 or 25 core cable Infra Red devices have proven quite popular recently. You may of seen many electronic diaries and palmtop computers which have infra red capabilities build in. However could you imagine transmitting 8 bits of data at the onetime across the room and being able to (from the devices point of view) decipher which bits are which? Therefore serial transmission is used where one bit is sent at a time. IrDA-1 (The first infra red specifications) was capable of 115.2k baud and was interfaced into a UART.

Microcontrollers have also proven to be quite popular recently. Many of these have in built SCI (Serial Communications Interfaces) which can be used to talk to the outside world. Serial Communication reduces the pin count of these MPU's. Only two pins are commonly used, Transmit Data (TXD) and Receive Data (RXD) compared with at least 8 pins if you use a 8 bit Parallel method.

4.4 MAX 232

4.4.1 INTRODUCTION: Electrical signal characteristics such as voltage levels, signaling rate, timing and slew-rate of signals, voltage withstand level; short-circuit behavior, and maximum load capacitance. Interface mechanical characteristics, pluggable connectors and pin identification. Details of character format and transmission bit rate are controlled by the serial port hardware, often a single integrated circuit called a UART that converts data from parallel to asynchronous start-stop serial form. Details of voltage levels, slew rate, and short-circuit behavior are typically controlled by a line-driver that converts from the UART's logic levels to RS-232 compatible signal levels, and a receiver that converts from RS-232 compatible signal levels to the UART's logic levels. 4.4.2 PIN DIAGRAM OF MAX 232:

Fig. 9 Pin Diagram of MAX 232 A common deviation from the standard was to drive the signals at a reduced voltage: the standard requires the transmitter to use +12V and -12V, but requires the receiver to distinguish voltages as low as +3V and -3V. Some manufacturers therefore built transmitters that supplied +5V and -5V and labeled them as "RS-232 compatible."

The large voltage swings and requirement for positive and negative supplies increases power consumption of the interface and complicates power supply design. The voltage swing requirement also limits the upper speed of a compatible interface. Singleended signaling referred to a common signal ground limits the noise immunity and transmission distance. Multi-drop connection among more than two devices is not defined. While multi-drop "work-around" has been devised, they have limitations in speed and compatibility. 4.4.3 STANDARD DETAILS: In RS-232, user data is sent as a time-series of bits. Both synchronous and asynchronous transmissions are supported by the standard. In addition to the data circuits, the standard defines a number of control circuits used to manage the connection between the DTE and DCE. Each data or control circuit only operates in one direction that is, signaling from a DTE to the attached DCE or the reverse. Since transmit data and receive data are separate circuits, the interface can operate in a full duplex manner, supporting concurrent data flow in both directions. The RS-232 standard defines the voltage levels that correspond to logical one and logical zero levels. Valid signals are plus or minus 3 to 15 volts. The range near zero volts is not a valid RS-232 level; logic one is defined as a negative voltage, the signal condition is called marking, and has the functional significance of OFF. Logic zero is positive; the signal condition is spacing, and has the function ON. The standard specifies a maximum open-circuit voltage of 25 volts; signal levels of 5 V, 10 V,12 V, and 15 V are all commonly seen depending on the power supplies available within a device. RS-232 drivers and receivers must be able to withstand indefinite short circuit to ground or to any voltage level up to 25 volts. The slew rate, or how fast the signal changes between levels, is also controlled.

Because the voltage levels are higher than logic levels typically used by integrated circuits, special intervening driver circuits are required to translate logic levels. These also protect the device's internal circuitry from short circuits or transients
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that may appear on the RS-232 interface, and provide sufficient current to comply with the slew rate requirements for data transmission. Because both ends of the RS-232 circuit depend on the ground pin being zero volts, problems will occur when connecting machinery and computers where the voltage between the ground pin on one end and the ground pin on the other is not zero. This may also cause a hazardous ground loop. 4.4.4 SIGNALS: Commonly-used signals are: Transmitted Data (TxD) Received Data (RxD) Request To Send (RTS) Ready To Receive (RTR) Clear To Send (CTS) Data Terminal Ready (DTR) Data Set Ready (DSR) 4.4.4.1 Transmitted Data (TXD) Data sent from DTE to DCE. 4.4.4.2 Received Data (RXD) Data sent from DCE to DTE. 4.4.4.3 Request to Send (RTS) Asserted (set to logic 0, positive voltage) by DTE to prepare DCE to receive data. This may require action on the part of the DCE.

4.4.4.4 Ready to Receive (RTR)

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 Asserted by DTE to indicate to DCE that DTE is ready to receive data. If in use, this signal appears on the pin that would otherwise be used for Request to send, and the DCE assumes that RTS is always asserted. 4.4.4.5 Clear to Send (CTS) Asserted by DCE to acknowledge RTS and allow DTE to transmit. This signaling was originally used with half-duplex modems and by slave terminals on multi drop lines: 4.4.4.6 Data Terminal Ready (DTR) Asserted by DTE to indicate that it is ready to be connected. If the DCE is a modem, this may "wake up" the modem, bringing it out of a power saving mode 4.4.4.7 Data Set Ready (DSR) Asserted by DCE to indicate the DCE is powered on and is ready to receive commands or data for transmission from the DTE 4.4.5 HANDSHAKING The DTE asserts RTS to indicate a desire to transmit to the DCE, and the DCE asserts CTS in response to grant permission. This allows for half-duplex modems that disable their transmitters when not required, and must transmit a synchronization preamble to the receiver when they are re-enabled. There is no way for the DTE to indicate that it is unable to accept data from the DCE. 4.4.6 TIMING SIGNALS Some synchronous devices provide a clock signal to synchronize data transmission, especially at higher data rates. Two timing signals are provided by the DCE on pins 15 and 17. Pin 15 is the transmitter clock, or send timing (ST); the DTE puts the next bit on the data line (pin 2) when this clock transitions from OFF to ON (so it is stable during the ON to OFF transition when the DCE registers the bit). Pin 17 is the receiver clock, or receive timing (RT); the DTE reads the next bit from the data line (pin 3) when this clock transitions from ON to OFF. 4.5 LIQUID CRYSTAL DISPLAY (LCD)

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4.5.1 INTRODUCTION: A 162 LCD display is used for displaying the Crossing the Boundary. LCD display is connected to port 2 of the microcontroller. Every pin in port 2 is connected to LCD display. Message is sent through commands via serial communication. The most commonly used Character based LCDs are based on Hitachi's HD44780 controller or other which are compatible with HD44580. In this project document, we will discuss about character based LCDs, their interfacing with various microcontrollers, various interfaces (8-bit/4-bit), programming.

Fig. 10 LCD Display

LCDs are more energy efficient and offer safer disposal than CRTs. Its low electrical power consumption enables it to be used in battery-powered electronic equipment. It is an electronically modulated optical device made up of any number of segments filled with liquid crystals and arrayed in front of a light source (backlight) or reflector to produce images in colour or monochrome. The most flexible ones use an array of small pixels.

4.5.2 PIN DETAILS:

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PIN NUMBER Pin Number-1 Pin Number-2 Pin Number-3 Pin Number-4

NAME VSS VCC VEE RS

DESCRIPTION Power Supply (GND) Power Supply(+5V) Contrast Adjust 0=Instruction Input 1=Data Input

Pin Number-5

R/W

0=Write to LED Module 1=Read from LED Module

Pin Number-6 Pin Number-7 Pin Number-8 Pin Number-9 Pin Number-10 Pin Number-11 Pin Number-12 Pin Number-13 Pin Number-14

EN D0 D1 D2 D3 D4 D5 D6 D7

Enable Signal Data Bus Line 0 (LSB) Data Bus Line 1 Data Bus Line 2 Data Bus Line 3 Data Bus Line 4 Data Bus Line 5 Data Bus Line 6 Data Bus Line 7 (MSB)

Tab. 3 Character LCD Pins

2. MICROCONTROLLER
2.1 FEATURES:

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 Compatible with MCS-51 Products 4K Bytes of In-System Reprogrammable Flash Memory Endurance: 1,000 Write/Erase Cycles Fully Static Operation: 0 Hz to 24 MHz Three-level Program Memory Lock 128 x 8-bit Internal RAM 32 Programmable I/O Lines Two 16-bit Timer/Counters Six Interrupt Sources Programmable Serial Channel Low-power Idle and Power-down Modes 2.2 DESCRIPTION: The AT89C51 is a low-power, high-performance CMOS 8-bit Microcomputer with 4K bytes of Flash programmable and erasable read only memory (PEROM). The device is manufactured using Atmels high-density nonvolatile memory technology and is compatible with the industry-standard MCS-51 instruction set and pin out. The onchip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89C51 is a powerful microcomputer which provides a highly-flexible and cost-effective solution to many embedded control applications

2.3 PIN DIAGRAM:

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2.4 PIN DESCRIPTION: VCC - Supply voltage. GND - Ground. PORT 0: Port 0 is an 8-bit open-drain bi-directional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high impedance inputs. Port 0 may also be configured to be the multiplexed low order address/data bus during accesses to external program and data memory. In this mode P0 has internal pull-ups. Port 0 also receives the code bytes during Flash programming, and outputs the code bytes during program verification. External pull-ups are required during program verification.

PORT 1
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Port 1 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pull-ups Port 1 also receives the low-order address bytes during Flash programming and verification. PORT 2 Port 2 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pull-ups. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that uses 16-bit addresses (MOVX @ DPTR). In this application, it uses strong internal pull-ups when emitting 1s. During accesses to external data memory that uses 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits and some control signals during Flash programming and verification. PORT 3 Port 3 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the pull-ups. Port 3 also serves the functions of various special features of the AT89C51 as listed below: Port 3 also receives some control signals for Flash programming and verification.

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RST Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device. ALE/PROG Address Latch Enable output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming. In normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency, and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external Data Memory. If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode. PSEN Program Store Enable is the read strobe to external program memory. When the AT89C51 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory.

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EA/VPP External Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped to VCC for internal program executions. This pin also receives the 12-volt programming enable voltage (VPP) during Flash programming, for parts that require 12-volt VPP. 2.5 OSCILLATOR: XTAL1 Input to the inverting oscillator amplifier and input to the internal clock operating circuit. XTAL2 Output from the inverting oscillator to amplifier. 2.5.1 OSCILLATOR CHARACTERISTICS XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in Figure 1. Either quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 2. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flipflop, but minimum and maximum voltage high and low time specifications must be observed.

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2.5.2 OSCILLATOR CONNECTIONS:

2.6 IDLE MODE In idle mode, the CPU puts itself to sleep while all the on chip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and the entire special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset. It should be noted that when idle is terminated by a hard ware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory. 2.7 EXTERNAL CLOCK DRIVE CONFIGURATIONS:

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2.8 BLOCK DIAGRAM:

The AT89C51 provides the following standard features: 4K bytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bit timer/counters, five vector two-level interrupt architecture, a full duplex serial port, and on-chip oscillator and clock circuitry. In addition, the AT89C51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt system

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to continue functioning. The Power Down Mode saves the RAM contents but freezes the oscillator disabling all other chip functions until the next hardware reset 2.9 POWER-DOWN MODE: In the power-down mode, the oscillator is stopped, and the instruction that invokes power-down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the power-down mode is terminated. The only exit from power-down is a hardware reset. Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize. 2.10 PROGRAM MEMORY LOCK BITS: On the chip are three lock bits which can be left unprogrammed (U) or can be programmed (P) to obtain the additional features listed in the table below. When lock bit 1 is programmed, the logic level at the EA pin is sampled and latched during reset. If the device is powered up without a reset, the latch initializes to a random value, and holds that value until reset is activated. It is necessary that the latched value of EA be in agreement with the current logic level at that pin in order for the device to function properly.

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2.11 PROGRAMMING THE FLASH The AT89C51 is normally shipped with the on-chip Flash memory array in the erased state (that is, contents = FFH) and ready to be programmed. The programming interface accepts either a high-voltage (12-volt) or a low-voltage (VCC) program enable signal. The low voltage programming mode provides a convenient way to program the AT89C51 inside the users system, while the high-voltage programming mode is compatible with conventional third party Flash or EPROM programmers. The AT89C51 is shipped with either the high-voltage or low-voltage programming mode enabled. The respective top-side marking and device signature codes are listed in the following table.

The AT89C51 code memory array is programmed byte-by byte in either programming mode. To program any nonblank byte in the on-chip Flash Memory, the entire memory must be erased using the Chip Erase Mode. 2.11.1 PROGRAMMING ALGORITHM: Before programming the AT89C51, the address, data and control signals should be set up according to the Flash programming mode table and Figures 3 and 4. To program the AT89C51, take the following steps.

Input the desired memory location on the address lines.

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 Input the appropriate data byte on the data lines. Activate the correct combination of control signals. Raise EA/VPP to 12V for the high-voltage programming mode. Pulse ALE/PROG once to program a byte in the Flash array or the lock bits. The byte-write cycle is self-timed and typically takes no more than 1.5ms. Repeat steps 1 through 5, changing the address and data for the entire array or until the end of the object file is reached. DATA POLLING: The AT89C51 features Data Polling to indicate the end of a write cycle. During a write cycle, an attempted read of the last byte written will result in the complement of the written datum on PO.7. Once the write cycle has been completed, true data are valid on all outputs, and the next cycle may begin. Data Polling may begin any time after a write cycle has been initiated. READY/BUSY: The progress of byte programming can also be monitored by the RDY/BSY output signal. P3.4 is pulled low after ALE goes high during programming to indicate BUSY. P3.4 is pulled high again when programming is done to indicate READY. PROGRAM VERIFY: If lock bits LB1 and LB2 have not been programmed, the programmed code data can be read back via the address and data lines for verification. The lock bits cannot be verified directly. Verification of the lock bits is achieved by observing that their features are enabled. CHIP ERASE: The entire Flash array is erased electrically by using the proper combination of control signals and by holding ALE/PROG low for 10ms. The code array is written with all 1s. The chip erase operation must be executed before the code memory can be reprogrammed.

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READING THE SIGNATURE BYTES: The signature bytes are read by the same procedure as a normal verification of locations 030H, 031H, and 032H, except that P3.6 and P3.7 must be pulled to a logic low. The values returned are as follows. (030H) = 1EH indicates manufactured by Atmel (031H) = 51H indicates 89C51 (032H) = FFH indicates 12V programming (032H) = 05H indicates 5V programming 2.11.2 PROGRAMMING INTERFACE Every code byte in the Flash array can be written and the entire array can be erased by using the appropriate combination of control signals. The write operation cycle is self timed and once initiated, will automatically time itself to completion. All major programming vendors offer worldwide support for the Atmel microcontroller series. Please contact your local programming vendor for the appropriate software revision. 2.12 SPECIAL FUNCTION REGISTERS A map of the on-chip memory area called the Special Function Register (SFR). Note that not all of the addresses are occupied, and unoccupied addresses may not be implemented on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect. User software should not write 1s to these unlisted locations, since they may be used in future products to invoke new features. In that case, the reset or inactive values of the new bits will always be 0.

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TIMER 2 REGISTERS Control and status bits are contained in registers T2CON and T2MOD for Timer 2. The register pair (RCAP2H, RCAP2L) is the Capture/Reload registers for Timer 2 in 16-bit capture mode or 16-bit auto-reload mode. INTERRUPT REGISTERS The individual interrupt enable bits are in the IE register. Two priorities can be set for each of the six interrupt sources in the IP register. 2.13 DATA MEMORY The AT89C52 implements 256 bytes of on-chip RAM. The upper 128 bytes occupy a parallel address space to the Special Function Registers. That means the upper 128bytes have the same addresses as the SFR space but are physically separate from SFR space. When an instruction accesses an internal location above address 7FH, the address mode used in the instruction specifies whether the CPU accesses the upper 128 bytes of RAM or the SFR space. Instructions that use direct addressing access SFR space. For example, the following direct addressing instruction accesses the SFR at location 0A0H (which is P2). MOV 0A0H, #data Instructions that use indirect addressing access the upper 128 bytes of RAM. For example, the following indirect addressing instruction, where R0 contains 0A0H, accesses the data byte at address 0A0H, rather than P2 (whose address is 0A0H). MOV @R0, #data Note that stack operations are examples of indirect addressing, so the upper 128 bytes of data RAM are available as stack space.

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TIMER 0 AND 1 Timer 0 and Timer 1 in the AT89C52 operate the same way as Timer 0 and Timer 1 in the AT89C51. TIMER 2 Timer 2 is a 16-bit Timer/Counter that can operate as either a timer or an event counter. The type of operation is selected by bit C/T2 in the SFR T2CON (shown in Table 2). Timer 2 has three operating modes: capture, auto-reload (up or down counting), and baud rate generator. The modes are selected by bits in T2CON, as shown in Table 3. Timer 2 consists of two 8-bit registers, TH2 and TL2. In the Timer function, the TL2 register is incremented every machine cycle. Since a machine cycle consists of 12 oscillator periods, the count rate is 1/12 of the oscillator frequency. In the Counter function, the register is incremented in response to a 1-to-0 transition at its corresponding external input pin, T2. In this function, the external input is sampled during S5P2 of every machine cycle. When the samples show a high in one cycle and a low in the next cycle, the count is incremented. The new count value appears in the register during S3P1 of the cycle following the one in which the transition was detected. Since two machine cycles (24 oscillator periods) are required to recognize a 1-to-0 transition, the maximum count rate is 1/24 of the oscillator frequency. To ensure that a given level is sampled at least once before it changes, the level should be held for at least one full machine cycle. 2.14 CAPTURE MODES In the capture mode, two options are selected by bit EXEN2 in T2CON. If EXEN2 = 0, Timer 2 is a 16-bit timer or counter which upon overflow sets bit TF2 in T2CON. This bit can then be used to generate an interrupt. If EXEN2 = 1, Timer 2 performs the same operation, but a 1-to-0 transition at external input T2EX also causes the current value in TH2 and TL2 to be captured into RCAP2H and RCAP2L, respectively. In addition, the transition at T2EX causes bit EXF2 in T2CON to be set. The EXF2 bit, like TF2, can generate an interrupt.

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AUTO-RELOAD (UP OR DOWN COUNTER) Timer 2 can be programmed to count up or down when configured in its 16-bit auto-reload mode. This feature is invoked by the DCEN (Down Counter Enable) bit located in the SFR T2MOD (see Table 4). Upon reset, the DCEN bit is set to 0 so that timer 2 will default to count up. When DCEN is set, Timer 2 can count up or down, depending on the value of the T2EX pin. TIME IN CAPTURE MODE: Timer 2 automatically counting up when DCEN = 0. In this mode, two options are selected by bit EXEN2 in T2CON. If EXEN2 = 0, Timer 2 counts up to 0FFFFH and then sets the TF2 bit upon overflow. The overflow also causes the timer registers to be reloaded with the 16-bit value in RCAP2H and RCAP2L. The values in Timer in Capture ModeRCAP2H and RCAP2L are preset by software. If EXEN2 = 1, a 16-bit reload can be triggered either by an overflow or by a 1-to-0 transition at external input T2EX. This transition also sets the EXF2 bit. Both the TF2 and EXF2 bits can generate an interrupt if enabled. Setting the DCEN bit enables Timer 2 to count up or down, as shown in Figure 3. In this mode, the T2EX pin controls the direction of the count. Logic 1 at T2EX makes Timer 2 count up. The timer will overflow at 0FFFFH and set the TF2 bit. This overflow also causes the 16-bit value in RCAP2H and RCAP2L to be reloaded into the timer registers, TH2 and TL2, respectively. Logic 0 at T2EX makes Timer 2 count down. The timer underflows when TH2 and TL2 equal the values stored in RCAP2H and RCAP2L. The underflow sets the TF2 bit and causes 0FFFFH to be reloaded into the timer registers. The EXF2 bit toggles whenever Timer 2 overflows or underflows and can be used as a 17th bit of resolution. In this operating mode, EXF2 does not flag an interrupt.

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2.15 PROGRAMMABLE CLOCK OUT A 50% duty cycle clock can be programmed to come out on P1.0, as shown in Figure 5. This pin, besides being a regular I/O pin, has two alternate functions. It can be programmed to input the external clock for Timer/Counter 2 or to output a 50% duty cycle clock ranging from 61 Hz to 4MHz at a 16 MHz operating frequency. To configure the Timer/Counter 2 as a clock generator, bit C/T2 (T2CON.1) must be cleared and bit T2OE (T2MOD.1) must be set. Bit TR2 (T2CON.2) starts and stops the timer. The clock-out frequency depends on the oscillator frequency and the reload value of Timer 2 capture registers (RCAP2H, RCAP2L), as shown in the following equation

In the clock-out mode, Timer 2 roll-overs will not generate an interrupt. This behavior is similar to when Timer 2 is used as a baud-rate generator. It is possible to use Timer 2 s a baud-rate generator and a clock generator simultaneously. Note, however, that the baud-rate and clock-out frequencies cannot be determined independently from one another since they both use RCAP2H and RCAP2L.

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UART The UART in the AT89C52 operates the same way as the UART in the AT89C51. 2.16 INTERRUPTS The AT89C52 has a total of six interrupt vectors: two external interrupts (INT0 and INT1), three timer interrupts (Timers 0, 1, and 2), and the serial port interrupt. These interrupts are all shown in Figure 6. Each of these interrupt sources can be individually enabled or disabled by setting or clearing a bit in Special Function Register IE. IE also contains a global disable bit, EA, which disables all interrupts at once. Note that Table shows that bit position IE.6 is unimplemented. In the AT89C51, bit position IE.5 is also unimplemented. User software should not write 1s to these bit positions, since they may be used in future AT89 products. Timer 2 interrupt is generated by the logical OR of bits TF2 and EXF2 in register T2CON. Neither of these flags is cleared by hardware when the service routine is vectored to. In fact, the service routine may have to determine whether it was TF2 or EXF2 that generated the interrupt, and that bit will have to be cleared in software. The Timer 0 and Timer 1 flags, TF0 and TF1, are set at S5P2 of the cycle in which the timers overflow. The values are then polled by the circuitry in the next cycle. However, the Timer 2 flag, TF2, is set at S2P2 and is polled in the same cycle in which the timer overflows. RELAY DRIVER 3.7.1 FEATURES: Seven darlingtons per package Output current 500ma per driver(600ma peak) Output voltage 50v integrated suppression diodes for Inductive loads outputs can be paralleled for Higher current Ttl/cmos/pmos/dtl compatible inputs inputs pinned opposite outputs to Simplify layout.

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3.7.2 DESCRIPTION: The ULN2001A, ULN2002A, ULN2003 and ULN2004A are high voltage, high current darlington arrays each containing seven open collector darlington pairs with common emitters. Each channel rated at 500mA and can withstand peak currents of 600mA. Suppression diodes are included for inductive load driving and the inputs are pinned opposite the outputs to simplify board layout. The four versions interface to all common logic families These versatile devices are useful for driving a wide range of loads including solenoids, relays DC motors, LED displays filament lamps, thermal printheads and high power buffers. The ULN2001A/2002A/2003A and 2004A are supplied in 16 pin plastic DIP packages with a copper leadframe to reduce thermal resistance. They are available also in small outline package

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4.PIR SENSOR
4.1GENERAL DESCRIPTION: The PIR (Passive Infra-Red) Sensor is a pyroelectric device that detects motion by measuring changes in the infrared levels emitted by surrounding objects. This motion can be detected by checking for a high signal on a single I/O pin. 4.2FEATURES: Single bit output Small size makes it easy to conceal Compatible with all Parallax microcontrollers

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4.5CONNECTING AND TESTING Connect the 3-pin header to your circuit so that the minus (-) pin connects to ground or Vss, the plus (+) pin connects to +5 volts or Vdd and the OUT pin connects to your microcontrollers I/O pin. One easy way to do this would be to use a standard servo/LCD extension cable, available separately from Parallax(#805-00002). This cable makes it easy to plug sensor into the servo headers on our Board Of Education or Professional Development Board. If you use the Board Of Education, be sure the servo voltage jumper (located between the 2 servo header blocks) is in the Vdd position, not Vin. If you do not have this jumper on your board you should manually connect to Vdd through the breadboard. CALIBRATION The PIR Sensor requires a warm-up time in order to function properly. This is due to the settling time involved in learning its environment. This could be anywhere from 10-60 seconds. During this time there should be as little motion as possible in the sensors field of view. SENSITIVITY The PIR Sensor has a range of approximately 20 feet. This can vary with environmental conditions. The sensor is designed to adjust to slowly changing conditions that would happen normally as the day progresses and the environmental conditions change, but responds by toggling its output when sudden changes occur, such as when there is motion.

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Features:

The automatic sensor: to enter the sensor output range is high, people leave the sensor range of the automatic delay off high, output low.

The photosensitive control (optional, factory is not set) may set the photosensitive control during the day or light intensity without induction.

5.ULTRASONIC DISTANCE SENSOR

The Parallax PING))) ultrasonic distance sensor provides precise, non-contact distance measurements from about 2 cm (0.8 inches) to 3 meters (3.3 yards). It is very easy to connect to BASIC Stamp or Javelin Stamp microcontrollers, requiring only one I/O pin. The PING))) sensor works by transmitting an ultrasonic (well above human hearing range) burst and providing an output pulse that corresponds to the time required for the burst echo to return to the sensor. By measuring the echo pulse width the distance to target can easily be calculated. Features Supply Voltage 5 VDC Supply Current 30 mA typ; 35 mA max Range 2 cm to 3 m (0.8 in to 3.3 yrds) Input Trigger positive TTL pulse, 2 uS min, 5 s typ. Echo Pulse positive TTL pulse, 115 uS to 18.5 ms Echo Hold-off 750 s from fall of Trigger pulse Burst Frequency 40 kHz for 200 s Burst Indicator LED shows sensor activity Delay before next measurement 200 s Size 22 mm H x 46 mm W x 16 mm D (0.84 in x 1.8 in x 0.6 in)
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The PING))) sensor has a male 3-pin header used to supply power (5 VDC), ground, and signal. The header allows the sensor to be plugged into a solderless breadboard, or to be located remotely through the use of a standard servo extender cable (Parallax part #805-00002). Standard connections are show in the diagram to the right.

QUICK-START CIRCUIT :

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This circuit allows you to quickly connect your PING))) sensor to a BASIC Stamp 2 via the Board of Education breadboard area. The PING))) modules GND pin connects to Vss, the 5 V pin connects to Vdd, and the SIG pin connects to I/O pin P15.

5.1 THEORY OF OPERATION The PING))) sensor detects objects by emitting a short ultrasonic burst and then "listening" for the echo. Under control of a host microcontroller (trigger pulse), the sensor emits a short 40 kHz (ultrasonic) burst. This burst travels through the air at about 1130 feet per second, hits an object and then bounces back to the sensor. The PING))) sensor provides an output pulse to the host that will terminate when the echo is detected, hence the width of this pulse corresponds to the distance to the target.

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6.ZIGBEE TECHNOLOGY
The CC2520 is TI's second generation ZigBee / IEEE 802.15.4 RF transceiver for the 2.4 GHz unlicensed ISM band. This chip enables industrial grade applications by offering state-of-the-art selectivity/co-existence, excellent link budget, operation up to 125C and low voltage operation. In addition, the CC2520 provides extensive hardware support for frame handling, data buffering, burst transmissions, data encryption, data authentication, clear channel assessment, link quality indication and frame timing information. These features reduce the load on the host controller. 6.1 FEATURES: Integrated 2.4 GHz ,IEEE 802,15,4-compliant transceiver: 0 dBm nominal TX output power -92 dBm RX sensitivity + 2 dBm in boost mode RX filtering for co-existence with IEEE 802.11g and Bluetooth devices Integrated VCO and loop filter Integrated IEEE 802.15.4 PHY and MAC Controlled by a Standard Serial Line for an
easy interface of host microcontrollers (SPI) 36

 Embedded flash and integrated RAM for program and data storage On board 24 MHz stable Xtal Integrated RC oscillator ( typ 10 kHz) for low power operation 1 A power consumption in Deep sleep mode
Watchdog timer and power on reset

Pins available for Non-intrusive debug interface (SIF) Single supply voltage 2.1 to 3.6 Vdc.

Available Link and Activity outputs for external Indication / monitor CE compliant SPZB260 is a low power consumption ZigBeemodule optimized for embedded

6.2 DESCRIPTION: applications. It enables OEMs to easily add wireless capability to electronic devices. The module is based on SN260 ZigBee Network Processor which integrates a 2.4 GHz, IEEE 802.15.4-compliant transceiver as well as IEEE 802.15.4 PHY and MAC. 24 MHz high stability Xtal is available aboard the module to perform the timing requirements as per ZigBee specifications. A single supply voltage is requested to power the module.

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An integrated 2.5 GHz specific Murata antenna is aboard. The voltage supply also determines the I/O ports level allowing an easy interface with the host system. The module is controlled by means of a standard serial interface (SPI) allowing the connections to a variety of Host microcontrollers.

6.3 NEED FOR ZIGBEE TECHNOLOGY: Zigbee is the only wireless standards-based technology that addresses the unique needs of remote monitoring and control, sensory network applications. Sensors and controls dont need high bandwidth but they do need low latency and very low energy consumption for long battery lives and for large device arrays. There are a multitude of standards that address mid to high data rates for voice, PCLANs, video, etc. However, up till now there hasnt been a wireless network standard that meets the unique needs of sensors and control devices. There are a multitude of proprietary wireless systems manufactured today to solve a multitude of problems that also dont require high data rates but do require low cost and very low current drain. This network has large number of nodes when compared to other technologies. It is easy to deploy and configure i.e., if any new node enters into the network it automatically senses and configure it.

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6.4 PIN DESCRIPTION:

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MAXIMUM RATINGS:
ABSOLUTE MAXIMUM RATINGS:

OPERATING RANGES:

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7. SOFTWARE REQUIREMENTS
7.1 EMBEDDED C: Use of embedded processors in passenger cars, mobile phones, medical equipment, aerospace systems and defence systems is widespread, and even everyday domestic appliances such as dish washers, televisions, washing machines and video recorders now include at least one such device. There is a large - and growing international demand for programmers with 'embedded' skills, and many desktop developers are starting to move into this important area. These popular chips have very limited resources available: most such devices have around 256 bytes of RAM, and the available processor power is around 1000 times less than that of a desktop processor. As a result, developing embedded software presents significant new challenges, even for experienced desktop programmers. 7.1.1KEY FEATURES

Covers key techniques required in all embedded systems in detail, including the control of port pins and the reading of switches. Presents a complete embedded operating system which uses less than 1% of the available processor power of an embedded 8051 microcontroller. Covers the microcontroller serial interface, which is widely used for debugging embedded systems, as well as for system maintenance and in data acquisition applications.

Includes a substantial and realistic case study. Uses 100% C code: no knowledge of assembly language is needed. An industrystandard C compiler from Keil Software is also included on the CD, along with copies of the source code.

Includes a copy of the Keil hardware simulator for the 8051 microcontroller on the CD.

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7.2 KEIL COMPILER 7.2.1 HOW TO INSTALL THE COMPILER AND SIMULATOR We use the standard Keil C compiler. From the CD menu, please choose 'Install Evaluation Software': this does not require a serial number. The evaluation software is not 'time limited' (that is, it will work "forever"): its main restriction is the size of the 'executable' file you can create. This size restriction is quite generous, and we will be able to compile and simulate all of the code your own without difficulty. The Keil Compilers support all 8051, 251, C16x/ST10, and compatible devices. The Keil Compiler generates code for any device that is compatible with the 8051, 251, C16x/ST10, or ARM microcontrollers. The only exception to this would be a device that has removed or altered the instruction set. However, that device would no longer be a compatible part. First select a chip from the database then we are constantly updating the database and adding new parts. To ensure that we always have the latest database from the keil. If the latest software's Device Database does not include the part we use, you may add a Device Database entry. The Device Database is simply a way to specify the default compiler, assembler, and linker settings. For new devices, you may simply copy the settings for a similar device. Each microcontroller has its own unique set of Special Function Registers. The SFRs for a chip may be identical to those of another device. Keil Software provides custom header files that define the SFRs for almost every 8051, 251, and C16x compatible device. However, there may be new devices for which we have not yet created a header file. That does not mean that this chip is not supported. Creating header files for new devices is easy. When support is not yet available, we may use new devices the compatible mode of operation. When support is integrated into the compiler assembler, and linker, the device database will be updated with the appropriate controls.

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Once we compile, assemble, and link your program, you will need a method of testing it. The Keil Vision IDE supports two distinct methods of program testing: simulation and target debugging. In simulation, Keil Software or the silicon vendor has created a DLL that simulates the on-chip peripherals of the selected device. With over 350 devices in the database, it is impossible to provide simulation support for all of them. However, it is our goal to simulate as many as possible. Even if complete simulation is not available, partial simulation (base timers, counters, interrupts, and I/O ports) are supported

8. FUTURE ENHANCEMENT:
This project is to design a robotic system for military applications using zigbee technology. Here in this project robot is controlled through PC. And to implement a system in military areas and also to monitor the locations by using cam which is connected to robot. And also we can implement a system in which a robot direction can be controlled wirelessly with respect to the commands given by the user through PC using Zigbee technology

9. BIBLIOGRAPHY: The 8051 Micro controller and Embedded Systems-Muhammad Ali MazidiJanice Gillispie Mazidi The 8051 Micro controller Architecture, Programming & Applications -Kenneth J.Ayala Fundamentals Of Microprocessors and Microcomputers-B.Ram Microprocessor Architecture, Programming& Applications -Ramesh S.Gaonkar Electronic Components-D.V.Prasad Wireless Communications- Theodore S. Rappaport
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10 .CONCLUSION
A technology which gives full protection to the Robotic developed. Through this the theft can be identified with exact location as well it can be avoided. The second lock security system which is incorporated will give full protection to the vehicle as well it this can be implemented with a minimum cost and maintenance is also quite easy.

11.REFERENCES : www.national.com www.atmel.com www.microsoftsearch.com www.geocities.com

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