Dell Inspiron 1545 Wistron DR1 (Roberts)

5
DR1 (Roberts) Schematics Document

uFCPGA Mobile Penryn
Intel Cantiga-GM + ICH9M
C
2008-10-02
REV : A00
B
DY : Nopop Component
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
Document Number
Custom
Cover Page
Date: Thursday, October 02, 2008

5
Rev
A00
Roberts
Sheet
1
of
58
CPU DC/DC
Roberts Block Diagram

D
Socket P
28,29
INPUTS
OUTPUTS
+PWR_SRC
+VCC_CORE
SYSTEM DC/DC
Project code : 91.4AQ01.001

PCB P/N
: 48.4AQ01.011
Revision
: 08212-1
Intel Mobile CPU

Penryn
Clock Generator
SLG8SP513VTR 4
ISL6266A
TPS51117
30
INPUTS
OUTPUTS
+PWR_SRC
+1.05V_VCCP
5,6,7
SYSTEM DC/DC
MAX17020
FSB
800/1066MHz
INPUTS
OUTPUTS
+5V_ALW2
+3.3V_RTC_LDO
+5V_ALW
+3.3V_ALW
+PWR_SRC
DDRII
667/800
Slot 0
14
DDRII 667/800 Channel A
Intel
Cantiga-GML
SYSTEM DC/DC
CRT
(on I/O board)
RGB CRT
TPS51116
Power SW
AGTL+ CPU I/F
DDRII
667/800
Slot 1
15
LVDS(Dual Channel)
DDR Memory I/F
DDR II 667/800 Channel B
G577BR91U
LCD
27
INPUTS
41
35
31
OUTPUTS
+1.8V_SUS
+0.9V_DDR_VTT
+V_DDR_MCH_REF
+PWR_SRC
External Graphics
8,9,10,11,12,13
PCIE x 1 & USB 2.0 x 1
PCIE x 1
10/100 NIC
Marvell 88E8040
SD/MMC
MS/MS Pro/xD
USB2.0
Realtek
RTS5158E
37
Digital Mic Array

MIC IN
CAMERA
(Option)
USB 2.0 x 1
USB 2.0
SATA ports (4)
OUTPUTS
+5V_ALW
+5V_RUN
+3.3V_ALW
+3.3V_RUN
37
MAX8731A
26
41
INPUTS
OUTPUTS
+DC_IN
LPC I/F
+PWR_SRC
ACPI 1.1
+PBATT
USB 2.0 x 1
Bluetooth
41
USB 2.0 x 1
Right Side:
USB x 1
43
PCI/PCI BRIDGE
IDT
92HD71B7
LPC Bus
16,17,18,19
22
Internal Analog MIC
34
MAXIM CHARGER
PCI Express ports (6)
AZALIA
+1.5V_RUN
LDO
Mini-Card
PCIE x 1
High Definition Audio
Azalia
CODEC
+1.8V_SUS
SYSTEM DC/DC
USB 2.0/1.1 ports (12)
CAMERA Module
OUTPUTS
INPUTS
ICH9-M
32
INPUTS
Left Side:
USB x 2
41
PCIE
APL5912
RJ45
CONN
802.11a/b/g
21
20
USB 2.0 x 2
Intel
CardReader
SYSTEM DC/DC
41
I/O Board
Connector
C-LINK
DMIx4
New Card
PCB LAYER
L1: Top
OP AMP
MAX9789A
SATA
HP1
SATA
L2: VCC
L3: Signal
KBC
SPI
WINBOND
L4: Signal
24
WPCE773L
L5: GND
23
L6: Bottom
A
<Core Design>
2CH SPEAKER
HDD
36
ODD
36
Flash ROM
2MB 42
Touch
PAD
44
Int.
KB
Thermal & Fan

EMC2102
44
Wistron Corporation
25
40
Title
Block Diagram
Size
Document Number
Custom

5
Rev
A00
Roberts
Sheet
1
of
58
ICH9M Functional Strap Definitions
ICH9 EDS 642879
Rev.1.5
Montevina Platform Design guide 22339 Rev.0.5
Resistor Type/Value
Pin Name
Strap Description
PULL-UP 20K
CFG[2:0]
FSB Frequency Select 000 = FSB1067

011 = FSB667
010 = FSB800
others = Reserved
Usage/When Sampled
HDA_SDOUT
XOR Chain Entrance/

Allows entrance to XOR Chain testing when TP3
PCIE Port Config1 bit1, pulled low. When TP3 not pulled low at rising edge
Rising Edge of PWROK.
of PWROK, sets bit1 of RPC.PC (Cofig Registers:
offset 224h). This signal has weak internal
pull-down.
CL_CLK[1:0]
PCIE config1 bit0,

ENERGY_DETECT
PULL-UP 20K
Reserved
CFG[4:3]
CFG8
CFG[15:14]
CFG[18:17]
HDA_BIT_CLK
PULL-DOWN 20K
CFG5
DMI x2 Select
0 = DMI x2
1 = DMI x4 (Default)
HDA_DOCK_EN#/GPIO33
PULL-UP 20K
CFG6
iTPM Host Interface
HDA_RST#
PULL-DOWN 20K
0 = The iTPM Host Interface is enabled (Note 2)

1 = The iTPM Host Interface is disabled (default)
HDA_SDIN[3:0]
PULL-DOWN 20K
CFG7
HDA_SDOUT
PULL-DOWN 20K
Intel Management
engine crypto strap
0 = Transport Layer Security (TLS) cipher

suite with no confidentiality
1 = TLS cipher suite with confidentiality(Default)
HDA_SYNC
PULL-DOWN 20K
CFG9
PCIE Graphics Lane
GLAN_DOCK#
The pull-up or pull-down

active when configured
for native GLAN_DOCK#
functionality and determined
by LAN controller.
0 = Reserved Lanes, 15->0, 14->1 ect..

1 = Normal operation (Default): Lane Numbered in
Order
CFG10
PCIE Loopback enable 0 = Enable (Note 3)

1 = Disable (Default)
HDA_SYNC
This signal has a weak internal pull-down.

Sets bit0 of PRC.PC (Config Registers: Offset
224h).
GNT2#/
GPIO53
PCIE config2 bit2,

This signal has a weak internal pull-up.

Sets bit2 of PRC.PC2 (Config Registers: Offset
224h).
GPIO20
Reserved.
This signal should not be pulled high.
GNT1#/
GPIO51
ESI Strap (Server Only) ESI compatible mode is for server platforms only.
This signal should not be pulled low for desktop
and mobile.
GNT3#/
GPIO55
Top-Block Swap
override. Rising Edge
of PWROK.
Sampled low: Top-Block Swap mode (inverts A16 for

all cycles targeting FWH BIOS space).
Note: Software will not be able to clear the
Top-Swap bit until the system is rebooted
without GNT3# being pulled down.
SIGNAL
CL_DATA[1:0]
PULL-UP 20K
CL_RST0#
PULL-UP 20K
DPRSLPVR/GPIO16
PULL-DOWN 20K
GNT[3:0]#/GPIO[55,53,51]
PULL-UP 20K
GPIO20
PULL-DOWN 20K
GPIO49
PULL-UP 20K
LDA[3:0]#/FHW[3:0]#
PULL-UP 20K
GNT0#:
SPI_CS1#/
GPIO58
Boot BIOS Destination

Selection 0:1.
SPI_MOSI
Integrated TPM Enable, Sample low: the Integrated TPM will be disable.
Rising Edge of CLPWROK. Sample high: the MCH TPM enable strap is sampled
low and the TPM Disable bit is clear, the
Integrated TPM will be enable.
LAN_RXD[2:0]
PULL-UP 20K
LDRQ[0]
PULL-UP 20K
LDRQ[1]/GPIO23
PULL-UP 20K
DMI Termination
Voltage. Rising Edge
of CLPWROK.
PME#
PULL-UP 20K
PWRBTN#
PULL-UP 20K
SATALED#
PULL-UP 15K
SPI_CS1#/GPIO58/CLGPIO6
PULL-UP 20K
GPIO49
SATALED#
SPKR
TP3
Rev.1.5
Cantiga chipset and ICH9M I/O controller

Hub strapping configuration
Signal
ICH9 EDS 642879

Comment
ICH9 Integrated pull-up

and pull-down Resistors
GPIO33/
HDA_DOCK
_EN#
Controllable via Boot BIOS Destination bit

(Config Registers: Offset 3410h:bit 11:10).
GNT0# is MSB, 01-SPI, 10-PCI, 11-LPC
The signal is required to be low for desktop

applications and required to be high for mobile
applications.
PCI Express Lane

Reversal. Rising Edge
of PWROK.
Signal has weak internal pull-up. Sets bit 27

of MPC.LR (Device 28: Function 0:Offset D8).
SPI_MOSI
PULL-DOWN 20K
No Reboot.
If sampled high, the system is strapped to the

"No Reboot" mode (ICH9 will disable the TCO Timer
system reboot feature). The status is readable
via the NO REBOOT bit.
SPI_MISO
PULL-UP 20K
SPKR
PULL-DOWN 20K
TACH_[3:0]
PULL-UP 20K
XOR Chain Entrance.

Flash Descriptor
Security Override
Strap. Rising Edge of
PWROK.
This signal should not be pull low unless using

XOR Chain testing.
Sampled low: the Flash Descriptor Security will be
overridden. If high, the security measures will be
in effect. This should only be enabled in
manufacturing environments using an external
pull-up resister.
TP[3]
PULL-UP 20K
USB[11:0][P,N]
PULL-DOWN 15K
PCIE Routing
Configuration
CFG[13:12] XOR/ALL
00
10
01
11
CFG16
FSB Dynamic ODT
0 = Dynamic ODT Disabled

1 = Dynamic ODT Enabled (Default)
CFG19
DMI Lane Reversal
0 = Normal operation (Default): Lane Numbered in

Order
1 = Reverse Lanes
DMI x4 mode [MCH->ICH]: (3->0, 2->1, 1->2 and 0->3)
DMI x2 mode [MCH->ICH]: (3->0, 2->1)
CFG20
Digital Display Port 0 = Only Digital Display Port or PCIE is

operational (Default)
(SDVO/DP/iHDMI)
display Port and PCIe are operating
Concurrent with PCIe 1 = Digital
simulataneously via the PEG port
SDVO
SDVO Present
_CTRLDATA
L_DDC_DATA Local Flat Panel
(LFP) Present
=
=
=
=
Reserve
XOR mode Enabled
ALLZ mode Enable (Note 3)
Disabled (Default)
0 = No SDVO Card Present (Default)

1 = SDVO Card Present
0 = LFP Disabled (Default)
1 = LFP Card Present; PCIE disabled
NOTE:
1. All strap signals are sampled with respect to the leading edge of the (G)MCH
Power OK (PWROK) signal.
2. iTPM can be disabled by a 'Soft-Strap' option in the Flash-decriptor section of
the Firmware. This 'Soft-Strap' is activated only after enabling iTPM via CFG6.
Only one of the CFG10/CFG12/CFG13 straps can be enabled at any time.
USB Table
USB
LANE2
MiniCard WLAN
LANE3
LAN
LANE5
New Card
Pair
0
1
2
3
4
5
6
7
8
9
10
11
Device
USB1
USB2
USB3
RESERVED
MINI CARD
RESERVED
BLUETOOTH
NEW CARD
RESERVED
RESERVED
Card Reader
CAMERA
<Core Design>
Wistron Corporation
Title
Size
Document Number
Custom
Table of Content
Rev
A00
Roberts
Sheet
of
58
3D3V_S0_CK505_IO
NEWCARD_CLKREQ#
CLK_PCIE_NEW
CLK_PCIE_NEW#
3D3V_S0_CK505_IO
CLK_XTAL_IN
CLK_XTAL_OUT
R217 1
21 CLK_48M_CARD
3
2
2 22R2J-2-GP
19
27
43
52
33
56
U54
VDD96_IO
VDDPLL3_IO
VDDSRC_IO
VDDSRC_IO
VDDSRC_IO
VDDCPU_IO
4
16
9
46
62
23
C461
SC12P50V2JN-3GP
DY
VDDREF
VDD48
VDDPCI
VDDSRC
VDDCPU
VDDPLL3
1
C462
SC12P50V2JN-3GP
C237
SCD1U16V2KX-3GP
C215
SCD1U16V2KX-3GP
1
2
C209
SCD1U16V2KX-3GP
1
2
C239
SCD1U16V2KX-3GP
1
2
DY
C210
SCD1U16V2KX-3GP
X-14D31818M-37GP
1 R204
2
0R0603-PAD
C226
SC10U6D3V5MX-3GP
C229
SC1U10V3KX-3GP
X3
18
3D3V_S0_CK505
CLK_48M_ICH
18
18
C234
SCD1U16V2KX-3GP
C225
SCD1U16V2KX-3GP
1
2
C207
SCD1U16V2KX-3GP
1
2
C238
SCD1U16V2KX-3GP
1
2
C218
SCD1U16V2KX-3GP
1
2
C211
SC10U6D3V5MX-3GP
1
2
C233
SC1U10V3KX-3GP
C245
1 R200
2
0R0603-PAD
FSA
2
22R2J-2-GP
CLK_CPU_BCLK 5
CLK_CPU_BCLK# 5
CPUT1_F
CPUC1_F
58
57
CLK_MCH_BCLK 8
CLK_MCH_BCLK# 8
CPUT2_ITP/SRCT8
CPUC2_ITP/SRCC8
54
53
USB_48MHZ/FSLA
CLK_CPU_ITP 37
CLK_CPU_ITP# 37
45
44
PCI_STOP#
CPU_STOP#
SRCT7/CR#_F
SRCC7/CR#_E
51
50
CLK_PCIE_LAN 20
CLK_PCIE_LAN# 20
SRCT6
SRCC6
48
47
SRCC10
41
42
SRCT11/CR#_H
SRCC11/CR#_G
40
39
SRCT9
SRCC9
37
38
CLK_PCIE_MINI1 37
CLK_PCIE_MINI1# 37
SRCT4
SRCC4
34
35
CLK_MCH_3GPLL 9
CLK_MCH_3GPLL# 9
SRCT3/CR#_C
SRCC3/CR#_D
31
32
CLK_PCIE_ICH 16
CLK_PCIE_ICH# 16
SRCT2/SATAT
SRCC2/SATAC
28
29
CLK_PCIE_SATA 17
CLK_PCIE_SATA# 17
27MHZ_NONSS/SRCT1/SE1
27MHZ_SS/SRCC1/SE2
24
25
MCH_SSCDREFCLK 9
MCH_SSCDREFCLK# 9
SRCT0/DOTT_96
SRCC0/DOTC_96
20
21
DY 2SC4D7P50V2CN-1GP
H_STP_PCI#
H_STP_CPU#
7
6
14,15,18 ICH_SMBCLK
14,15,18 ICH_SMBDATA
18
63
CK_PWRGD
A00.08/0910
CPUT0
CPUC0
X1
X2
17
ICS9LPRS355BKLFT-GP-USRCT10
SCLK
SDATA
CK_PWRGD/PD#
2 33R2J-2-GP
2 33R2J-2-GP
27_SEL
ITP_EN
CLK_14M_ICH
R190 1
2 33R2J-2-GP
FSB
FSC
64
5
FSLB/TEST_MODE
REF0/FSLC/TEST_SEL
55
NC#55
18
15
1
22
30
36
49
59
26
GND48
GNDPCI
GNDREF
PCI0/CR#_A
PCI1/CR#_B
PCI2/TME
PCI3
PCI4/27_SELECT
PCI_F5/ITP_EN
DY
2
DY
C224
SC4D7P50V2CN-1GP
C243
SC4D7P50V2CN-1GP
DY
18
DY
CLKREQ#_1
PCI2_TME
GND
R207 1
R212 1
A00.08/0922
C236
SC4D7P50V2CN-1GP
24
16
2 475R2F-L1-GP
2 33R2J-2-GP
CLK_PCIE_NEW 41
CLK_PCIE_NEW# 41
NEWCARD_CLKREQ#
MINI1_CLKREQ# 37
41
C
CLK_MCH_DREFCLK 9
CLK_MCH_DREFCLK# 9
A00.08/0910
65
PCLK_KBC
CLK_PCI_ICH
8
10
11
12
13
14
R178 1
R196 1
GND
GNDSRC
GNDSRC
GNDSRC
GNDCPU
GND
18 CLKSATAREQ#
9
CLKREQ#_B
37
PCLK_FWH
61
60
R216
+3.3V_RUN
DY
+3.3V_RUN
+3.3V_RUN
2 10KR2J-3-GP
2 10KR2J-3-GP
3D3V_S0_CK505
R193 1
R195 1
EC57
SC22P50V2JN-4GP
NEWCARD_CLKREQ#
MINI1_CLKREQ#
SSID = CLOCK
C464
SC4D7P50V2CN-1GP
C463
SC4D7P50V2CN-1GP
Main source: 71.08513.003 (SLG8SP513VTR)

2nd source: 71.00875.C03 (RTM875N-606-VD-GRT)
3rd source:
Co-layout Ref: 71.09355.B03 (ICS9LPRS355BKLFT)
B
SRC8
CPU_ITP
PCI2_TME
DY
1
EC140
SC47P50V2JN-3GP
DY
EC139
SC47P50V2JN-3GP
PCI2_TME
R202
10KR2J-3-GP
Overclocking of CPU and SRC allowed
Overclocking of CPU and SRC not allowed
27_SEL
PIN 20
PIN 21
DOT96T
DOT96C
SRCT0
SRCC0
GM45
PM45
DY
Output
CLK_MCH_DREFCLK#
0
1
R206
10KR2J-3-GP
R198
10KR2J-3-GP
Output
1
R218
10KR2J-3-GP
DY
ITP_EN
ITP_EN
R209
10KR2J-3-GP
CLK_MCH_DREFCLK
1
27_SEL
3D3V_S0_CK505
1
3D3V_S0_CK505
SEL2 SEL1 SEL0

FSC FSB FSA
1
0
1
0
0
1
1
0
1
0
1
0
0
0
0
CPU
100M
133M
166M
200M
266M
FSB
X
533M
667M
800M
1067M
CPU_BSEL2
R186 1
2 10KR2J-3-GP
FSC
CPU_BSEL1
R412 1
2 0R2J-2-GP
FSB
CPU_BSEL0
R214 1
2 2K2R2J-2-GP
FSA
R215 1
2 1KR2J-1-GP
MCH_CLKSEL0 9
R411 1
2 1KR2J-1-GP
MCH_CLKSEL1 9
R181 1
2 1KR2J-1-GP
MCH_CLKSEL2 9
<Core Design>
Wistron Corporation
Title
Clock Generator SLG8SP513VTR
Size
Document Number
Custom

5
Rev
A00
Roberts
Sheet
1
of
58
SSID = CPU
U41A 1 OF 4
H_A#[35..3]
REQ0#
REQ1#
REQ2#
REQ3#
REQ4#
H_ADSTB#1
Y2
U5
R3
W6
U4
Y5
U1
R4
T5
T3
W2
W5
Y4
U2
V4
W3
AA4
AB2
AA3
V1
17
17
17
H_A20M#
H_FERR#
H_IGNNE#
A6
A5
C4
A20M#
FERR#
IGNNE#
17
17
17
17
H_STPCLK#
H_INTR
H_NMI
H_SMI#
D5
C6
B4
A3
STPCLK#
LINT0
LINT1
SMI#
TP30
TP31
TP13
TP23
TP21
TP24
TP19
TP55
TP25
TP34
TPAD30
TP12
RSVD_CPU_1
RSVD_CPU_2
RSVD_CPU_3
RSVD_CPU_4
RSVD_CPU_5
RSVD_CPU_6
RSVD_CPU_7
RSVD_CPU_8
RSVD_CPU_9
RSVD_CPU_10
M4
N5
T2
V3
B2
C3
D2
D22
D3
F6
RSVD_CPU_11
B1
BR0#
IERR#
INIT#
H_ADS#
H_BNR#
H_BPRI#
H5
F21
E1
H_DEFER# 8
H_DRDY# 8
H_DBSY# 8
F1
LOCK#
H4
RESET#
RS0#
RS1#
RS2#
TRDY#
C1
F3
F4
G3
G2
HIT#
HITM#
G6
E4
BPM0#
BPM1#
BPM2#
BPM3#
PRDY#
PREQ#
TCK
TDI
TDO
TMS
TRST#
DBR#
AD4
AD3
AD1
AC4
AC2
AC1
AC5
AA6
AB3
AB5
AB6
C20
PROCHOT#
THRMDA
THRMDC
THERMTRIP#
BCLK0
BCLK1
R47
2 56R2J-4-GP
H_INIT#
17
+1.05V_VCCP
H_TRDY# 8
H_HIT#
H_HITM#
ITP_BPM#0
ITP_BPM#1
ITP_BPM#2
ITP_BPM#3
ITP_BPM#4
ITP_BPM#5
ITP_TCK
ITP_TDI
ITP_TDO
ITP_TMS
ITP_TRST#
ITP_DBRESET#
R50
R51
DY
8
8
ITP_BPM#0 37
ITP_BPM#1 37
ITP_BPM#2 37
ITP_BPM#3 37
ITP_BPM#4 37
ITP_BPM#5 37
ITP_TCK 37
ITP_TDI 37
ITP_TDO 37
ITP_TMS 37
ITP_TRST# 37
ITP_DBRESET# 37
2 0R2J-2-GP
2 56R2J-4-GP
D21
A24
B25
CPU_PROCHOT# 28
H_THRMTRIP# 9,17,24,34
1
DY
2 56R2J-4-GP
C
H_THERMDA
+1.05V_VCCP
H_THERMDA 25
H_THERMDC 25
C7
A22
A21
H_LOCK# 8
H_CPURST# 8,37
H_RS#[2..0] 8
H_CPURST#
H_RS#0
H_RS#1
H_RS#2
R76
HCLK
8
8
8
H_BREQ#0 8
D20 CPU_IERR#
B3
THERMAL
ICH
TPAD30
TPAD30
TPAD30
TPAD30
TPAD30
TPAD30
TPAD30
TPAD30
TPAD30
TPAD30
A17#
A18#
A19#
A20#
A21#
A22#
A23#
A24#
A25#
A26#
A27#
A28#
A29#
A30#
A31#
A32#
A33#
A34#
A35#
ADSTB1#
ADDR GROUP 1
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
H_REQ#0 K3
H_REQ#1 H2
H_REQ#2 K2
H_REQ#3 J3
H_REQ#4 L1
DEFER#
DRDY#
DBSY#
H1
E2
G5
+1.05V_VCCP
H_ADSTB#0
H_REQ#[4..0]
ADS#
BNR#
BPRI#
H_THERMDA, H_THERMDC routing together,

Trace width / Spacing = 10 / 10 mil
DY
H_THERMDC
8
8
A3#
A4#
A5#
A6#
A7#
A8#
A9#
A10#
A11#
A12#
A13#
A14#
A15#
A16#
ADSTB0#
CONTROL
J4
L5
L4
K5
M3
N2
J1
N3
P5
P2
L2
P4
P1
R1
M1
ADDR GROUP 0
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
XDP/ITP SIGNALS
H_A#[35..3]
C49
SC2200P50V2KX-2GP
H_THRMTRIP# should connect to

ICH9 and MCH without T-ing.
A00.08/0903
CLK_CPU_BCLK 4
CLK_CPU_BCLK# 4
RSVD#M4
RSVD#N5
RSVD#T2
RSVD#V3
RSVD#B2
RSVD#C3 TEST7
RSVD#D2
RSVD#D22
RSVD#D3
RSVD#F6
RESERVED
KEY_NC
BGA479-SKT6-GPU7
62.10040.221
<Core Design>
Wistron Corporation
Title
Size
Document Number
Custom
CPU-FSB(1/3)
Rev
A00
Roberts
Sheet
of
58
SSID = CPU
H_DINV#[3..0]
H_DSTBN#[3..0]
H_DSTBP#[3..0]
H_D#[63..0]
D
H_DINV#[3..0]
H_DSTBN#[3..0]
H_DSTBP#[3..0]
H_D#[63..0]
H_DSTBN#0
H_DSTBP#0
H_DINV#0
Layout notes
Z= 55 Ohm 0.5" MAX for CPU_GTLREF0
+1.05V_VCCP
R354
2KR2F-3-GP
H_DSTBN#1
H_DSTBP#1
H_DINV#1
CPU_GTLREF0
DY
C376
SC1KP50V2KX-1GP
8
8
8
R357
1KR2F-3-GP
4
4
4
R53
R60
R58
1
1
1
R7
DY
DY
DY
DY
CPU_BSEL0
CPU_BSEL1
CPU_BSEL2
2 1KR2J-1-GP
2 1KR2J-1-GP
2 1KR2J-1-GP
TEST1
TEST2
CPU_TEST3
2 1KR2J-1-GP
CPU_TEST5
N22
K25
P26
R23
L23
M24
L22
M23
P25
P23
P22
T24
R24
L25
T25
N25
L26
M26
N24
D16#
D17#
D18#
D19#
D20#
D21#
D22#
D23#
D24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#
DSTBN1#
DSTBP1#
DINV1#
AD26
C23
D25
C24
AF26
AF1
A26
GTLREF
TEST1
TEST2
TEST3
TEST4
TEST5
TEST6
B22
B23
C21
DATA GRP1
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
DATA GRP3
8
8
8
D0#
D1#
D2#
D3#
D4#
D5#
D6#
D7#
D8#
D9#
D10#
D11#
D12#
D13#
D14#
D15#
DSTBN0#
DSTBP0#
DINV0#
DATA GRP0
E22
F24
E26
G22
F23
G25
E25
E23
K24
G24
J24
J23
H22
F26
K22
H23
J26
H26
H25
DATA GRP2
U41B 2 OF 4
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
MISC
BSEL0
BSEL1
BSEL2
D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#
DSTBN2#
DSTBP2#
DINV2#
Y22
AB24
V24
V26
V23
T22
U25
U23
Y25
W22
Y23
W24
W25
AA23
AA24
AB25
Y26
AA26
U22
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
D63#
DSTBN3#
DSTBP3#
DINV3#
AE24
AD24
AA21
AB22
AB21
AC26
AD20
AE22
AF23
AC25
AE21
AD21
AC22
AD23
AF22
AC23
AE25
AF24
AC20
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
COMP0
COMP1
COMP2
COMP3
R26
U26
AA1
Y1
COMP0
COMP1
COMP2
COMP3
DPRSTP#
DPSLP#
DPWR#
PWRGOOD
SLP#
PSI#
E5
B5
D24
D6
D7
AE6
H_DSTBN#2 8
H_DSTBP#2 8
H_DINV#2 8
H_DSTBN#3 8
H_DSTBP#3 8
H_DINV#3 8
R350
R349
R14
R13
1
1
1
1
2
2
2
2
27D4R2F-L1-GP
54D9R2F-L1-GP
27D4R2F-L1-GP
54D9R2F-L1-GP
H_DPRSTP# 9,17,28
H_DPSLP# 17
H_DPWR# 8
H_PWRGOOD 17,34
H_CPUSLP# 8
PSI#
28
Layout Note:
Comp0, 2 connect with Zo=27.4 ohm, make
trace length shorter than 0.5".
Comp1, 3 connect with Zo=55 ohm, make
trace length shorter than 0.5".
BGA479-SKT6-GPU7
62.10040.221
Route the CPU_TEST3 and CPU_TEST5 signals

through a ground referenced Zo = 55-ohm trace
that ends in a via that is near a GND via
and is accessible through an oscilloscope connection.
<Core Design>
Wistron Corporation
Title
Size
Document Number
Custom
CPU-FSB(2/3)
Rev
A00
Roberts
Sheet
of
58
SSID = CPU
1
2
1
2
C366
SC22U6D3V5MX-2GP
DY
2
C365
SC22U6D3V5MX-2GP
DY
C3
SC22U6D3V5MX-2GP
DY
C6
SC22U6D3V5MX-2GP
DY
C367
SC22U6D3V5MX-2GP
C5
SC22U6D3V5MX-2GP
C338
SC22U6D3V5MX-2GP
C370
SC22U6D3V5MX-2GP
DY
C11
SC22U6D3V5MX-2GP
DY
DY
DY
DY
DY
C10
SC22U6D3V5MX-2GP
1
2
1
2
C363
SC22U6D3V5MX-2GP
1
2
C357
SC22U6D3V5MX-2GP
C13
SC22U6D3V5MX-2GP
1
2
1
2
C35
SC22U6D3V5MX-2GP
1
2
1
2
C368
SC22U6D3V5MX-2GP
C347
SC22U6D3V5MX-2GP
1
2
C344
SC22U6D3V5MX-2GP
C340
SC22U6D3V5MX-2GP
C29
SC22U6D3V5MX-2GP
C30
SC22U6D3V5MX-2GP
C32
SC22U6D3V5MX-2GP
+1.5V_VCCA
C336
SC22U6D3V5MX-2GP
1
2
C7
SCD1U10V2KX-4GP
C9
SCD1U10V2KX-4GP
C45
SCD1U10V2KX-4GP
C43
SCD1U10V2KX-4GP
layout note: "+1.5V_VCCA"

as short as possible
C8
SCD1U10V2KX-4GP
+1.5V_RUN
1 R356
2
0R0603-PAD
C374
SCD01U16V2KX-3GP
R311 1
2 100R2F-L1-GP-U
C377
SC10U6D3V5MX-3GP
Layout Note:
Place as close as possible
to the CPU VCCA pin.
+VCC_CORE
AF7
VCC_SENSE 28
VSSSENSE
AE7
VSS_SENSE 28
R302 1
CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
CPU_VID5
CPU_VID6
28
CPU_VID[6..0]
VCCSENSE
BGA479-SKT6-GPU7
1
2
1
2
1
2
1
2
C12
SC22U6D3V5MX-2GP
2
1
AD6
AF5
AE5
AF4
AE3
AF3
AE2
VID0
VID1
VID2
VID3
VID4
VID5
VID6
DY
C44
SCD1U10V2KX-4GP
B26
C26
C24
SC22U6D3V5MX-2GP
+1.05V_VCCP
VCCA
VCCA
DY
+VCC_CORE
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
G21
V6
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21
C14
SC22U6D3V5MX-2GP
AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20
DY
U41D
A4
A8
A11
A14
A16
A19
A23
AF2
B6
B8
B11
B13
B16
B19
B21
B24
C5
C8
C11
C14
C16
C19
C2
C22
C25
D1
D4
D8
D11
D13
D16
D19
D23
D26
E3
E6
E8
E11
E14
E16
E19
E21
E24
F5
F8
F11
F13
F16
F19
F2
F22
F25
G4
G1
G23
G26
H3
H6
H21
H24
J2
J5
J22
J25
K1
K4
K23
K26
L3
L6
L21
L24
M2
M5
M22
M25
N1
N4
N23
N26
P3
+VCC_CORE
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
TC17
ST220U2D5VBM-LGP
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
DY
C26
SC22U6D3V5MX-2GP
U41C 3 OF 4
A7
A9
A10
A12
A13
A15
A17
A18
A20
B7
B9
B10
B12
B14
B15
B17
B18
B20
C9
C10
C12
C13
C15
C17
C18
D9
D10
D12
D14
D15
D17
D18
E7
E9
E10
E12
E13
E15
E17
E18
E20
F7
F9
F10
F12
F14
F15
F17
F18
F20
AA7
AA9
AA10
AA12
AA13
AA15
AA17
AA18
AA20
AB9
AC10
AB10
AB12
AB14
AB15
AB17
AB18
C31
SC22U6D3V5MX-2GP
+VCC_CORE
DY
C352
SC22U6D3V5MX-2GP
+VCC_CORE
C36
SC22U6D3V5MX-2GP
DY
C15
SC22U6D3V5MX-2GP
DY
C17
SC22U6D3V5MX-2GP
C25
SC22U6D3V5MX-2GP
+VCC_CORE
VCC_SENSE and VSS_SENSE lines

should be of equal length.
2 100R2F-L1-GP-U
4 OF 4
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
62.10040.221
P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
A2
AF6
AF8
AF11
AF13
AF16
AF19
AF21
A25
AF25
NCTF
PIN
CPU_GND1
TP10
B
CPU_GND2
CPU_GND3
TP224
TP20
CPU_GND4
TP56
BGA479-SKT6-GPU7
62.10040.221
<Core Design>
Wistron Corporation
Title
Size
Document Number
Custom
CPU-Power(3/3)

5
Rev
A00
Roberts
Sheet
1
of
58
SSID = MCH
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
+1.05V_VCCP
H_SWING routing Trace width and

Spacing use 10 / 20 mil
R368
221R2F-2-GP
2
H_SWING Resistors and

Capacitors close MCH
500 mil ( MAX )
R367
100R2F-L1-GP-U
2
H_SWING
C399
SCD1U10V2KX-4GP
H_RCOMP routing Trace width and

Spacing use 10 / 20 mil
1
R361
2 H_RCOMP
24D9R2F-L-GP
Place R51 near to the chip ( < 0.5")
H_SWING
H_RCOMP
C5
E3
H_D#_0
H_D#_1
H_D#_2
H_D#_3
H_D#_4
H_D#_5
H_D#_6
H_D#_7
H_D#_8
H_D#_9
H_D#_10
H_D#_11
H_D#_12
H_D#_13
H_D#_14
H_D#_15
H_D#_16
H_D#_17
H_D#_18
H_D#_19
H_D#_20
H_D#_21
H_D#_22
H_D#_23
H_D#_24
H_D#_25
H_D#_26
H_D#_27
H_D#_28
H_D#_29
H_D#_30
H_D#_31
H_D#_32
H_D#_33
H_D#_34
H_D#_35
H_D#_36
H_D#_37
H_D#_38
H_D#_39
H_D#_40
H_D#_41
H_D#_42
H_D#_43
H_D#_44
H_D#_45
H_D#_46
H_D#_47
H_D#_48
H_D#_49
H_D#_50
H_D#_51
H_D#_52
H_D#_53
H_D#_54
H_D#_55
H_D#_56
H_D#_57
H_D#_58
H_D#_59
H_D#_60
H_D#_61
H_D#_62
H_D#_63
H_SWING
H_RCOMP
+1.05V_VCCP
F2
G8
F8
E6
G2
H6
H2
F6
D4
H3
M9
M11
J1
J2
N12
J6
P2
L2
R2
N9
L6
M5
J3
N2
R1
N5
N6
P13
N8
L7
N10
M3
Y3
AD14
Y6
Y10
Y12
Y14
Y7
W2
AA8
Y9
AA13
AA9
AA11
AD11
AD10
AD13
AE12
AE9
AA2
AD8
AA3
AD3
AD7
AE14
AF3
AC1
AE3
AC3
AE11
AE8
AG2
AD6
HOST
H_D#[63..0]
H_D#[63..0]
R369
1KR2F-3-GP
C12
E11
5,37 H_CPURST#
6
H_CPUSLP#
A11
B11
H_AVREF
H_DVREF
A14
C15
F16
H13
C18
M16
J13
P16
R16
N17
M13
E17
P17
F17
G20
B19
J16
E20
H16
J20
L17
A17
B17
L16
C21
J17
H20
B18
K17
B20
F21
K21
L20
H_ADS#
H_ADSTB#_0
H_ADSTB#_1
H_BNR#
H_BPRI#
H_BREQ#
H_DEFER#
H_DBSY#
HPLL_CLK
HPLL_CLK#
H_DPWR#
H_DRDY#
H_HIT#
H_HITM#
H_LOCK#
H_TRDY#
H12
B16
G17
A9
F11
G12
E9
B10
AH7
AH6
J11
F9
H9
E12
H11
C9
H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3
J8
L3
Y13
Y1
H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3
H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3
L10
M7
AA5
AE6
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3
L9
M8
AA6
AE5
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3
H_REQ#_0
H_REQ#_1
H_REQ#_2
H_REQ#_3
H_REQ#_4
B15
K13
F13
B13
B14
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_RS#_0
H_RS#_1
H_RS#_2
B6
F12
C8
H_RS#0
H_RS#1
H_RS#2
C
H_ADS#
5
H_ADSTB#0 5
H_ADSTB#1 5
H_BNR#
5
H_BPRI# 5
H_BREQ#0 5
H_DEFER# 5
H_DBSY# 5
CLK_MCH_BCLK 4
CLK_MCH_BCLK# 4
H_DPWR# 6
H_DRDY# 5
H_HIT#
5
H_HITM# 5
H_LOCK# 5
H_TRDY# 5
H_DINV#[3..0]
H_DSTBN#[3..0]
H_DINV#[3..0]
H_DSTBN#[3..0]
H_DSTBP#[3..0]
B
H_DSTBP#[3..0]
H_REQ#[4..0]
H_RS#[2..0]
H_REQ#[4..0]
H_RS#[2..0]
CANTIGA-GM-GP-U-NF
DY
H_CPURST#
H_CPUSLP#
H_A#[35..3]
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8
H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31
H_A#_32
H_A#_33
H_A#_34
H_A#_35
C403
SCD1U16V2KX-3GP
R372
2KR2F-3-GP
H_AVREF
H_A#[35..3]
1 OF 10
U52A
<Core Design>
Wistron Corporation
Title
Cantiga-HOST(1/6)
Size
Document Number
Custom
Rev
A00
Roberts
Sheet
of
58
+3.3V_RUN
BD17
AY17
BF15
AY13
M_ODT0
M_ODT1
M_ODT2
M_ODT3
14
14
15
15
SM_RCOMP
SM_RCOMP#
BG22
BH21
M_RCOMPP
M_RCOMPN
SM_RCOMP_VOH
SM_RCOMP_VOL
BF28
BH28
SM_RCOMP_VOH
SM_RCOMP_VOL
SM_VREF
SM_PWROK
SM_REXT
SM_DRAMRST#
AV42
AR36
BF17
BC36
SM_REXT R374 1
DPLL_REF_CLK
DPLL_REF_CLK#
DPLL_REF_SSCLK
DPLL_REF_SSCLK#
B38
A38
E41
F41
CLK_MCH_DREFCLK
CLK_MCH_DREFCLK#
MCH_SSCDREFCLK
MCH_SSCDREFCLK#
PEG_CLK
PEG_CLK#
F43
E43
CLK_MCH_3GPLL
CLK_MCH_3GPLL#
DMI_RXN_0
DMI_RXN_1
DMI_RXN_2
DMI_RXN_3
AE41
AE37
AE47
AH39
DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3
R121 1
DMI_RXP_0
DMI_RXP_1
DMI_RXP_2
DMI_RXP_3
AE40
AE38
AE48
AH40
DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3
DMI_TXN_0
DMI_TXN_1
DMI_TXN_2
DMI_TXN_3
AE35
AE43
AE46
AH42
DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3
DMI_TXP_0
DMI_TXP_1
DMI_TXP_2
DMI_TXP_3
AD35
AE44
AF46
AH43
DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3
2 2K21R2F-GP CFG18
FSB setting
2 4K02R2F-GP CFG19
4
4
4
2 4K02R2F-GP CFG20
RN20
4
3
1
2
PM_EXTTS#0
PM_EXTTS#1
MCH_CLKSEL0
MCH_CLKSEL1
MCH_CLKSEL2
TP86
TP88
SRN10KJ-5-GP
R383 1
R112 1
R111 1
R102 1
R382 1
R375 1
R101 1
R105 1
R103 1
DY
DY
DY
DY
DY
DY
DY
DY
DY
2 2K21R2F-GP CFG5
2 2K21R2F-GP CFG6
2 2K21R2F-GP CFG7
TP84
TP85
2 2K21R2F-GP CFG8
TP87
2 4K02R2F-GP CFG9
2 2K21R2F-GP CFG10
CFG_0
CFG_1
CFG_2
CFG_3
CFG_4
CFG_5
CFG_6
CFG_7
CFG_8
CFG_9
CFG_10
CFG_11
CFG_12
CFG_13
CFG_14
CFG_15
CFG_16
CFG_17
CFG_18
CFG_19
CFG_20
CFG
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
CFG20
T25
R25
P25
P20
P24
C25
N24
M24
E21
C23
C24
N21
P21
T21
R20
M20
L21
H21
P29
R28
T28
RSTIN#
18,24,25 PM_PWROK
R29
B7
N33
P32
AT40
AT11
T20
R32
PM_SYNC#
PM_DPRSTP#
PM_EXT_TS#_0
PM_EXT_TS#_1
PWROK
RSTIN#
THERMTRIP#
DPRSLPVR
PM
18
PM_SYNC#
6,17,28 H_DPRSTP#
14
PM_EXTTS#0
15
PM_EXTTS#1
2 2K21R2F-GP CFG16
DY
C151
SCD01U16V2KX-3GP
DY
R116
3K01R2F-3-GP
SM_RCOMP_VOL
2
R142
10KR2J-3-GP
R145
10KR2J-3-GP
C145
SC2D2U10V3KX-1GP
R119
1KR2F-3-GP
1
CLK_MCH_DREFCLK 4
CLK_MCH_DREFCLK# 4
MCH_SSCDREFCLK 4
MCH_SSCDREFCLK# 4
C162
SCD01U16V2KX-3GP
1
2 499R2F-2-GP
C159
SC2D2U10V3KX-1GP
+1.8V_SUS
SM_RCOMP_VOH
+V_DDR_MCH_REF
CLK_MCH_3GPLL 4
CLK_MCH_3GPLL# 4
DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3
16
16
16
16
DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3
16
16
16
16
DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3
16
16
16
16
DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3
16
16
16
16
+1.05V_VCCP
+3.3V_RUN
R370
56R2J-4-GP
CANTIGA-GM-GP-U-NF
TSATN#
GFX_VID_0
GFX_VID_1
GFX_VID_2
GFX_VID_3
GFX_VID_4
B33
B32
G33
F33
E33
GFX_VR_EN
C34
R371
10KR2J-3-GP
DY
TSATN#_KBC 24
DY
Q19
MMBT3904WT1G-GP
+1.05V_VCCP
CL_CLK
CL_DATA
CL_PWROK
CL_RST#
CL_VREF
AH37
AH36
AN36
AJ35
AH34
MCH_CLVREF
R126
1KR2F-3-GP
CL_CLK0 18
CL_DATA0 18
M_PWROK 18
CL_RST#0 18
MCH_CLVREF ~= 0.35V
NC
5,17,24,34 H_THRMTRIP#
18,28 DPRSLPVR
DY
NC#BG48
NC#BF48
NC#BD48
NC#BC48
NC#BH47
NC#BG47
NC#BE47
NC#BH46
NC#BF46
NC#BG45
NC#BH44
NC#BH43
NC#BH6
NC#BH5
NC#BG4
NC#BH3
NC#BF3
NC#BH2
NC#BG2
NC#BE2
NC#BG1
NC#BF1
NC#BD1
NC#BC1
NC#F1
NC#A47
MISC
C94
SC100P50V2JN-3GP
BG48
BF48
BD48
BC48
BH47
BG47
BE47
BH46
BF46
BG45
BH44
BH43
BH6
BH5
BG4
BH3
BF3
BH2
BG2
BE2
BG1
BF1
BD1
BC1
F1
A47
HDA
2
1
100R2F-L1-GP-U
PLT_RST#
ME
R94
16,20,21,24,37,41
R122
1KR2F-3-GP
R377
80D6R2F-L-GP
TSATN#_KBC
2 2K21R2F-GP CFG12
2 2K21R2F-GP CFG13
+1.8V_SUS
R117 1
2 2K21R2F-GP CFG11
DMI
R128 1
DY
DY
DY
DY
SA_ODT_0
SA_ODT_1
SB_ODT_0
SB_ODT_1
GRAPHICS VID
R104 1
14
14
15
15
CLK
M_CS0#
M_CS1#
M_CS2#
M_CS3#
L_DDC_DATA
DDPC_CTRLDATA
Reverse DMI lanes
BA17
AY16
AV16
AR13
R380
80D6R2F-L-GP
SDVO_CTRLDATA
* PCIE and SDVO are

Only PCIE or SDVO
simultaneously
* operatiing
is operational
via the PEG port
enable
SDVO interface disable
* SDVOLFPinterface
LFP disable
card present
*
SDVO/iHDMI/DP
SDVO/iHDMI/DP
interface disabled *
interface enabled
Normal operation
RESERVED#BG23
RESERVED#BF23
RESERVED#BH18
RESERVED#BF18
SA_CS#_0
SA_CS#_1
SB_CS#_0
SB_CS#_1
+1.8V_SUS
CFG 19
DMI Lane Reserved
CFG 20
SDVO concurrent
with PCIE
BG23
BF23
BH18
BF18
14
14
15
15
FSB dynamic ODT disable
CFG 16
RESERVED#AY21
M_CKE0
M_CKE1
M_CKE2
M_CKE3
XOR mode enable
BC28
AY28
AY36
BB36
CFG 13
AY21
SA_CKE_0
SA_CKE_1
SB_CKE_0
SB_CKE_1
ALLZ mode enable
14
14
15
15
PCIE loopback enable
CFG 12
RESERVED#B31
RESERVED#B2
RESERVED#M1
M_CLK_DDR#0
M_CLK_DDR#1
M_CLK_DDR#2
M_CLK_DDR#3
CFG 10
B31
B2
M1
AR24
AR21
AU24
AV20
PCIE GFX lane reversed
SA_CK#_0
SA_CK#_1
SB_CK#_0
SB_CK#_1
CFG 9
14
14
15
15
CFG 7
*
*
*
*
PCIE loopback disable
*
ALLZ mode disable
*
XOR mode disable
*
FSB Dynamic ODT enable
*
ITPM disable
TLS cipher suite with

confidentiality
PCIE GFX lane
numbered in oder
M_CLK_DDR0
M_CLK_DDR1
M_CLK_DDR2
M_CLK_DDR3
ITPM enable
TLS cipher suite with
no confidentiality
RSVD
CFG 6
AP24
AT21
AV24
AU20
DDPC_CTRLCLK
DDPC_CTRLDATA
SDVO_CTRLCLK
SDVO_CTRLDATA
CLKREQ#
ICH_SYNC#
N28
M28
G36
E36
K36
H36
TSATN#
B12
HDA_BCLK
HDA_RST#
HDA_SDI
HDA_SDO
HDA_SYNC
B28
B30
B29
C29
A28
TP271
CLKREQ#_B 4
MCH_ICH_SYNC#
TSATN#
+3.3V_RUN
High
DMI X 4
R130
499R2F-2-GP
R131
CLKREQ#_B
10KR2J-3-GP
Low
DMI X 2
CFG 5
SA_CK_0
SA_CK_1
SB_CK_0
SB_CK_1
CFG Strap
RESERVED#M36
RESERVED#N36
RESERVED#R33
RESERVED#T33
RESERVED#AH9
RESERVED#AH10
RESERVED#AH12
RESERVED#AH13
RESERVED#K12
RESERVED#AL34
RESERVED#AK34
RESERVED#AN35
RESERVED#AM35
RESERVED#T24
C175
SCD1U10V2KX-4GP
* is current setting
M36
N36
R33
T33
AH9
AH10
AH12
AH13
K12
AL34
AK34
AN35
AM35
T24
DDR CLK/ CONTROL/COMPENSATION
SSID = MCH
2 OF 10
U52B
18
<Core Design>
Wistron Corporation
Title
Cantiga-DMI/CFG(2/6)
Size
Document Number
Custom
Sheet
Rev
A00
Roberts
9
of
58
SSID = MCH
CANTIGA-GM-GP-U-NF
M_A_BS#0 14
M_A_BS#1 14
M_A_BS#2 14
SA_RAS#
SA_CAS#
SA_WE#
BB20
BD20
AY20
M_A_RAS# 14
M_A_CAS# 14
M_A_WE# 14
SA_DM_0
SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7
AM37
AT41
AY41
AU39
BB12
AY6
AT7
AJ5
M_A_DM0
M_A_DM1
M_A_DM2
M_A_DM3
M_A_DM4
M_A_DM5
M_A_DM6
M_A_DM7
SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6
SA_DQS_7
SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7
AJ44
AT44
BA43
BC37
AW12
BC8
AU8
AM7
AJ43
AT43
BA44
BD37
AY12
BD8
AU9
AM8
M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7
M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7
SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8
SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13
SA_MA_14
BA21
BC24
BG24
BH24
BG25
BA24
BD24
BG27
BF25
AW24
BC21
BG26
BH26
BH17
AY25
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_DQS[7..0]
M_A_DQS#[7..0]
M_A_A[14..0]
M_A_DM[7..0] 14
M_A_DQS[7..0] 14
M_A_DQS#[7..0] 14
M_A_A[14..0] 14
M_B_DQ[63..0]
5 OF 10
U52E
M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63
AK47
AH46
AP47
AP46
AJ46
AJ48
AM48
AP48
AU47
AU46
BA48
AY48
AT47
AR47
BA47
BC47
BC46
BC44
BG43
BF43
BE45
BC41
BF40
BF41
BG38
BF38
BH35
BG35
BH40
BG39
BG34
BH34
BH14
BG12
BH11
BG8
BH12
BF11
BF8
BG7
BC5
BC6
AY3
AY1
BF6
BF5
BA1
BD3
AV2
AU3
AR3
AN2
AY2
AV1
AP3
AR1
AL1
AL2
AJ1
AH1
AM2
AM3
AH3
AJ3
SB_DQ_0
SB_DQ_1
SB_DQ_2
SB_DQ_3
SB_DQ_4
SB_DQ_5
SB_DQ_6
SB_DQ_7
SB_DQ_8
SB_DQ_9
SB_DQ_10
SB_DQ_11
SB_DQ_12
SB_DQ_13
SB_DQ_14
SB_DQ_15
SB_DQ_16
SB_DQ_17
SB_DQ_18
SB_DQ_19
SB_DQ_20
SB_DQ_21
SB_DQ_22
SB_DQ_23
SB_DQ_24
SB_DQ_25
SB_DQ_26
SB_DQ_27
SB_DQ_28
SB_DQ_29
SB_DQ_30
SB_DQ_31
SB_DQ_32
SB_DQ_33
SB_DQ_34
SB_DQ_35
SB_DQ_36
SB_DQ_37
SB_DQ_38
SB_DQ_39
SB_DQ_40
SB_DQ_41
SB_DQ_42
SB_DQ_43
SB_DQ_44
SB_DQ_45
SB_DQ_46
SB_DQ_47
SB_DQ_48
SB_DQ_49
SB_DQ_50
SB_DQ_51
SB_DQ_52
SB_DQ_53
SB_DQ_54
SB_DQ_55
SB_DQ_56
SB_DQ_57
SB_DQ_58
SB_DQ_59
SB_DQ_60
SB_DQ_61
SB_DQ_62
SB_DQ_63
SB_BS_0
SB_BS_1
SB_BS_2
BC16
BB17
BB33
M_B_BS#0 15
M_B_BS#1 15
M_B_BS#2 15
SB_RAS#
SB_CAS#
SB_WE#
AU17
BG16
BF14
M_B_RAS# 15
M_B_CAS# 15
M_B_WE# 15
SB_DM_0
SB_DM_1
SB_DM_2
SB_DM_3
SB_DM_4
SB_DM_5
SB_DM_6
SB_DM_7
AM47
AY47
BD40
BF35
BG11
BA3
AP1
AK2
M_B_DM0
M_B_DM1
M_B_DM2
M_B_DM3
M_B_DM4
M_B_DM5
M_B_DM6
M_B_DM7
SB_DQS_0
SB_DQS_1
SB_DQS_2
SB_DQS_3
SB_DQS_4
SB_DQS_5
SB_DQS_6
SB_DQS_7
SB_DQS#_0
SB_DQS#_1
SB_DQS#_2
SB_DQS#_3
SB_DQS#_4
SB_DQS#_5
SB_DQS#_6
SB_DQS#_7
AL47
AV48
BG41
BG37
BH9
BB2
AU1
AN6
AL46
AV47
BH41
BH37
BG9
BC2
AT2
AN5
M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7
M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7
SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8
SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13
SB_MA_14
AV17
BA25
BC25
AU25
AW25
BB28
AU28
AW28
AT33
BD33
BB16
AW33
AY33
BH15
AU33
M_B_DM[7..0]
BD21
BG18
AT25
MEMORY
15 M_B_DQ[63..0]
SA_BS_0
SA_BS_1
SA_BS_2
M_A_DM[7..0]
SA_DQ_0
SA_DQ_1
SA_DQ_2
SA_DQ_3
SA_DQ_4
SA_DQ_5
SA_DQ_6
SA_DQ_7
SA_DQ_8
SA_DQ_9
SA_DQ_10
SA_DQ_11
SA_DQ_12
SA_DQ_13
SA_DQ_14
SA_DQ_15
SA_DQ_16
SA_DQ_17
SA_DQ_18
SA_DQ_19
SA_DQ_20
SA_DQ_21
SA_DQ_22
SA_DQ_23
SA_DQ_24
SA_DQ_25
SA_DQ_26
SA_DQ_27
SA_DQ_28
SA_DQ_29
SA_DQ_30
SA_DQ_31
SA_DQ_32
SA_DQ_33
SA_DQ_34
SA_DQ_35
SA_DQ_36
SA_DQ_37
SA_DQ_38
SA_DQ_39
SA_DQ_40
SA_DQ_41
SA_DQ_42
SA_DQ_43
SA_DQ_44
SA_DQ_45
SA_DQ_46
SA_DQ_47
SA_DQ_48
SA_DQ_49
SA_DQ_50
SA_DQ_51
SA_DQ_52
SA_DQ_53
SA_DQ_54
SA_DQ_55
SA_DQ_56
SA_DQ_57
SA_DQ_58
SA_DQ_59
SA_DQ_60
SA_DQ_61
SA_DQ_62
SA_DQ_63
MEMORY
AJ38
AJ41
AN38
AM38
AJ36
AJ40
AM44
AM42
AN43
AN44
AU40
AT38
AN41
AN39
AU44
AU42
AV39
AY44
BA40
BD43
AV41
AY43
BB41
BC40
AY37
BD38
AV37
AT36
AY38
BB38
AV36
AW36
BD13
AU11
BC11
BA12
AU13
AV13
BD12
BC12
BB9
BA9
AU10
AV9
BA11
BD9
AY8
BA6
AV5
AV7
AT9
AN8
AU5
AU6
AT5
AN10
AM11
AM5
AJ9
AJ8
AN12
AM13
AJ11
AJ12
SYSTEM
4 OF 10
U52D
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63
DDR
M_A_DQ[63..0]
SYSTEM
14 M_A_DQ[63..0]
DDR
M_B_DM[7..0] 15
M_B_DQS[7..0]
M_B_DQS[7..0] 15
M_B_DQS#[7..0]
M_B_DQS#[7..0] 15
M_B_A[14..0]
M_B_A[14..0] 15
M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
CANTIGA-GM-GP-U-NF
<Core Design>
Wistron Corporation
Title
Cantiga-DDR(3/6)
Size
Document Number
Custom
Rev
A00
Roberts
Sheet
10
of
58
SSID = MCH
FOR VCC CORE
1
2
1
2
C166
SCD1U10V2KX-4GP
1
2
C113
SCD22U10V2KX-1GP
1
2
C111
SC10U6D3V5MX-3GP
1
2
C164
SCD1U10V2KX-4GP
1
2
C142
SC1U10V3KX-3GP
1
2
C156
SCD1U10V2KX-4GP
VCC_GMCH_35
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
AE33
AC33
AA33
Y33
W33
V33
U33
AH28
AF28
AC28
AA28
AJ26
AG26
AE26
AC26
AH25
AG25
AF25
AG24
AJ23
AH23
AF23
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
T32
VCC
1
2
DY
C435
SC22U6D3V5MX-2GP
C426
SC22U6D3V5MX-2GP
1
2
TC21
ST220U2D5VBM-2GP
+1.8V_SUS
Signal Group
+1.05V_VCCP
VCC
2898.52mA
+1.05V_VCCP
Imax
+1.05V_VCCP
VCC_AXG
8700mA
+1.05V_VCCP
VTT
852mA
+1.05V_VCCP
VCC_PEG
1782mA
+1.05V_VCCP
VCC_DMI
456mA
+1.05V_VCCP
VCCA_SM
720mA
+1.05V_VCCP
VCCA_SM_CK
26mA
+1.05V_VCCP
VCCA_HPLL
24mA
+1.05V_VCCP
VCCA_MPLL
139.2mA
+1.05V_VCCP
VCCD_HPLL
157.2mA
+1.05V_VCCP
VCCA_PEG_PLL
50mA
+1.05V_VCCP
VCCD_PEG_PLL
50mA
+1.05V_VCCP
VCC_AXF
321.35mA
+1.5V_RUN
VCC_HDA
50mA
+1.5V_RUN
VCCD_TVDAC
35mA
+1.8V_SUS
VCCD_LVDS
60.31mA
+1.8V_SUS
VCC_SM
3000mA
+1.8V_SUS
VCC_SM_CK
124mA
+3.3V_RUN
VCCA_PEG_BG
414uA
+3.3V_RUN
VCC_HV
105.3mA
VCC NCTF
Place CAP where

LVDS and DDR2 taps
Supply
POWER
C80
SCD1U10V2KX-4GP
C98
SCD1U10V2KX-4GP
1
2
C84
SCD1U16V2KX-3GP
1
2
C91
SCD22U10V2KX-1GP
C390
SC22U6D3V5MX-2GP
1
2
C383
SC10U6D3V5MX-3GP
1
2
C173
SCD1U16V2KX-3GP
1
2
C108
SCD1U16V2KX-3GP
C110
SCD1U16V2KX-3GP
C161
SCD47U6D3V2KX-GP
C170
SC22U6D3V5MX-2GP
FOR VCC SM
VCC_AXG_SENSE
VSS_AXG_SENSE
AG34
AC34
AB34
AA34
Y34
V34
U34
AM33
AK33
AJ33
AG33
AF33
0R2J-2-GP
C431
SCD1U10V2KX-4GP
AJ14
AH14
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
AM32
AL32
AK32
AJ32
AH32
AG32
AE32
AC32
AA32
Y32
W32
U32
AM30
AL30
AK30
AH30
AG30
AF30
AE30
AC30
AB30
AA30
Y30
W30
V30
U30
AL29
AK29
AJ29
AH29
AG29
AE29
AC29
AA29
Y29
W29
V29
AL28
AK28
AL26
AK26
AK25
AK24
AK23
1
2
C186
SC1U10V3KX-3GP
1
2
C178
SC1U10V3KX-3GP
1
2
C182
SCD47U6D3V2KX-GP
C134
SCD22U10V2KX-1GP
1
2
C81
SCD22U10V2KX-1GP
1
2
AV44 SM_LF1_GMCH
BA37 SM_LF2_GMCH
AM40 SM_LF3_GMCH
AV21 SM_LF4_GMCH
AY5 SM_LF5_GMCH
AM10 SM_LF6_GMCH
BB13 SM_LF7_GMCH
C92
SCD1U10V2KX-4GP
CANTIGA-GM-GP-U-NF
VCC_SM_LF
VCC_SM_LF
VCC_SM_LF
VCC_SM_LF
VCC_SM_LF
VCC_SM_LF
VCC_SM_LF
VCC GFX
CANTIGA-GM-GP-U-NF
C99
SCD1U10V2KX-4GP
VCC_AXG_SENSE
VSS_AXG_SENSE
R125
TP83
TP82
Coupling CAP
Place on the Edge
VCC SM LF
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
1
2
8700mA
Y26
AE25
AB25
AA25
AE24
AC24
AA24
Y24
AE23
AC23
AB23
AA23
AJ21
AG21
AE21
AC21
AA21
Y21
AH20
AF20
AE20
AC20
AB20
AA20
T17
T16
AM15
AL15
AE15
AJ15
AH15
AG15
AF15
AB15
AA15
Y15
V15
U15
AN14
AM14
U14
T14
Coupling CAP
POWER
VCC GFX NCTF
+1.05V_VCCP
DY
Coupling CAP 370 mils from the Edge
TC19
ST220U2D5VBM-2GP
VCC_SM/NC
VCC_SM/NC
VCC_SM/NC
VCC_SM/NC
VCC_SM/NC
VCC_SM/NC
VCC_SM/NC
W28
V28
W26
V26
W25
V25
W24
V24
W23
V23
AM21
AL21
AK21
W21
V21
U21
AM20
AK20
W20
U20
AM19
AL19
AK19
AJ19
AH19
AG19
AF19
AE19
AB19
AA19
Y19
W19
V19
U19
AM17
AK17
AH17
AG17
AF17
AE17
AC17
AB17
Y17
W17
V17
AM16
AL16
AK16
AJ16
AH16
AG16
AF16
AE16
AC16
AB16
AA16
Y16
W16
V16
U16
Place on the Edge
BA36
BB24
BD16
BB21
AW16
AW13
AT13
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
+1.05V_VCCP
2898.52mA
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
3000mA
AP33
AN33
BH32
BG32
BF32
BD32
BC32
BB32
BA32
AY32
AW32
AV32
AU32
AT32
AR32
AP32
AN32
BH31
BG31
BF31
BG30
BH29
BG29
BF29
BD29
BC29
BB29
BA29
AY29
AW29
AV29
AU29
AT29
AR29
AP29
VCC SM
7 OF 10
U52G
+1.8V_SUS
6 OF 10
U52F
+1.05V_VCCP
VCC CORE
<Core Design>
Wistron Corporation
Title
Cantiga-Power(4/6)
Size
Document Number
Custom
Date: Thursday, September 11, 2008
Rev
A00
Roberts
Sheet
11
of
58
+1.05V_VCCP
VCCA_LVDS
J47
VSSA_LVDS
TC3
ST220U2D5VBM-LGP
EC48
SCD1U25V3KX-GP
C128
SC4D7U6D3V3KX-GP
1
2
C123
SC4D7U6D3V3KX-GP
1
2
C135
SC2D2U10V3KX-1GP
C143
SCD47U6D3V2KX-GP
1
2
C408
SC1U10V3KX-3GP
1 R97
2
0R0805-PAD
2 1
R100
1R3F-GP
C137
SC10U6D3V5MX-3GP
1 R405
2
0R0603-PAD
1
2
C449
SC22U6D3V5MX-2GP
1
2
PEG
VTTLF
VTTLF
VTTLF
AH48
AF48
AH47
AG47
VCC_DMI
VCC_DMI
VCC_DMI
VCC_DMI
C446
SC10U6D3V5MX-3GP
+1.05V_VCCP
VTTLF1
VTTLF2
VTTLF3
A8
L1
AB2
CANTIGA-GM-GP-U-NF
1
2
C181
SCD1U10V2KX-4GP
1
2
1
2
C90
SCD47U6D3V2KX-GP
VCCD_LVDS
VCCD_LVDS
C394
SCD47U6D3V2KX-GP
M38
L37
60.31mA
1D8V_SUS_DLVDS
C407
SC10U6D3V5MX-3GP
+1.05V_VCCP
V48
U48
V47
U47
U46
C191
SC10U6D3V5MX-3GP
VCC_PEG
VCC_PEG
VCC_PEG
VCC_PEG
VCC_PEG
HV
C35
B35
A35
+3.3V_VCC_HV
105.3mA
K47
C395
SCD47U6D3V2KX-GP
C438
SCD1U10V2KX-4GP
+1.8V_SUS
1 R140
2
0R0603-PAD
C133
SCD1U10V2KX-4GP
AXF
124mA
SM CK
A CK
321.35mA
2
VCCD_PEG_PLL 50mA
1D8V_TXLVDS_S3
C447
SC4D7U6D3V3KX-GP
157.2mA
BF21
BH20
BG20
BF20
VCC_HV
VCC_HV
VCC_HV
1782mA
VCCD_HPLL
AA47
VCC_SM_CK
VCC_SM_CK
VCC_SM_CK
VCC_SM_CK
456mA
AF1
1D05V_RUN_PEGPLL
35mA
2mA
B22
B21
A21
VTTLF
VCCD_QDAC
DMI
VCCD_TVDAC
L28
DY
C385
SCD1U10V2KX-4GP
852mA
A PEG
M25
1D5VRUN_QDAC
1D05V_RUN_HPLL
50mA
VCC_AXF
VCC_AXF
VCC_AXF
118.8mA VCC_TX_LVDS
D TV/CRT
VCC_HDA
1 R373
2
0R0603-PAD
+1.8V_SUS
TV
A32
1D5VRUN_TVDAC
Reserved for TV ripple
VCC_HDA
C437
SCD1U10V2KX-4GP
+1.8V_SUS
HDA
C157
SCD1U10V2KX-4GP
C416
SCD01U16V2KX-3GP
VCCA_TV_DAC
VCCA_TV_DAC
1
10R2J-2-GP
+1.05V_VCCP
POWER
VCCA_SM_CK
VCCA_SM_CK
VCCA_SM_CK
VCCA_SM_CK
VCCA_SM_CK
VCCA_SM_CK_NCTF
VCCA_SM_CK_NCTF
VCCA_SM_CK_NCTF
VCCA_SM_CK_NCTF
VCCA_SM_CK_NCTF
VCCA_SM_CK_NCTF
VCCA_SM_CK_NCTF
VCCA_SM_CK_NCTF
B24
A24
1 R398
2
0R0402-PAD
BAT54-7-F-GP
VCCA_PEG_PLL 50mA
LVDS
+1.05V_VCCP
1D05V_VCC_AXF
VCCA_SM
VCCA_SM
VCCA_SM
VCCA_SM
VCCA_SM
VCCA_SM
VCCA_SM
VCCA_SM
VCCA_SM
+3.3V_VCC_HV
R396
A SM
1
2
C129
SC1U10V3KX-3GP
C130
SC4D7U6D3V3KX-GP
AR20
AP20
AN20
AR17
AP17
AN17
AT16
AR16
AP16
DY
2
C417
SCD1U10V2KX-4GP
AA48
AP28
AN28
AP25
AN25
AN24
AM28
AM26
AM25
AL25
AM24
AL24
AM23
AL23
1
2
C158
SCD1U10V2KX-4GP
1
2
C154
SCD01U16V2KX-3GP
1 R395
2
0R0402-PAD
G9091-330T12U-GP
Main source:
74.09091.H3F
2nd source:
74.09198.07F
VTT
VCCA_PEG_BG
+3.3V_RUN
D22
1
C440
SC1KP50V2KX-1GP
AD48
DY
+1.05V_VCCP
1D05V_SM_CK
C126
SC22U6D3V5MX-2GP
2
1
C144
SC2D2U10V3KX-1GP
2
1
2
DY
DY
EN
GND
VIN
VOUT
NC#5
CRT
13.2mA
1
2
J48
U13
T13
U12
T12
U11
T11
U10
T10
U9
T9
U8
T8
U7
T7
U6
T6
U5
T5
V3
U3
V2
U2
T2
V1
U1
C445
SC10U6D3V5MX-3GP
1D8V_TXLVDS
A LVDS
2
2
1
C127
SC22U6D3V5MX-2GP
1
2
1
2
1
2
1
1 R378
2
0R0402-PAD
U53
C419
SC10U6D3V5MX-3GP
VCCA_MPLL 139.2mA
+3.3V_TV_DAC
1 R360
2
0R0603-PAD
+3.3V_CRT_LDO
AE1
24mA
1D5VRUN_QDAC
1
2
3
4
5
VCCA_HPLL
C442
SCD1U10V2KX-4GP
1D05V_RUN_PEGPLL
C153
SCD01U16V2KX-3GP
C152
SCD1U10V2KX-4GP
+3.3V_CRT_LDO
1 R120
2
0R0603-PAD
+5V_RUN
C436
SC1U10V3KX-3GP
AD1
79mA
180ohm 100MHz
M_VCCA_HPLL
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
414uA
L3
1
2
HCB1608K-181T20GP
VCCA_DPLLB
VCCA_PEG_BG
DY
1D5VRUN_TVDAC
A00.08/0903
VCCA_DPLLA
L48
5mA
26mA
1 R115
2
0R0603-PAD
F47
M_VCCA_DPLLB
C441
SC1KP50V2KX-1GP
+1.05V_VCCP
+1.05V_VCCP
+1.5V_RUN
M_VCCA_DPLLA
1 R402
2
0R0402-PAD
C443
SCD1U10V2KX-4GP
1D05V_RUN_PEGPLL
220ohm 100MHz
C450
SC10U6D3V5MX-3GP
L16
1
2
BLM18BB221SN1D-GP
C384
SCD1U10V2KX-4GP
1
2
+1.05V_VCCP
VCCA_DAC_BG
VSSA_DAC_BG
720mA
C391
SC10U6D3V5MX-3GP
DY
A25
B25
+1.5V_RUN
M_VCCA_MPLL
120ohm 100MHz
M_VCCA_DAC_BG
M_VCCA_MPLL
C140
SC22U6D3V5MX-2GP
L11
1
2
FCM1608KF-1-GP
C387
SCD1U10V2KX-4GP
1
2
120ohm 100MHz
C393
SC4D7U6D3V3KX-GP
M_VCCA_HPLL
VCCA_CRT_DAC
VCCA_CRT_DAC
1 R403
2
0R0402-PAD
L12
1
2
FCM1608KF-1-GP
B27
A26
PLL
C433
SCD1U10V2KX-4GP
2
1
+1.8V_SUS
R351
0R3-0-U-GP
8 OF 10
U52H
C423
SCD1U10V2KX-4GP
1
2
C439
SCD1U10V2KX-4GP
C444
SCD1U16V2KX-3GP
1
2
1 R390
2
0R0603-PAD
+1.05V_VCCP
+3.3V_CRT_LDO
DY
+1.05V_VCCP
3D3V_CRTDAC_S0
64.8mA
C448
SCD1U16V2KX-3GP
M_VCCA_DPLLB
C434
SCD01U16V2KX-3GP
1 R394
2
0R0603-PAD
+3.3V_CRT_LDO
C427
SCD01U16V2KX-3GP
C187
SCD1U10V2KX-4GP
C188
SCD1U16V2KX-3GP
C189
SCD1U16V2KX-3GP
DY
73mA
1 R408
2
0R0603-PAD
M_VCCA_DPLLA
SSID = MCH
1 R152
2
0R0603-PAD
C185
SCD1U10V2KX-4GP
<Core Design>
Wistron Corporation
Title
Cantiga-Power/Filter(5/6)
Size
Document Number
Custom
Sheet
Rev
A00
Roberts
12
of
58
+1.05V_VCCP
2
SSID = MCH
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AN13
AJ13
AE13
N13
L13
G13
E13
BF12
AV12
AT12
AM12
AA12
J12
A12
BD11
BB11
AY11
AN11
AH11
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Y11
N11
G11
C11
BG10
AV10
AT10
AJ10
AE10
AA10
M10
BF9
BC9
AN9
AM9
AD9
G9
B9
BH8
BB8
AV8
AT8
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AH8
Y8
L8
E8
B8
AY7
AU7
AN7
AJ7
AE7
AA7
N7
J7
BG6
BD6
AV6
AT6
AM6
M6
C6
BA5
AH5
AD5
Y5
L5
J5
H5
F5
BE4
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
BC3
AV3
AL3
R3
P3
F3
BA2
AW2
AU2
AR2
AP2
AJ2
AH2
AF2
AE2
AD2
AC2
Y2
M2
K2
AM1
AA1
P1
H1
VSS
VSS
VSS
VSS
U24
U28
U25
U29
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
AF32
AB32
V32
AJ30
AM29
AF29
AB29
U26
U23
AL20
V20
AC19
AL17
AJ17
AA17
U17
VSS_SCB
VSS_SCB
VSS_SCB
VSS_SCB
VSS_SCB
BH48
BH1
A48
C1
A3
NC#E1
NC#D2
NC#C3
NC#B4
NC#A5
NC#A6
NC#A43
NC#A44
NC#B45
NC#C46
NC#D47
NC#B47
NC#A46
NC#F48
NC#E48
NC#C48
NC#B48
RN41
L_BKLT_CTRL
L_BKLT_EN
L_CTRL_CLK
M33
K33
J33
L_CTRL_DATA
L_DDC_CLK
L_DDC_DATA
M29
C44
B43
E37
E38
C41
C40
B37
A37
L_VDD_EN
LVDS_IBG
LVDS_VBG
LVDS_VREFH
LVDS_VREFL
LVDSA_CLK#
LVDSA_CLK
LVDSB_CLK#
LVDSB_CLK
35 VGA_TXAOUT035 VGA_TXAOUT135 VGA_TXAOUT2-
H47
E46
G40
A40
LVDSA_DATA#_0
LVDSA_DATA#_1
LVDSA_DATA#_2
LVDSA_DATA#_3
35 VGA_TXAOUT0+
35 VGA_TXAOUT1+
35 VGA_TXAOUT2+
H48
D45
F40
B40
LVDSA_DATA_0
LVDSA_DATA_1
LVDSA_DATA_2
LVDSA_DATA_3
35 VGA_TXBOUT035 VGA_TXBOUT135 VGA_TXBOUT2-
A41
H38
G37
J37
LVDSB_DATA#_0
LVDSB_DATA#_1
LVDSB_DATA#_2
LVDSB_DATA#_3
35 VGA_TXBOUT0+
35 VGA_TXBOUT1+
35 VGA_TXBOUT2+
B42
G38
F37
K37
LVDSB_DATA_0
LVDSB_DATA_1
LVDSB_DATA_2
LVDSB_DATA_3
F25
H25
K25
TVA_DAC
TVB_DAC
TVC_DAC
H24
TV_RTN
C31
E32
TV_DCONSEL_0
TV_DCONSEL_1
L_CTRL_DATA
L_CTRL_CLK
1
2
SRN10KJ-5-GP
RN19
4
3
LDDC_CLK
LDDC_DATA
35
35
35
LDDC_CLK
LDDC_DATA
LCDVDD_EN
SRN2K2J-1-GP
R144 2
35
35
35
35
1 2K37R2F-GP
TP225
45
M_BLUE
45
M_GREEN
45
M_RED
GMCH_GND1
GMCH_GND2
GMCH_GND3
GMCH_GND4
TP103
TP80
TP226
TP78
LIBG
LVDS_VBG
VGA_TXACLKVGA_TXACLK+
VGA_TXBCLKVGA_TXBCLK+
R389 1
R386 1
R385 1
2 75R2F-2-GP
2 75R2F-2-GP
2 75R2F-2-GP
TV_DACA
TV_DACB
TV_DACC
M_BLUE
2 150R2F-1-GP
M_GREEN
2 150R2F-1-GP
M_RED
150R2F-1-GP
2
R376 1
R379 1
R381 1
GMCH_DDCCLK
GMCH_DDCDATA
2 GMCH_HS
33R2J-2-GP
45 GMCH_HSYNC
1
R123
CRT_IREF
routing Trace
width use 20 mil.
1
R124
CRT_IREF
1K02R2F-1-GP
1
R392
GMCH_VS
33R2J-2-GP
45 GMCH_VSYNC
E1
D2
C3
B4
A5
A6
A43
A44
B45
C46
D47
B47
A46
F48
E48
C48
B48
L32
G32
M32
4
3
+3.3V_RUN
+3.3V_RUN
1
2
3 OF 10
U52C
35 LBKLT_CTL
24 GMCH_BL_ON
R133
49D9R2F-GP
1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
E28
CRT_BLUE
G28
CRT_GREEN
J28
CRT_RED
G29
CRT_IRTN
H32
J32
J29
E29
L29
CRT_DDC_CLK
CRT_DDC_DATA
CRT_HSYNC
CRT_TVO_IREF
CRT_VSYNC
GRAPHICS
VSS
VSS NCTF
BA16
AU16
AN16
N16
K16
G16
E16
BG15
AC15
W15
A15
BG14
AA14
C14
BG13
BC13
BA13
VSS
VSS SCB
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
PEG_CMP
PEG_COMPI
PEG_COMPO
T37
T36
PEG_RX#_0
PEG_RX#_1
PEG_RX#_2
PEG_RX#_3
PEG_RX#_4
PEG_RX#_5
PEG_RX#_6
PEG_RX#_7
PEG_RX#_8
PEG_RX#_9
PEG_RX#_10
PEG_RX#_11
PEG_RX#_12
PEG_RX#_13
PEG_RX#_14
PEG_RX#_15
H44
J46
L44
L40
N41
P48
N44
T43
U43
Y43
Y48
Y36
AA43
AD37
AC47
AD39
PEG_RX_0
PEG_RX_1
PEG_RX_2
PEG_RX_3
PEG_RX_4
PEG_RX_5
PEG_RX_6
PEG_RX_7
PEG_RX_8
PEG_RX_9
PEG_RX_10
PEG_RX_11
PEG_RX_12
PEG_RX_13
PEG_RX_14
PEG_RX_15
H43
J44
L43
L41
N40
P47
N43
T42
U42
Y42
W47
Y37
AA42
AD36
AC48
AD40
PEG_TX#_0
PEG_TX#_1
PEG_TX#_2
PEG_TX#_3
PEG_TX#_4
PEG_TX#_5
PEG_TX#_6
PEG_TX#_7
PEG_TX#_8
PEG_TX#_9
PEG_TX#_10
PEG_TX#_11
PEG_TX#_12
PEG_TX#_13
PEG_TX#_14
PEG_TX#_15
J41
M46
M47
M40
M42
R48
N38
T40
U37
U40
Y40
AA46
AA37
AA40
AD43
AC46
PEG_TX_0
PEG_TX_1
PEG_TX_2
PEG_TX_3
PEG_TX_4
PEG_TX_5
PEG_TX_6
PEG_TX_7
PEG_TX_8
PEG_TX_9
PEG_TX_10
PEG_TX_11
PEG_TX_12
PEG_TX_13
PEG_TX_14
PEG_TX_15
J42
L46
M48
M39
M43
R47
N37
T39
U36
U39
Y39
Y46
AA36
AA39
AD42
AD46
VGA
BG21
L12
AW21
AU21
AP21
AN21
AH21
AF21
AB21
R21
M21
J21
G21
BC20
BA20
AW20
AT20
AJ20
AG20
Y20
N20
K20
F20
C20
A20
BG19
A18
BG17
BC17
AW17
AT17
R17
M17
H17
C17
TV
10 OF 10
U52J
AM36
AE36
P36
L36
J36
F36
B36
AH35
AA35
Y35
U35
T35
BF34
AM34
AJ34
AF34
AE34
W34
B34
A34
BG33
BC33
BA33
AV33
AR33
AL33
AH33
AB33
P33
L33
H33
N32
K32
F32
C32
A31
AN29
T29
N29
K29
H29
F29
A29
BG28
BD28
BA28
AV28
AT28
AR28
AJ28
AG28
AE28
AB28
Y28
P28
K28
H28
F28
C28
BF26
AH26
AF26
AB26
AA26
C26
B26
BH25
BD25
BB25
AV25
AR25
AJ25
AC25
Y25
N25
L25
J25
G25
E25
BF24
AD12
AY24
AT24
AJ24
AH24
AF24
AB24
R24
L24
K24
J24
G24
F24
E24
BH23
AG23
Y23
B23
A23
AJ6
LVDS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
PCI-EXPRESS
9 OF 10
U52I
AU48
AR48
AL48
BB47
AW47
AN47
AJ47
AF47
AD47
AB47
Y47
T47
N47
L47
G47
BD46
BA46
AY46
AV46
AR46
AM46
V46
R46
P46
H46
F46
BF44
AH44
AD44
AA44
Y44
U44
T44
M44
F44
BC43
AV43
AU43
AM43
J43
C43
BG42
AY42
AT42
AN42
AJ42
AE42
N42
L42
BD41
AU41
AM41
AH41
AD41
AA41
Y41
U41
T41
M41
G41
B41
BG40
BB40
AV40
AN40
H40
E40
AT39
AM39
AJ39
AE39
N39
L39
B39
BH38
BC38
BA38
AU38
AH38
AD38
AA38
Y38
U38
T38
J38
F38
C38
BF37
BB37
AW37
AT37
AN37
AJ37
H37
C37
BG36
BD36
AK15
AU36
Place R105
close to
MCH within
500 mils.
CANTIGA-GM-GP-U-NF
NCTF
PIN
+3.3V_RUN
RN2
+3.3V_RUN
3
4
2
1
SRN2K2J-1-GP
U4
GMCH_DDCDATA
45 DDC_CLK_CON
DDC_CLK_CON
1
2N7002SPT
DDC_DATA_CON
DDC_DATA_CON
45
GMCH_DDCCLK
5V @ ext. CRT side
<Core Design>
Wistron Corporation
CANTIGA-GM-GP-U-NF

CANTIGA-GM-GP-U-NF
Title
Cantiga-GND/LVDS/VGA(6/6)
Size
Document Number
Custom
Sheet
Rev
A00
Roberts
13
of
58
DM2
TC8
ST220U2D5VBM-LGP
DY
2
C106
SCD1U16V2KX-3GP
C100
SCD1U16V2KX-3GP
C109
SCD1U16V2KX-3GP
C93
SCD1U16V2KX-3GP
DY
2
1
2
DY
C116
SC2D2U10V3KX-1GP
C138
SC2D2U10V3KX-1GP
DY
2
1
2
C122
SC2D2U10V3KX-1GP
1
2
C132
SC2D2U10V3KX-1GP
C160
SC2D2U10V3KX-1GP
Layout Note:
Place near DM1
+1.8V_SUS
Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9V_DDR_VTT.
1
2
C420
SCD1U16V2KX-3GP
1
2
C428
SCD1U16V2KX-3GP
1
2
C115
SCD1U16V2KX-3GP
C119
SCD1U16V2KX-3GP
C118
SCD1U16V2KX-3GP
DY
2
C114
SCD1U16V2KX-3GP
DY
2
C87
SCD1U16V2KX-3GP
DY
2
DY
C432
SCD1U16V2KX-3GP
C83
SCD1U16V2KX-3GP
1
2
DY
C96
SCD1U16V2KX-3GP
C103
SCD1U16V2KX-3GP
1
2
C409
SCD1U16V2KX-3GP
DY
2
C101
SCD1U16V2KX-3GP
+0.9V_DDR_VTT
M_ODT0
M_ODT1
DY
M_CLK_DDR0
M_CLK_DDR#0
M_CLK_DDR0 9
M_CLK_DDR#0 9
CK1
CK1#
164
166
M_CLK_DDR1
M_CLK_DDR#1
M_CLK_DDR1 9
M_CLK_DDR#1 9
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
10
26
52
67
130
147
170
185
M_A_DM0
M_A_DM1
M_A_DM2
M_A_DM3
M_A_DM4
M_A_DM5
M_A_DM6
M_A_DM7
SDA
SCL
195
197
ICH_SMBDATA
ICH_SMBCLK
VDDSPD
199
SA0
SA1
198
200
NC#50
NC#69
NC#83
NC#120
NC#163/TEST
50
69
83
120
163
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
81
82
87
88
95
96
103
104
111
112
117
118
VREF
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
3
8
9
12
15
18
21
24
27
28
33
34
39
40
41
42
47
48
53
54
59
60
65
66
71
72
77
78
121
122
127
128
132
133
138
139
144
145
149
150
155
156
161
162
165
168
171
172
177
178
183
184
187
190
193
196
DQS0#
DQS1#
DQS2#
DQS3#
DQS4#
DQS5#
DQS6#
DQS7#
M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7
13
31
51
70
131
148
169
188
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
M_ODT0
M_ODT1
114
119
OTD0
OTD1
1
2
202
GND
GND
201
MH1
MH1
MH2
MH2
SKT-SODIMM200-37GP
5
11
29
49
68
129
146
167
186
C195
DUMMY-C2
M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7
1
1
ICH_SMBDATA 4,15,18
ICH_SMBCLK 4,15,18
+3.3V_RUN
R55
R56
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
5
7
17
19
4
6
14
16
23
25
35
37
20
22
36
38
43
45
55
57
44
46
56
58
61
63
73
75
62
64
74
76
123
125
135
137
124
126
134
136
141
143
151
153
140
142
152
154
157
159
173
175
158
160
174
176
179
181
189
191
180
182
192
194
C192
DUMMY-C2
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63
BA0
BA1
107
106
C74
DUMMY-C2
M_A_BS#0
M_A_BS#1
C202
SC2D2U10V3KX-1GP
30
32
M_A_BS#2
9
9
C203
SCD1U16V2KX-3GP
+V_DDR_MCH_REF
CK0
CK0#
9
9
M_A_BS#0
M_A_BS#1
M_CKE0 9
M_CKE1 9
+3.3V_RUN
2 10KR2J-3-GP
2 10KR2J-3-GP
PM_EXTTS#0 9
+1.8V_SUS
M_A_BS#2
10
10
79
80
C53
SC2D2U10V3KX-1GP
10
10 M_A_A[14..0]
M_CS0#
M_CS1#
CKE0
CKE1
put near connector

M_CLK_DDR0
M_CLK_DDR#0
M_CLK_DDR1
M_CLK_DDR#1
DY
2
10 M_A_DQS[7..0]
CS0#
CS1#
110
115
M_A_RAS# 10
M_A_WE# 10
M_A_CAS# 10
C54
SCD1U16V2KX-3GP
10 M_A_DM[7..0]
108
109
113
C72
DUMMY-C2
RAS#
WE#
CAS#
10 M_A_DQ[63..0]
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15
A16/BA2
10 M_A_DQS#[7..0]
102
101
100
99
98
97
94
92
93
91
105
90
89
116
86
84
85
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
SSID = MEMORY
Layout Note:
Place these resistors close to DM1,
all trace length Max=1.5".
+0.9V_DDR_VTT
RN37
M_A_A9
M_A_A12
1
2
RN6
4
3
4
3
SRN56J-4-GP
4
3
RN35
1
2
4
3
SRN56J-4-GP
4
3
M_A_A5
M_A_A8
1
2
SRN56J-4-GP
RN4
M_ODT0
M_CS0#
M_A_A13
SRN56J-4-GP
RN31
M_A_A10
M_A_BS#0
1
2
RN10
1
2
4
3
M_A_A6
M_A_A2
1
2
SRN56J-4-GP
SRN56J-4-GP
RN12
M_CKE1
M_A_A14
4
3
RN33
1
2
4
3
SRN56J-4-GP
SRN56J-4-GP
RN29
M_A_WE#
M_A_CAS#
4
3
RN39
1
2
1
2
SRN56J-4-GP
4
3
M_A_A11
M_A_A7
4
3
M_CKE0
M_A_BS#2
4
3
SRN56J-4-GP
RN28
M_CS1#
M_ODT1
M_A_A1
M_A_A3
1
2
RN8
1
2
4
3
SRN56J-4-GP
M_A_BS#1
M_A_RAS#
1
2
SRN56J-4-GP
RN11
RN17
1
2
SRN56J-4-GP
4
3
M_A_A0
M_A_A4
1
2
SRN56J-4-GP
<Core Design>
Wistron Corporation
Title
DDRII-SODIMM SLOT1
Size
Document Number
Custom
62.10017.E21
2
Sheet
1
Rev
A00
Roberts
14
of
58
DM1
TC4
ST220U2D5VBM-LGP
DY
2
C131
SCD1U16V2KX-3GP
C104
SCD1U16V2KX-3GP
C150
SCD1U16V2KX-3GP
C124
SCD1U16V2KX-3GP
1
2
C105
SC2D2U10V3KX-1GP
1
2
C112
SC2D2U10V3KX-1GP
1
2
DY
9
9
9
9
10
10
10
1
2
DY
C102
SCD1U16V2KX-3GP
C404
SCD1U16V2KX-3GP
1
2
C88
SCD1U16V2KX-3GP
C117
SCD1U16V2KX-3GP
DY
2
C410
SCD1U16V2KX-3GP
C95
SCD1U16V2KX-3GP
C405
SCD1U16V2KX-3GP
1
2
C406
SCD1U16V2KX-3GP
1
2
C414
SCD1U16V2KX-3GP
C418
SCD1U16V2KX-3GP
1
2
C425
SCD1U16V2KX-3GP
2
5
M_ODT2
M_ODT3
GND
202
NC#50
NC#69
NC#83
NC#120
NC#163/TEST
110
115
79
80
108
113
109
CS0#
CS1#
CKE0
CKE1
RAS#
CAS#
WE#
ICH_SMBCLK
ICH_SMBDATA
197
195
SCL
SDA
M_ODT2
M_ODT3
114
119
ODT0
ODT1
1
C200
SCD1U16V2KX-3GP
201
C201
SC2D2U10V3KX-1GP
9
9
+3.3V_RUN
+1.8V_SUS
EC12
SCD1U25V3KX-GP
DY
Layout Note:
Place these resistors close to DM2,
all trace length Max=1.5".
+0.9V_DDR_VTT
RN7
M_B_WE#
M_B_CAS#
4
3
RN27
1
2
4
3
SRN56J-4-GP
4
3
RN38
1
2
4
3
SRN56J-4-GP
M_B_BS#1
M_B_A0
4
3
RN36
1
2
4
3
SRN56J-4-GP
RN32
RN34
1
2
4
3
SRN56J-4-GP
4
3
4
3
RN30
1
2
4
3
SRN56J-4-GP
4
3
M_B_RAS#
M_CS2#
1
2
SRN56J-4-GP
RN40
M_CKE3
M_B_A10
M_B_BS#0
1
2
SRN56J-4-GP
RN5
4
3
M_B_A4
M_B_A2
1
2
RN9
1
2
SRN56J-4-GP
M_ODT3
M_CS3#
SRN56J-4-GP
RN15
M_B_A1
M_B_A3
M_B_A7
M_B_A6
1
2
SRN56J-4-GP
4
3
M_B_A14
M_B_A11
1
2
SRN56J-4-GP
RN16
M_B_A5
M_B_A8
M_ODT2
M_B_A13
1
2
SRN56J-4-GP
RN13
M_B_BS#2
M_CKE2
RN14
1
2
4
3
SRN56J-4-GP
M_B_A12
M_B_A9
1
2
SRN56J-4-GP
<Core Design>
Wistron Corporation
Title
DDRII-SODIMM SLOT2
Size
Document Number
Custom
SKT-SODIMM200-38GP
62.10017.E31
3
GND
50
69
83
120
163
C197
DUMMY-C2
2
3
8
9
12
15
18
21
24
27
28
33
34
39
40
41
42
47
48
53
54
59
60
65
66
71
72
77
78
121
122
127
128
132
133
138
139
144
145
149
150
155
156
161
162
165
168
171
172
177
178
183
184
187
190
193
196
VREF
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
81
82
87
88
95
96
103
104
111
112
117
118
C193
DUMMY-C2
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
2 10KR2J-3-GP
2 10KR2J-3-GP
+3.3V_RUN
199
1
1
+3.3V_RUN
VDD_SPD
R57
R54
SA0
SA1
198
200
M_CLK_DDR2
M_CLK_DDR#2
M_CLK_DDR3
M_CLK_DDR#3
C75
DUMMY-C2
M_CLK_DDR2
M_CLK_DDR#2
M_CLK_DDR3
M_CLK_DDR#3
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
30
32
164
166
5
7
17
19
4
6
14
16
23
25
35
37
20
22
36
38
43
45
55
57
44
46
56
58
61
63
73
75
62
64
74
76
123
125
135
137
124
126
134
136
141
143
151
153
140
142
152
154
157
159
173
175
158
160
174
176
179
181
189
191
180
182
192
194
CK0
CK0#
CK1
CK1#
M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63
9
9
+V_DDR_MCH_REF
M_B_DM0
M_B_DM1
M_B_DM2
M_B_DM3
M_B_DM4
M_B_DM5
M_B_DM6
M_B_DM7
BA0
BA1
M_CS2#
M_CS3#
M_CKE2
M_CKE3
M_B_RAS#
M_B_CAS#
M_B_WE#
4,14,18 ICH_SMBCLK
4,14,18 ICH_SMBDATA
10
26
52
67
130
147
170
185
107
106
PM_EXTTS#1
1
2
DY
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
M_B_BS#0
M_B_BS#1
C56
SC2D2U10V3KX-1GP
M_B_BS#0
M_B_BS#1
M_B_BS#2
10
10
Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9V_DDR_VTT.
C415
SCD1U16V2KX-3GP
C430
SCD1U16V2KX-3GP
DY
C107
SC2D2U10V3KX-1GP
C97
SC2D2U10V3KX-1GP
1
2
C136
SC2D2U10V3KX-1GP
DY
+0.9V_DDR_VTT
M_B_BS#2
Layout Note:
Place near DM2
+1.8V_SUS
10
10 M_B_A[14..0]
put near connector

M_CLK_DDR2
M_CLK_DDR#2
M_CLK_DDR3
M_CLK_DDR#3
10 M_B_DQS[7..0]
M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7
M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7
C52
SCD1U16V2KX-3GP
10 M_B_DM[7..0]
MH2
13
31
51
70
131
148
169
188
11
29
49
68
129
146
167
186
C71
DUMMY-C2
10 M_B_DQ[63..0]
MH2
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS0#
DQS1#
DQS2#
DQS3#
DQS4#
DQS5#
DQS6#
DQS7#
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15
A16_BA2
10 M_B_DQS#[7..0]
D
MH1
102
101
100
99
98
97
94
92
93
91
105
90
89
116
86
84
85
M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
MH1
SSID = MEMORY

2
Sheet
1
Rev
A00
Roberts
15
of
58
+3.3V_RUN
U25B
D11
C8
D9
E12
E9
C9
E10
B7
C7
C5
G11
F8
F11
E7
A3
D2
F10
D5
D10
B3
F7
C3
F3
F4
C1
G7
H7
D1
G5
H6
G1
H3
5 OF 6
U25E
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A1
A2
A28
A29
AH1
AH29
AJ1
AJ2
AJ28
AJ29
B1
B29
5
9,20,21,24,37,41
PLT_RST#
PLT_RST#
GND
VCC
DY
PCI_PLTRST#
74LVC1G08GW-1-GP
1 R262
2
0R0402-PAD
+3.3V_RUN
R245
R240
10KR2J-3-GP
10KR2J-3-GP
DY
U27
SPI_WP#
SPI_MOSO
SPI_CS#0
4
3
2
1
GND
SI
WP#
SCLK
SO
HOLD#
CS#
VCC
DY
SPI_MOSI
SPI_CLK
SPI_HOLD#
5
6
7
8
DY
2
DY
2
1
C315
SCD1U16V2KX-3GP
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
MX25L512MC-12G-GP
J5
E1
J6
C4
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
REQ0#
GNT0#
REQ1#/GPIO50
GNT1#/GPIO51
REQ2#/GPIO52
GNT2#/GPIO53
REQ3#/GPIO54
GNT3#/GPIO55
PCI
F1
G4
B6
A7
F13
F12
E6
F6
PCI_REQ0#
PCI_GNT0#
PCI_REQ1#
PCI_GNT1#
PCI_REQ2#
PCI_GNT2#
PCI_REQ3#
PCI_GNT3#
RN57
PCI_PIRQF#
PCI_TRDY#
PCI_REQ3#
PCI_PIRQD#
TP179
TP261
1
2
3
4
SRN8K2J-4-GP
RN25
PCI_PIRQB#
PCI_PIRQG#
PCI_REQ0#
PCI_PIRQH#
C/BE0#
C/BE1#
C/BE2#
C/BE3#
D8
B4
D6
A5
IRDY#
PAR
PCIRST#
DEVSEL#
PERR#
PLOCK#
SERR#
STOP#
TRDY#
FRAME#
D3
E3
R1
C6
E4
C2
J4
A4
F5
D7
PCI_IRDY#
PLTRST#
PCICLK
PME#
C14
D4
R2
PCI_PLTRST#
8
7
6
5
1
2
3
4
SRN8K2J-4-GP
PCIRST1#
PCI_DEVSEL#
PCI_PERR#
PCI_PLOCK#
PCI_SERR#
PCI_STOP#
PCI_TRDY#
PCI_FRAME#
RN26
TP135
PCI_STOP#
PCI_PLOCK#
PCI_IRDY#
PCI_PERR#
8
7
6
5
PCI_DEVSEL#
PCI_REQ1#
PCI_FRAME#
PCI_REQ2#
8
7
6
5
1
2
3
4
SRN8K2J-4-GP
RN58
CLK_PCI_ICH
TP138
ICH_PME#
1
2
3
4
SRN8K2J-4-GP
Interrupt I/F
PIRQA#
PIRQB#
PIRQC#
PIRQD#
PIRQE#/GPIO2
PIRQF#/GPIO3
PIRQG#/GPIO4
PIRQH#/GPIO5
RN56
H4
K6
F2
G2
PCI_PIRQE#
PCI_PIRQF#
PCI_PIRQG#
PCI_PIRQH#
PCI_SERR#
PCI_PIRQE#
PCI_PIRQA#
PCI_PIRQC#
8
7
6
5
1
2
3
4
SRN8K2J-4-GP
C
RP1
USB_OC#7
USB_OC#11
USB_OC#5
USB_OC#4
+3.3V_ALW
PCI_GNT0#
1
R442
SPI_CS#1
1
R443
PCI_GNT3#
1
R441
RN55
1
2
3
4
5
10
9
8
7
6
+3.3V_ALW
USB_OC#0
USB_OC#1
USB_OC#6
USB_OC#2
8
7
6
5
+3.3V_ALW
USB_OC#9
USB_OC#8
USB_OC#10
USB_OC#3
1
2
3
4
SRN8K2J-4-GP
DY
DY
DY
1KR2J-1-GP
1KR2J-1-GP
1KR2J-1-GP
BOOT BIOS Strap
SRN10KJ-L3-GP
PCI_GNT#0
SPI_CS#1
BOOT BIOS Location
4 OF 6
U25D
LAN
20
20
New Card
20
20
41
41
41
41
PERN2
PERP2
PETN2
PETP2
PCIE_RXN2
PCIE_RXP2
PCIE_TXN2
PCIE_TXP2
C500 2
C497 2
1 SCD1U16V2KX-3GP
1 SCD1U16V2KX-3GP
PCIE_C_TXN2
PCIE_C_TXP2
L29
L28
M27
M26
PCIE_RXN3
PCIE_RXP3
PCIE_TXN3
PCIE_TXP3
C506 2
C510 2
1 SCD1U16V2KX-3GP
1 SCD1U16V2KX-3GP
PCIE_C_TXN3
PCIE_C_TXP3
J29
J28
K27
K26
PERN3
PERP3
PETN3
PETP3
G29
G28
H27
H26
PERN4
PERP4
PETN4
PETP4
E29
E28
F27
F26
PERN5
PERP5
PETN5
PETP5
PCIE_RXN5
PCIE_RXP5
PCIE_TXN5
PCIE_TXP5
C518 2
C517 2
1 SCD1U16V2KX-3GP
1 SCD1U16V2KX-3GP
PCIE_C_TXN5
PCIE_C_TXP5
C29
C28
D27
D26
SPI_CLK
SPI_CS#0
SPI_MOSI
SPI_MOSO
ICH_GND1
ICH_GND2
ICH_GND3
ICH_GND4
R233 1
R241 1
R230 1
R237 1
45
45
43
TP177
DY
DY
2 15R2J-GP
2 15R2J-GP
DY
DY
2 15R2J-GP
2 15R2J-GP
D23
D24
F23
SPI_MOSI_R
SPI_MOSO_R
D25
E23
USB_OC#0
USB_OC#1
USB_OC#2
USB_OC#3
USB_OC#4
USB_OC#5
USB_OC#6
USB_OC#7
USB_OC#8
USB_OC#9
USB_OC#10
USB_OC#11
USB_OC#0
USB_OC#1
USB_OC#2
TP178
NCTF PIN
TP125
TP127
R208
1
SPI_CLK_R
SPI_CS#0_R
SPI_CS#1
22R2F-1-GP
N4
N5
N6
P6
M1
N2
M4
M3
N3
N1
P5
P3
USB_RBIAS_PN AG2
AG1
DMI0RXN
DMI0RXP
DMI0TXN
DMI0TXP
V27
V26
U29
U28
DMI_RXN0
DMI_RXP0
DMI_TXN0
DMI_TXP0
9
9
9
9
DMI1RXN
DMI1RXP
DMI1TXN
DMI1TXP
Y27
Y26
W29
W28
DMI_RXN1
DMI_RXP1
DMI_TXN1
DMI_TXP1
9
9
9
9
DMI2RXN
DMI2RXP
DMI2TXN
DMI2TXP
AB27
AB26
AA29
AA28
DMI_RXN2
DMI_RXP2
DMI_TXN2
DMI_TXP2
9
9
9
9
DMI3RXN
DMI3RXP
DMI3TXN
DMI3TXP
AD27
AD26
AC29
AC28
DMI_RXN3
DMI_RXP3
DMI_TXN3
DMI_TXP3
9
9
9
9
T26
T25
CLK_PCIE_ICH# 4
CLK_PCIE_ICH 4
DMI_CLKN
DMI_CLKP
DMI_ZCOMP
DMI_IRCOMP
PERN6/GLAN_RXN
PERP6/GLAN_RXP
PETN6/GLAN_TXN
PETP6/GLAN_TXP
USBP0N
USBP0P
USBP1N
USBP1P
SPI_CLK
USBP2N
SPI_CS0#
USBP2P
SPI_CS1#/GPIO58/CLGPIO6 USBP3N
USBP3P
SPI_MOSI
USBP4N
SPI_MISO
USBP4P
USBP5N
OC0#/GPIO59
USBP5P
OC1#/GPIO40
USBP6N
OC2#/GPIO41
USBP6P
OC3#/GPIO42
USBP7N
OC4#/GPIO43
USBP7P
OC5#/GPIO29
USBP8N
OC6#/GPIO30
USBP8P
OC7#/GPIO31
USBP9N
OC8#/GPIO44
USBP9P
OC9#/GPIO45
USBP10N
OC10#/GPIO46
USBP10P
OC11#/GPIO47
USBP11N
USBP11P
USBRBIAS
USBRBIAS#
USB
AF29
AF28
AC5
AC4
AD3
AD2
AC1
AC2
AA5
AA4
AB2
AB3
AA1
AA2
W5
W4
Y3
Y2
W1
W2
V2
V3
U5
U4
U1
U2
USB_PN5
USB_PP5
USB_PN8
USB_PP8
USB_PN9
USB_PP9
USB_PN10
USB_PP10
SPI
PCI
LPC(Default)
A16 swap override strap

PCI_GNT#3
low = A16 swap override enable

high = default
+1.5V_RUN
DMI_IRCOMP_R
USB_PN3
USB_PP3
37
37
PERN1
PERP1
PETN1
PETP1
R429
24D9R2F-L-GP
USB
Pair
0
USB1
USB2
USB3
USB_PN0 45
USB_PP0 45
USB_PN1 45
USB_PP1 45
USB_PN2 43
USB_PP2 43
TP246
TP247
USB_PN4 37
USB_PP4 37
TP250
TP251
USB_PN6 41
USB_PP6 41
USB_PN7 41
USB_PP7 41
TP248
TP249
TP252
TP253
USB_PN10 21
USB_PP10 21
USB_PN11 41
USB_PP11 41
USB1
USB2
USB3
BlUETOOTH
New Card
RESERVED
MINI CARD
RESERVED
BLUETOOTH
NEW CARD
RESERVED
RESERVED
10
Card Reader
11
CAMERA
Wistron Corporation
Card Reader
CAMERA
Title
ICH9-PCI/PCIE/DMI/USB/GND(1/4)
Rev
Size
Document Number
Custom
ICH9M-GP-NF
<Core Design>

4
Device
Mini Card
N29
N28
P27
P26
PCI-Express
37
37
ICH9M-GP-NF
8
7
6
5
ICH9M-GP-NF
Direct Media Interface
H5
J23
J26
J27
AC22
K28
K29
L13
L15
L2
L26
L27
L5
L7
M12
M13
M14
M15
M16
M17
M23
M28
M29
N11
N12
N13
N14
N15
N16
N17
N18
N26
N27
P12
P13
P14
P15
P16
P17
P2
P23
P28
P29
P4
P7
R11
R12
R13
R14
R15
R16
R17
R18
R28
T12
T13
T14
T15
T16
T17
T23
B26
U12
U13
U14
U15
U16
U17
AD23
U26
U27
U3
V1
V13
V15
V23
V28
V29
V4
V5
W26
W27
W3
Y1
Y28
Y29
Y4
Y5
AG28
AH6
AF2
B25
SPI
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
U32
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
+3.3V_RUN
2 OF 6
SSID = ICH
AA26
AA27
AA3
AA6
AB1
AA23
AB28
AB29
AB4
AB5
AC17
AC26
AC27
AC3
AD1
AD10
AD12
AD13
AD14
AD17
AD18
AD21
AD28
AD29
AD4
AD5
AD6
AD7
AD9
AE12
AE13
AE14
AE16
AE17
AE2
AE20
AE24
AE3
AE4
AE6
AE9
AF13
AF16
AF18
AF22
AH26
AF26
AF27
AF5
AF7
AF9
AG13
AG16
AG18
AG20
AG23
AG3
AG6
AG9
AH12
AH14
AH17
AH19
AH2
AH22
AH25
AH28
AH5
AH8
AJ12
AJ14
AJ17
AJ8
B11
B14
B17
B2
B20
B23
B5
B8
C26
C27
E11
E14
E18
E2
E21
E24
E5
E8
F16
F28
F29
G12
G14
G18
G21
G24
G26
G27
G8
H2
H23
H28
H29
A00
Roberts
Sheet
1
16
of
58
SSID = ICH
ICH_RTCX1
R445 1
2 10MR2J-L-GP
ICH_RTCX2
X4
1
4
1
C522
SC12P50V2JN-3GP
C520
SC12P50V2JN-3GP
X-32D768KHZ-38GPU
LPC_LAD[0..3]
1 OF 6
+RTC_CELL
ICH_RTCRST#
SRTCRST#
SM_INTRUDER#
A25
F20
C22
RTCRST#
SRTCRST#
INTRUDER#
ICH_INTVRMEN
LAN100_SLP
B22
A22
INTVRMEN
LAN100_SLP
E25
GLAN_CLK
C13
LAN_RSTSYNC
R461
2
1
C526
SC1U10V3KX-3GP
20KR2F-L-GP
+1.5V_RUN
R506
Place within 500 mil of SB.

R444 1
22
22
22
22
R201
R197
R205
R194
ICH_AZ_CODEC_BITCLK
ICH_AZ_CODEC_SYNC
ICH_AZ_CODEC_RST#
ICH_SDOUT_CODEC
2 24D9R2F-L-GP
1
1
1
1
2
2
2
2
DY
2GPIO56
10KR2J-3-GP GLAN_COMP
33R2J-2-GP
33R2J-2-GP
33R2J-2-GP
33R2J-2-GP
HDD
B
ODD
36 SATA_RXN1_C
36 SATA_RXP1_C
36 SATA_TXN1
36 SATA_TXP1
C475 1
C476 1
2 SCD01U50V2KX-1GP
2 SCD01U50V2KX-1GP
2 SCD01U50V2KX-1GP
2 SCD01U50V2KX-1GP
GLAN_DOCK#/GPIO56
B28
B27
GLAN_COMPI
GLAN_COMPO
HDA_BIT_CLK
HDA_SYNC
HDA_RST#
SATA_LED#
C473 1
C474 1
B10
AE7
ACZ_SDATAOUT_R
36 SATA_RXN0_C
36 SATA_RXP0_C
36 SATA_TXN0
36 SATA_TXP0
LAN_TXD0
LAN_TXD1
LAN_TXD2
AF6
AH4
C230
SC4D7P50V2CN-1GP
TP235
D13
D12
E13
ACZ_RST#_R
DY
2
1
2
DY
LAN_RXD0
LAN_RXD1
LAN_RXD2
ACZ_BIT_CLK
ACZ_SYNC_R
22 ICH_SDIN_CODEC
C227
SC4D7P50V2CN-1GP
F14
G13
D14
SATA_TXN0_C
SATA_TXP0_C
SATA_TXN1_C
SATA_TXP1_C
AF4
AG4
AH3
AE5
HDA_SDIN0
HDA_SDIN1
HDA_SDIN2
HDA_SDIN3
AG5
HDA_SDOUT
AG7
AE8
HDA_DOCK_EN#/GPIO33
HDA_DOCK_RST#/GPIO34
AG8
SATALED#
AJ16
AH16
AF17
AG17
SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP
AH13
AJ13
AG14
AF14
SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP
IHDA
1
+RTC_CELL
SATA
G49
GAP-OPEN
LAN / GLAN
CPU
RTCX1
RTCX2
ICH_RTCRST#
20KR2F-L-GP
C307
SC1U10V3KX-3GP
C23
C24
RTC
LPC
U25A
R456
FWH0/LAD0
FWH1/LAD1
FWH2/LAD2
FWH3/LAD3
K5
K4
L6
K2
FWH4/LFRAME#
K3
LDRQ0#
LDRQ1#/GPIO23
J3
J1
LPC_LAD[0..3]
R438
1
DY
10KR2J-3-GP
N7
AJ27
DPRSTP#
DPSLP#
AJ25
AE23
H_DPRSTP#
FERR#
AJ26
H_FERR#_R
CPUPWRGD
AD22
H_PWRGOOD 6,34
IGNNE#
AF25
H_IGNNE# 5
INIT#
INTR
RCIN#
AE22
AG25
L3
H_INIT# 5
H_INTR 5
NMI
SMI#
AF23
AF24
H_NMI 5
H_SMI# 5
STPCLK#
AH27
THRMTRIP#
AG26
PECI
AG27
SATA4RXN
SATA4RXP
SATA4TXN
SATA4TXP
AH11
AJ11
AG12
AF12
SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP
AH9
AJ9
AE10
AF10
SATA_CLKN
SATA_CLKP
AH18
AJ18
AJ7
AH7
+3.3V_RUN
LPC_LFRAME# 24,37
A20GATE
A20M#
SATARBIAS#
SATARBIAS
24,37
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
KA20GATE 24
H_A20M# 5
+1.05V_VCCP
R163
1
H_DPRSTP# 6,9,28
H_DPSLP# 6
1
R166
56R2J-4-GP
2
56R2J-4-GP
H_FERR# 5
+3.3V_RUN
R242
1
DY
10KR2J-3-GP
KBRCIN#
H_STPCLK# 5
H_THERMTRIP_R
1
R165
24
+1.05V_VCCP
R164
2
56R2J-4-GP
R167
2 H_THERMTRIP_1
54D9R2F-L1-GP
Placed Within 2" from SB.
2
0R2J-2-GP
A00.08/0903
CLK_PCIE_SATA# 4
CLK_PCIE_SATA 4
SATARBIAS
1
R187
2
24D9R2F-L-GP
Place within 500 mils from SB.
ICH9M-GP-NF
+RTC_CELL
R448
2
ICH_INTVRMEN
1
330KR2F-L-GP
integrated VccSus1_05,VccSus1_5,VccCL1_5
INTVRMEN
High=Enable
Low=Disable
<Core Design>
integrated VccLan1_05VccCL1_05
R271
2
LAN100_SLP
LAN100_SLP
High=Enable
Wistron Corporation
Low=Disable

330KR2F-L-GP
Title
R264
2
SM_INTRUDER#
ICH9-LAN/HDA/SATA/LPC(2/4)
Size
Document Number
Custom
1MR2J-1-GP

5
Sheet
1
Rev
A00
Roberts
17
of
58
SSID = ICH
+3.3V_RUN
3 OF 6
SMB_ALERT#
TP186
4
4
SRN10KJ-5-GP
A17
H_STP_PCI#
H_STP_CPU#
H_STP_PCI#
H_STP_CPU#
A14
E19
L4
24 PM_CLKRUN#
R455 1
2 10KR2J-3-GP
PCIE_WAKE#
RN61
8
7
6
5
SMB_ALERT#
PM_BATLOW#_R
ITP_DBRESET#_1
ICH_RI#
1
2
3
4
SRN8K2J-4-GP
R451 1
2 10KR2J-3-GP
ECSMI#
24,28 VGATE_PWRGD
DY
H_STP_CPU#
H_STP_PCI#
1
2
SST
24
24
ECSWI#
ECSMI#
TP181
ECSWI#
ECSMI#
GPIO12
GPIO13
GPIO17
GPIO18
GPIO20
GPIO22
GPIO27
GPIO28
CLK_SEL0
CLK_SEL1
GPIO48
TP124
iTPM_EN
SRN10KJ-5-GP
1
1
2
2
2
2
2
DY
2
2
1
1
1
1
1
8K2R2J-3-GP
8K2R2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
8K2R2J-3-GP
10KR2J-3-GP
PM_CLKRUN#
INT_SERIRQ
GPIO18
ECSCI#
ECSWI#
GPIO22
CLKSATAREQ#
ICH_TP3
PM_SLP_S4# 24,31,41
TP259
S4_STATE#/GPIO26
C10
GPIO26
TP182
PWROK
G20
PM_PWROK
AG19
AH21
AG21
A21
C12
C21
AE18
K1
AF8
AJ22
A9
D19
L1
AE19
AG22
AF21
AH24
A8
TACH1/GPIO1
TACH2/GPIO6
TACH3/GPIO7
GPIO8
LAN_PHY_PWR_CTRL/GPIO12
ENERGY_DETECT/GPIO13
TACH0/GPIO17
GPIO18
GPIO20
SCLOCK/GPIO22
GPIO27
GPIO28
SATACLKREQ#/GPIO35
SLOAD/GPIO38
SDATAOUT0/GPIO39
SDATAOUT1/GPIO48
GPIO49
GPIO57/CLGPIO5
M7
AJ24
B21
AH20
AJ20
AJ21
SPKR
MCH_SYNC#
TP3
PWM0
PWM1
PWM2
DPRSLPVR/GPIO16
M2
BATLOW#
B13
PWRBTN#
R3
LAN_RST#
D20
RSMRST#
D22
ICH_SUSCLK
25
PM_PWRBTN# 24
LAN_RST#1
R5
CLPWROK
R6
M_PWROK
SLP_M#
B16
PM_SLP_M#
CL_CLK0
CL_CLK1
F24
B19
CL_DATA0
CL_DATA1
F22
C19
CL_VREF0
CL_VREF1
C25
A19
CL_RST0#
CL_RST1#
F21
D18
GPIO24/MEM_LED
GPIO10/SUS_PWR_ACK
GPIO14/AC_PRESENT
GPIO9/WOL_EN
A16
C18
C11
C20
DY DY
2
2
2
2
2
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
1 R439
2
0R0402-PAD
PM_PWROK 9,24,25
CL_CLK0 9
C
CL_DATA0 9
CL_VREF0_ICH
CL_VREF1_ICH
CL_RST#0 9
GPIO24
GPIO10
GPIO14
+3.3V_ALW
TP180
R268
3K24R2F-GP
1
R185
10KR2J-3-GP
1 = Enable
0 = Disable
DY
DY
DY
DY
DY
+3.3V_RUN
R454
3K24R2F-GP
DY
DY
CLK Gen select
CLK_SEL0
CLK_SEL1
iTPM_EN
R446
100KR2J-1-GP
DY DY
1
1
1
1
1
10KR2J-3-GP
100KR2J-1-GP
0R0402-PAD
10KR2J-3-GP
CLK Gen Select

R423
10KR2J-3-GP
R427
10KR2J-3-GP
iTPM_EN
DY
R501
R502
R503
R504
R505
M_PWROK
M_PWROK 9
+3.3V_RUN
R179
10KR2J-3-GP
GPIO10
GPIO13
GPIO14
GPIO17
GPIO48
DY
2
2
2
2
TP183
+3.3V_RUN
iTPM Select
1
1
1
1
CK_PWRGD 4
ICH9M-GP-NF
R449
100KR2J-1-GP
R440
R232
R266
R447
RSMRST#_KBC 24
CK_PWRGD
DY
PM_PWROK
DPRSLPVR
LAN_RST#1
RSMRST#_KBC
DPRSLPVR 9,28
PM_BATLOW#_R
R235
R244
R247
R421
R424
R180
R238
22
SB_SPKR
9 MCH_ICH_SYNC#
TP263
WAKE#
SERIRQ
THRM#
VRMPWRGD
ECSCI#
RN63
4
3
CLKRUN#
A20
ECSCI#
TP168
TP236
TP123
TP184
TP262
CLKSATAREQ#
STP_PCI#
STP_CPU#
D21
24
PM_SLP_S5#
SMBALERT#/GPIO11
ICH_TP7
DY
2 0R2J-2-GP
E20
M5
AJ23
SB_SLP_S3#
PMSYNC#/GPIO0
VGATE_PWRGD
R263 1
+3.3V_RUN
PCIE_WAKE#
INT_SERIRQ
20,41 PCIE_WAKE#
24 INT_SERIRQ
25 THERM_SCI#
ICH_SUSCLK
C16
E16
G17
4
3
M6
PM_SYNC#
P1
9
RN59
SUSCLK
SLP_S3#
SLP_S4#
SLP_S5#
SUS_STAT#/LPCPD#
SYS_RESET#
R4
G19
R450
453R2F-1-GP
SUS_STAT#
ITP_DBRESET#_1
1
2
ME_EC_DATA1
ME_EC_CLK1
TP257
37 ITP_DBRESET#_1
LINKALERT#
1
2
3
4
SRN10KJ-6-GP
CLK_14M_ICH 4
CLK_48M_ICH 4
C523
SCD1U10V2KX-4GP
2 10KR2J-3-GP
8
7
6
5
R267 1
H1
AF3
C309
SCD1U10V2KX-4GP
CLK14
CLK48
SATA2GP
SATA3GP
SATA1GP
SATA0GP
RI#
SATA0GP
SATA1GP
SATA2GP
SATA3GP
F19
AH23
AF19
AE21
AD20
R261
453R2F-1-GP
ICH_RI#
SRN2K2J-1-GP
SATA0GP/GPIO21
SATA1GP/GPIO19
SATA4GP/GPIO36
SATA5GP/GPIO37
SMB_DATA
SMB_CLK
1
2
SMBCLK
SMBDATA
LINKALERT#/GPIO60/CLGPIO4
SMLINK0
SMLINK1
SATA
GPIO
4
3
G16
A13
E17
C17
B18
Clocks
RN60
LINKALERT#
ME_EC_CLK1
ME_EC_DATA1
SYS GPIO
Power MGT
37,41
SMB_CLK
37,41 SMB_DATA
MISC
GPIO
Controller Link
+3.3V_ALW
RN49
SMB
U25C
Disable
Seligo
Realtek
ICS
CLK_SEL0
CLL_SEL1
X
1
1
0
X
1
0
1
+3.3V_ALW
U29
SB_SLP_S3#
VCC
DY
PM_SLP_S3#
PM_SLP_S3# 24,25,30,31,32,34,41
GND
74LVC1G08GW-1-GP
+3.3V_RUN
1 R265
2
0R0402-PAD
RN62
4
3
1
2
SRN2K2J-1-GP
4,14,15 ICH_SMBDATA
SMB_CLK
<Core Design>
U56
1
SMB_DATA
Wistron Corporation
ICH_SMBCLK 4,14,15
Title
ICH9-GPIO/PM/CL(3/4)
2N7002SPT
Size
Document Number
Custom

5
Sheet
1
Rev
A00
Roberts
18
of
58
+RTC_CELL
3D3V_GLAN_S0
0R3-0-U-GP A00.08/0909
F18
0R3-0-U-GP
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
A18
D16
D17
E22
VCCSUS3_3
AF1
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
T1
T2
T3
T4
T5
T6
U6
U7
V6
V7
W6
W7
Y6
Y7
T7
VCCCL1_05
G22
VCCCL1_5
G23
VCCCL3_3
VCCCL3_3
A24
B24
C503
SCD1U10V2KX-4GP
2
1
1
VCCSUS1_5[3]
A27
VCCGLANPLL 23mA
D28
D29
E26
E27
VCCGLAN1_5
VCCGLAN1_5
VCCGLAN1_5
VCCGLAN1_5
A26
VCCGLAN3_3 1mA
2
SB_VCCCL3_3
1 R452
2
0R0603-PAD
2
1
2
1
2
C217
SCD1U10V2KX-4GP
C516
SCD1U10V2KX-4GP
1
2
C302
SCD1U10V2KX-4GP
ICH9M-GP-NF
1
2
1
2
DY
<Core Design>
A00.08/0909
+3.3V_RUN
C221
SCD1U10V2KX-4GP
1 R436
2
0R0603-PAD
VCCSUS1_05[3]
VCCLAN3_3 78mA
VCCLAN3_3
+3.3V_ALW
VCCLAN1_05
VCCLAN1_05
A12
B12
A10
A11
C490
SCD022U16V2KX-3GP
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
1 R270
2
0R0603-PAD
Wistron Corporation
Title
ICH9-POWER(4/4)
Size
Document Number
Custom

5
1 R188
2
0R0402-PAD
DY
AA7
AB6
AB7
AC6
AC7
11mA
C509
SCD1U10V2KX-4GP
2
1
2
VCCUSBPLL
AJ5
C313
SCD1U10V2KX-4GP
VCC1_5_A
VCC1_5_A
VCC1_5_A
AC12
AC13
AC14
DY
VCC1_5_A
VCC1_5_A
SB_VCCSUS3_3
C491
SCD1U16V2KX-3GP
VCC1_5_A
G10
G9
C507
SCD1U10V2KX-4GP
308mA
AC21
SB_VCCHDA
VCC1_5_A
VCC1_5_A
+3.3V_RUN
+3.3V_ALW
AC18
AC19
+1.5V_RUN
1 R177
2
0R0603-PAD
C308
SCD1U10V2KX-4GP
VCC1_5_A
AC9
C515
SCD1U10V2KX-4GP
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
R172
DY
VCCSUS1_5
TP243
TP260
VCCSUS1_5[2]
1
1
C231
SC4D7U6D3V3KX-GP
VCCSUS1_5[1]
VCCSUS1_5
AD8
+3.3V_ALW
1 R191
2
0R0402-PAD
VCCSUS1_05[1]
VCCSUS1_05[2]
+3.3V_RUN
SB_VCC_3_3_C
C223
SCD1U10V2KX-4GP
AC8
F17
VCCSUS1_05
VCCSUS1_05
11mA VCCSUSHDA
C479
SCD1U10V2KX-4GP
SB_VCCHDA
1 R437
2
0R0603-PAD
AJ4
AJ3
1 R431
2
0R0603-PAD
+3.3V_RUN
11mA VCCHDA
DY
EC56
SCD1U25V3KX-GP
PCI_VCCP_CORE_S0
C478
SCD1U10V2KX-4GP
B9
F9
G3
G6
J2
J7
K7
C252
SC10U6D3V5MX-3GP
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
C477
SCD1U10V2KX-4GP
C232
SC1U10V3KX-3GP
C265
SC10U6D3V5MX-3GP
C263
SCD01U16V2KX-3GP
2
1
AD19
AF20
AG24
AC20
C253
SC4D7U6D3V3KX-GP
1
2
C492
SCD1U10V2KX-4GP
C495
SCD1U10V2KX-4GP
C501
SCD1U10V2KX-4GP
C496
SCD1U10V2KX-4GP
C488
SCD1U10V2KX-4GP
1634mA
CORE
VCC3_3
VCC3_3
VCC3_3
VCC3_3
SB_V_CPU_IO
C514
SCD1U10V2KX-4GP
R453
1
3D3V_VCCPCORE_ICH_S0
+1.05V_VCCP
+3.3V_RUN
C511
SCD1U10V2KX-4GP
+3.3V_RUN
VCC3_3
AC10
1 R434
2
0R0603-PAD
1 R430
2
0R0603-PAD
C279
SCD1U10V2KX-4GP
1
2
DY
AC11
AD11
AE11
AF11
AG10
AG11
AH10
AJ10
80mA
C276
SC4D7U6D3V3KX-GP
SB_VCC_3_3_C
GLAN POWER
VCC_GLAN_PLL
AJ6
+1.05V_VCCP
+1.5V_RUN
VCC3_3
SB_VCCLAN3_3
VCC3_3
SB_V_CPU_IO
C493
SCD1U10V2KX-4GP
C485
SCD1U10V2KX-4GP
1
1
C483
SCD1U10V2KX-4GP
1
2
DY
AB23
AC23
AG29
+1.5V_RUN
L5
2
1
IND-1D2UH-5-GP
C513
SC1U10V3KX-3GP
C521
SCD1U10V2KX-4GP
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
A00.08/0909
VCCDMI
VCCLAN1D05
VCCSATAPLL47mA
AC16
AD15
AD16
AE15
AF15
AG15
AH15
AJ15
USB CORE
DY
C482
SCD1U10V2KX-4GP
1D5V_USB_S0
C222
SCD1U10V2KX-4GP
1 R183
2
0R0603-PAD
C480
SCD1U10V2KX-4GP
+1.5V_RUN
DY
1D5V_DMIPLL_ICH_S0
V_CPU_IO
VCCP_CORE
C251
SC2D2U10V3KX-1GP
C219
SC1U10V3KX-3GP
1
1
C220
SC1U10V3KX-3GP
1
2
C312
SC10U6D3V5MX-3GP
1
2
1
2
+1.5V_RUN
DY
2mA V_CPU_IO
1342mA
C303
SC2D2U10V3KX-1GP
L7
2
1 VCC_GLAN_PLL
IND-1D2UH-5-GP
AJ19
ATX
C481
SC1U10V3KX-3GP
+1.5V_RUN
+1.5V_RUN
1
2
C301
SCD1U10V2KX-4GP
1
2
1
2
DY
W23
Y23
VCCDMI
ARX
C306
SCD1U10V2KX-4GP
SB_VCCLAN3_3
C213
SC10U6D3V5MX-3GP
1
2
L-10UH-11-GP
1 R269
2
0R0603-PAD
1
2
+VCCSATAPLL
L4
R29
50mA VCCDMI
DY
1D5V_DMIPLL_ICH_S0
+1.5V_RUN
+3.3V_RUN
C244
SC10U6D3V5MX-3GP
1
2
DY
C246
SC10U6D3V5MX-3GP
TC9
ST220U2D5VBM-LGP
DY
C512
SCD1U10V2KX-4GP
1
2
DY
23mA VCCDMIPLL
2mA
VCCA3GP
C489
SCD1U10V2KX-4GP
+1.5V_RUN
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
PCI
C242
SCD1U16V2KX-3GP
V5REF_SUS
646mA
C304
SC1U10V3KX-3GP
AE1
AA24
AA25
AB24
AB25
AC24
AC25
AD24
AD25
AE25
AE26
AE27
AE28
AE29
F25
G25
H24
H25
J24
J25
K24
K25
L23
L24
L25
M24
M25
N23
N24
N25
P24
P25
R24
R25
R26
R27
T24
T27
T28
T29
U24
U25
V24
V25
U23
W24
W25
K23
Y24
Y25
A15
B15
C15
D15
E15
F15
L11
L12
L14
L16
L17
L18
M11
M18
P11
P18
T11
T18
U11
U18
V11
V12
V14
V16
V17
V18
VCCPSUS
2
1
2
1
R213
10R2J-2-GP
V5REF_S5
+5V_ALW
D14
CH751H-40PT
2
R274
10R2J-2-GP
1
+3.3V_ALW
+5V_RUN
D15
CH751H-40PT
+3.3V_RUN
V5REF 2mA
212mA
V5REF_S5
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCCRTC
A6
VCCPUSB
V5REF_S0
73mA
C525
SCD1U10V2KX-4GP
C524
SCD1U10V2KX-4GP
A23
*Within a given well, 5VREF needs to

be up before the corresponding 3.3V rail
V5REF_S0
+1.05V_VCCP
U25F
SSID = ICH
6 OF 6
Rev
A00
Roberts
Sheet
1
19
of
58
SSID = LOM
+2.5V_LOM
NC#34
NC#35
36
37
NC#36
NC#37
33
39
44
48
58
2
7
13
VDD25
AVDDL
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
PCIE_TXN
PCIE_TXP
50
49
PCIE_RXN
PCIE_RXP
53
54
LED_LINK#
NC#62
LED_SPEED#
LED_ACT#
63
62
60
59
24
25
HSDACP
HSDACN
XTALI
XTALO
15
14
41
38
RXP
TXP
NC#26
NC#30
17
20
26
30
RXN
TXN
NC#27
NC#31
18
21
27
31
LAN_RXN3
LAN_RXP3
C285 1
C284 1
2 SCD1U10V2KX-4GP
2 SCD1U10V2KX-4GP
LANX1
LANX2
R228
2
MDI0+
MDI1+
MDI0+
MDI1+
1
C
+3.3V_LAN
X2
LANX2 1
R236
1
LANX1
XTAL-25MHZ-96GP
C259
SC12P50V2JN-3GP
MDI0MDI1-
2VPD_DATA
45
45
MDI0MDI1-
DY
10MR2J-L-GP
+3.3V_LAN
45
45
PCIE_RXN3 16
PCIE_RXP3 16
PCIE_TXN3 16
PCIE_TXP3 16
GND
LANHP
LANHN
PCIE_WAKE# 18,41
PLT_RST# 9,16,21,24,37,41
CLK_PCIE_LAN 4
CLK_PCIE_LAN# 4
65
1
1
PU_VDDO_TTL#42
PU_VDDO_TTL#43
TP136
TP139
C
42
43
DY
DY
LANSC
LANPWR
LANSV
LANRSET
CTRL12
CTRL25
TSTPT
TESTMODE
A00.08/0903
1 R246
2
0R0402-PAD
R221 1
2 2KR2F-3-GP
R243 1
2 10KR2J-3-GP
R239 1
2 10KR2J-3-GP
LOM_DISABLE#
VAUX_AVLBL
SWITCH_VCC
VMAIN_AVLBL
SWITCH_VAUX
RSET
PD_12
PD_25
29
46
+3.3V_LAN
10
12
11
47
9
16
3
4
VPD_DATA
VPD_CLK
LOM_DISABLE#
1
6
5
55
56
88E8040-A0-NNC1C000-GP
+3.3V_LAN
TP145
+3.3V_RUN
TP147
WAKE#
PERST#
REFCLKP
REFCLKN
4K7R2J-2-GP
34
35
R229
VDDO_TTL
VDDO_TTL
VDDO_TTL
VDDO_TTL
VDDO_TTL
+3.3V_LAN
64
23
1
8
40
45
61
AVDDL
AVDD
AVDD
AVDDL
AVDDL
AVDDL
AVDDL
U26
+1.2V_LOM
1
1
57
52
51
32
28
22
19
TP270
TP269
+3.3V_LAN
C260
SC12P50V2JN-3GP
C268 1
2 SC1KP50V2KX-1GP
C283 1
2 SC1U10V3KX-3GP
C281 1
2 SC1U10V3KX-3GP
4K7R2J-2-GP
R231
R234
DY0R2J-2-GP
+2.5V_LOM
2
4K7R2J-2-GP
C257 1
2 SCD1U10V2KX-4GP
C258 1
2 SC1KP50V2KX-1GP
C255 1
C288 1
2 SC1KP50V2KX-1GP
SC4D7U6D3V5KX-3GP
2 SC1U10V3KX-3GP
C291 1
+1.2V_LOM
+3.3V_LAN
+3.3V_RUN
R507
R248
DY
2
0R3-0-U-GP
DY
2
0R3-0-U-GP
Q14
S
C286
SC10U6D3V5MX-3GP
1
2
C271
SC4D7U6D3V5KX-3GP
1
2
C290
SC4D7U6D3V5KX-3GP
C266
SCD1U10V2KX-4GP
2
Q15
2N7002-7F-GP
AO3403-GP
C269
SCD1U10V2KX-4GP
MDI0+
2
D
C296
SCD1U10V2KX-4GP
R257
10KR2J-3-GP
MDI0MDI1+
MDI1-
1
R222
1
R223
1
R225
1
R224
DY
DY
DY
DY
MDIS0_LAN
49D9R2F-GP
1
C247
DY
49D9R2F-GP
2 MDIS1_LAN
49D9R2F-GP
2
49D9R2F-GP
1
C248
DY2SCD01U16V2KX-3GP
2 SC1U10V3KX-3GP
C267 1
2 SC1KP50V2KX-1GP
C282 1
2 SC1U10V3KX-3GP
C270 1
2 SC1KP50V2KX-1GP
C292 1
2 SC1U10V3KX-3GP
C261 1
2 SC1KP50V2KX-1GP
C278 1
2 SC4D7U6D3V5KX-3GP
2
SCD01U16V2KX-3GP
<Core Design>
Wistron Corporation
24 PM_LAN_ENABLE
+3.3V_ALW
C264 1

Title
LAN Marvell-88E8040
Size
Document Number
Custom

5
Sheet
1
Rev
A00
Roberts
20
of
58
SSID = SDIO
Please close to pin8.
+3.3V_PHY
D
1 R259
2
0R0603-PAD
+3.3V_PHY
2
MODE_SEL
2CARD_RST#_R
45
36
14
2
44
5
4
USB_PP10
USB_PN10
XTAL_CTR
13
XTAL_CTR
XTLI
XTLO
47
48
EESK
EECS
17
16
CARD_EESK
CARD_EECS
EEDO
EEDI
15
18
CARD_EEDO
CARD_EEDI
R510
1
DY
C318
SC1U10V2KX-1GP
PLT_RST# 9,16,20,24,37,41
2K2R2J-2-GP
C568
SC1U10V2KX-1GP
A00.08/1002
R272
2 10KR2J-3-GP
+3.3V_PHY
GND
GND
GND
GND
CLK_48M_CARD 4
6
12
32
46
NC#30
NC#7
NC#3
A00.08/0902
DP
DM
R284
100KR2J-1-GP
DY
RTS5158E-GRT-GP
30
7
3
R283
499KR2F-1-GP
A00.08/1002
MODE_SEL
SD_CMD
GPIO0
RREF
RST#
33
11
D3V3
D3V3
10
VREG
3V3_IN
AV_PLL
SP1
SP2
SP3
SP4
SP5
SP6
SP7
SP8
SP9
SP10
SP11
SP12
SP13
SP14
SP15
SP16
SP17
SP18
SP19
CARD_3V3
19
20
21
23
25
26
27
28
29
31
34
35
37
38
39
40
41
42
43
MS_D5
MS_D4
XD_CD#
SD_WP
SD_CD#
XD_D4/SD_DAT1
XD_D5/MS_BS
XD_D3/MS_D1
SD_DAT0/XD_D6/MS_D0
XD_D2/MS_D2
MS_INS#
XD_D7/MS_D3
SD_CLK/XD_D1/MS_CLK
XD_D0
XD_WP#
XD_RDY
SD_DAT3/XD_WE#
SD_DAT2/XD_RE#
XD_ALE
XD_CE#
XD_CLE
24
22
XD_CD#
SD_WP
SD_CD#
XD_D4/SD_DAT1
XD_D5/MS_BS
XD_D3/MS_D1
SD_DAT0/XD_D6/MS_D0
XD_D2/MS_D2
MS_INS#
XD_D7/MS_D3
SD_CLK/XD_D1/MS_CLK
XD_D0
XD_WP#
XD_RDY
SD_DAT3/XD_WE#
SD_DAT2/XD_RE#
XD_ALE
XD_CE#
XD_CLE
U34
1
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
DY
6K2R2F-GP
37
R282
CARD_RST#
BLM18BD601SN1D-GP
C299
SCD1U16V2KX-3GP
SD_CMD
R260
CARD_RREF
SD_CMD
+3.3V_RUN_CARD
Please close to pin11 and pin33.
C320
SC4D7U6D3V3KX-GP
C300
SCD1U16V2KX-3GP
C297
SC1U6D3V2KX-GP
C298
SC1U6D3V2KX-GP
1
2
+3.3V_RUN
VREG
C310
SCD1U16V2KX-3GP
1
2
C319
SCD1U16V2KX-3GP
+3.3V_PHY
D
37
MS_CLK
MS_CLK
L6
DLW21SN900SQ2LUGP
USB_PN10
USB_PP10
1 R250
2
0R0402-PAD
DY
1 R249
2
0R0402-PAD
DY DY
2
C273
SC15P50V2JN-2-GP
USB_PP10 16
SD_CLK
SD_CLK
37
SD_CLK/XD_D1/MS_CLK
USB_PN10 16
C280
SC15P50V2JN-2-GP
Power mode select

+3.3V_PHY
No staff R and C for power saving mode.
U33
GND
8
7
6
5
MODE_SEL
DY
<Core Design>
C311
SCD1U16V2KX-3GP
VCC
DC
DY ORG
R280
10KR2J-3-GP
DY
DY
Wistron Corporation
C317
SC47P50V2JN-3GP

AT93C46DN-SH-B-GP
CS
SK
DI
DO
1
2
3
4
CARD_EECS
CARD_EESK
CARD_EEDO
CARD_EEDI
Title
Reserve for changing USB VID/PID.

Size
Document Number
Custom
RTS5158E

5
Rev
A00
Roberts
Sheet
1
21
of
58
SSID = AUDIO
+3.3V_RUN
Place C915 close to pin9

D
SDO
17 ICH_AZ_CODEC_SYNC
10
SYNC
17 ICH_AZ_CODEC_RST#
11
RESET#
AUD_HP1_OUT_L
AUD_HP1_OUT_R
AUD_HP1_OUT_L 23
AUD_HP1_OUT_R 23
PORTB_L
PORTB_R
VREFOUT_B
21
22
28
AUD_EXT_MIC_L
AUD_EXT_MIC_R
AUD_VREFOUT_B
AUD_EXT_MIC_L 40
AUD_EXT_MIC_R 40
AUD_VREFOUT_B 40
PORTC_L
PORTC_R
VREFOUT_C
23
24
29
AUD_INT_MIC_L
AUD_INT_MIC_R
AUD_VREFOUT_C
C547 1
C549 1
R292 1
PORTD_L
PORTD_R
35
36
AUD_LINE_OUT_L
AUD_LINE_OUT_R
C560
PORTE_L
PORTE_R
VREFOUT_E/GPIO4
14
15
31
PORTF_L
PORTF_R
GPIO3
16
17
30
NC#18
NC#19
NC#20
18
19
20
PCBEEP
12
MONO_OUT
32
CAP2
VREFFILT
33
27
AVSS1
AVSS2
26
42
C532
SC4D7P50V2CN-1GP
AUD_DMIC_CLK
AUD_DMIC_IN0
41 AUD_DMIC_IN0
46
2
4
47
48
DMIC_CLK
VOL_UP/DMIC_0/GPIO1
VOL_DN/DMIC_1/GPIO2
EAPD/GPIO0/SPDIF_OUT0OR1
SPDIF_OUT0
GPIO5
GPIO6
GPIO7/SPDIF_OUT1
7
49
DVSS
GND
2
2
SC1U10V3KX-3GP
SC1U10V3KX-3GP
2 4K7R2J-2-GP
R473
1 39K2R2F-L-GP
AUD_HP1_JD#
R478
1 20KR2F-L-GP
EXT_MIC_JD# 40
C541
23,40
1 SC1KP50V2KX-1GP
INT_MIC_L_R 40
2 SC1U6D3V2KX-GP
AUD_LINE_OUT_L 23
AUD_LINE_OUT_R 23
Port
Port
Port
Port
A--->
B--->
C--->
D--->
HP
Ext Mic
Int Mic
Speaker
AUD_PC_BEEP
Trace width>15 mils
PC BEEP
AUD_PC_BEEP
C531 2
AUD_CAP2
AUD_VREFFLT
1
43
44
45
39
41
37
PORTA_L
PORTA_R
NC#37
1
2
DY
AUD_SENSE_A
AUD_SENSE_B
13
34
92HD71B7A5NLGXB3X8-GP
1 SCD1U10V2KX-4GP SB_SPKR_R
R464
499KR2F-1-GP
1
2
From SB
SB_SPKR 18
SDI_CODEC
SENSE_A
SENSE_B/NC#34
BITCLK
R479
5K1R2F-2-GP
R468
DUMMY-C2
SB_AZ_CODEC_SDIN0_R
R487
20KR2F-L-GP
25
38
1 33R2J-2-GP
17 ICH_SDOUT_CODEC
17 ICH_SDIN_CODEC
ICH_AZ_CODEC_BITCLK_R
1 22R2J-2-GP
+VDDA
AVDD1
AVDD2
DVDD_CORE
DVDD_CORE
NC#40/OTP
DVDD_IO
C561
SC10U6D3V5MX-3GP
R465 2
1
9
40
3
R463 2
17 ICH_AZ_CODEC_BITCLK
U61
C529
SCD1U10V2KX-4GP
+VDDA
C558
SC10U6D3V5MX-3GP
1 R467
2
0R0402-PAD
+3.3V_RUN
C555
SC1U10V3KX-3GP
+VDDA
C550
SCD1U10V2KX-4GP
1
2
C533
SCD1U10V2KX-4GP
C530
SC1U6D3V2KX-GP
1
2
C537
SCD1U10V2KX-4GP
Place C914 close to pin1
Azalia I/F EMI

ICH_SDOUT_CODEC
1
+3.3V_RUN
U59
41 AUD_DMIC_CLK_G
ICH_AZ_CODEC_SDOUT1
EC154
SC22P50V2JN-4GP
VCC
DY
OE#
A
GND
1
2
3
74LVC1G125DC-GP
R477 2
1 22R2J-2-GP
AUD_DMIC_CLK
A
<Core Design>
Wistron Corporation
DY
R466
47R2J-2-GP
DY
Title
C528
SCD1U10V2KX-4GP
AUDIO CODEC 92HD71B7
Size
Document Number
Custom

5
Sheet
1
Rev
A00
Roberts
22
of
58
SSID = AUDIO
+5V_RUN
Signal inverter for speaker shutdown
+5V_SPK_AMP
Close to U24.8
Close to U24.18
+5V_SPK_AMP
+5V_SPK_AMP
1
1
2
Close to Pin9
1 100KR2J-1-GP
6040
9789
2
2
AMP_MUTE#
AUD_HP1_JD
AUD_HP1_EN
97891
24
R489
10MR2J-L-GP
2N7002SPT
+5V_RUN
100KR2J-1-GP
+VDDA
C322
SC1U10V3KX-3GP
1
2
1
2
6040
C565
SC1U10V3KX-3GP
9789
AMP_MUTE#
R286
2
AUD_BIAS
AUD_SET
MAX9789A-GP
AUD_HP1_JD
From EC
1 0R2J-2-GP
2 SC1U10V3KX-3GP
+5V_SPK_AMP
AUD_HP1_JD#
R483 2
22,40 AUD_HP1_JD#
C556
SC1U10V3KX-3GP
AUD_SPK_ENABLE#
AMP_MUTE#_R
AUD_HP1_EN
AMP_REGEN
AMP_C1P C321 1
AMP_C1N
23
25
22
4
10
12
29
24
1
AUD_LINE_OUT_R 22
AUD_LINE_OUT_L 22
2 SCD033U16V3KX-GP
2 SCD033U16V3KX-GP
C551
1AUD_CPVSS
+5V_SPK_AMP
C566
AUD_BIAS
C567
AUD_SET
1 SCD033U16V3KX-GP
6040
2
1 SCD033U16V3KX-GP
6040
2
1 SCD1U10V2KX-4GP
9789
KBC_BEEP 24
10KR2J-3-GP
AUD_HP1_JD#
From EC
3AUD_SPK_ENABLE
1KR2J-1-GP
R484
NB_SPK_EN#
GAIN SETTING
R287
100KR2J-1-GP
2
D17
2
R472
KBC_BEEP_R 1
C535 2
R285
100KR2J-1-GP
2
R293
100KR2J-1-GP
AMP_REGEN
+5V_SPK_AMP
1
+VDDA
SC1U10V3KX-3GP
C548
SC1U6D3V2KX-GP
C552
SC10U6D3V5MX-3GP
1
2
C562
SCD1U10V2KX-4GP
C554
SC1U6D3V2KX-GP
30
17
VDD
HPVDD
9
CPVDD
1
HP_INR
HP_INL
21
5
26
27
SPKR_EN#
MUTE#
HP_EN
REGEN
C1P
C1N
VOUT
BIAS
SET
R469
0R2J-2-GP
R488
2K2R2J-2-GP
C544 1
C543 1
C557
SC10U6D3V5MX-3GP
18
2
GAIN1
GAIN2
AUD_LIN_R
AUD_LIN_L
2
3
PVSS
31
32
CPVSS
AUD_AMP_GAIN1
AUD_AMP_GAIN2
+5V_SPK_AMP
U36
SPKR_INR
SPKR_INL
14
HPR
HPL
C546
SC1U6D3V2KX-GP
R485
100KR2J-1-GP
R486 2
CPGND
15
16
PVDD
AUD_HP1_JACK_R
AUD_HP1_JACK_L
SC10U6D3V5MX-3GP
2K2R2J-2-GP
C564
R490
1
2 AUD_HP1_OUT_R1 1
2 AUD_HP1_OUT_R2
1
2 AUD_HP1_OUT_L1 1
2 AUD_HP1_OUT_L2
6040B
6040B
OUTL+
OUTLOUTROUTR+
13
22 AUD_HP1_OUT_R
22 AUD_HP1_OUT_L
6
7
19
20
11
40 AUD_HP1_JACK_R
40 AUD_HP1_JACK_L
AUD_SPK_L1
AUD_SPK_L2
AUD_SPK_R2
AUD_SPK_R1
GND
GND
AUD_SPK_L1
AUD_SPK_L2
AUD_SPK_R2
AUD_SPK_R1
PGND
PGND
40
40
40
40
PVDD
U62
C553
SC1U6D3V2KX-GP
+5V_SPK_AMP
28
33
1
2
1
2
C545
SCD1U10V2KX-4GP
60ohm 100MHz
3000mA 0.05ohm DC
C538
SC10U6D3V5MX-3GP
BLM21PG600SN-1GP
C563
SC1U10V3KX-3GP
L18
1
U35
4
AUD_SPK_ENABLE#
AMP_MUTE#
BAW56-2-GP
2N7002SPT
+5V_SPK_AMP
R288
100KR2J-1-GP
2
DY
2
R290
100KR2J-1-GP
AUD_AMP_GAIN2
AUD_AMP_GAIN1
R291
100KR2J-1-GP
R289
100KR2J-1-GP
Second
source
TPA6040A
(74.06040.013)
MAX9789A
(74.09789.013)
G80
R486
DY
Main
source
100K
No ASM
A00.08/0922
GAIN1
GAIN2
No ASM
0 Ohm
R469
No ASM
0 Ohm
R286
No ASM
100K
C535
0.033uF
No ASM
C566
0.033uF
No ASM
C565
1uF
No ASM
C567
No ASM
0.1uF
C564
10uF
2.2uF
C557
10uF
2.2uF
GAP-OPEN-PWR
G77
1
2
GAIN
6dB
10dB
15.6dB
21.6dB
R483
GAP-OPEN-PWR
G79
1
2
GAP-OPEN-PWR
G78
1
2
GAP-OPEN-PWR
<Core Design>
Wistron Corporation
Title
AUDIO AMP/SPEAKER
Size
Document Number
Custom

5
Sheet
1
Rev
A00
Roberts
23
of
58
42 EC_SPI_WP#_R
30,31,32 RUNPWROK
42
PWRLED
PM_SLP_S3#
KBC_PWRBTN#
AC_IN#
LID_CLOSE#
BIOS_ID
A00.08/0902
R182
RUNPWROK_R
2
0R0402-PAD
A00.08/0903
45 AD_OFF
18 RSMRST#_KBC
18,31,41 PM_SLP_S4#
A00.08/0903
27 3V_5V_POK
9,18,25 PM_PWROK
45 PSID_DISABLE#
36 HDD_5V_EN
35
BLON_OUT
28 CPUCORE_ON
R158
PM_PWROK_R
2
0R0402-PAD
R159
CPUCORE_ON_R
2
0R0402-PADECSMI#_KBC
A00.08/0903
43,45 USB_PWR_EN#
101
105
106
107
64
95
93
94
119
6
109
120
65
66
16
17
20
21
22
23
24
25
26
27
28
73
74
75
110
GPI94
GPI95
GPI96
GPI97
R150
10KR2J-3-GP
DY
2
R141
10KR2J-3-GP
1
2
R143
10KR2J-3-GP
DY
80
GPIO01/TB2
GPIO03
GPIO06
GPIO07
GPIO23
GPIO24
GPIO30
GPIO31
GPIO32/D_PWM
GPIO33/H_PWM
GPIO40/F_PWM
GPIO42/TCK
GPIO43/TMS
GPIO44/TDI
GPIO45/E_PWM
GPIO46/TRST#
GPIO47
GPIO50/TDO
GPIO51
GPIO52/RDY#
GPIO53
GPIO70
GPIO71
GPIO72
GPO82/TRIS#
0
0
0
0
0
0
1
1
0
1
0
1
GPIO41
GPIO66/G_PWM
81
GPIO77
GPIO76/SHBM
GPIO75
GPIO81
DY
111
113
112
GPIO16
GPIO34
GPIO36
114
14
15
VCORF
44
KA20GATE
KBRCIN#
C KBC_THERMTRIP#
18
ECSWI#_KBC
ECSCI#
BAS16-1-GP
2
ECSCI#_KBC
D12
18
ECSMI#
S5_ENABLE
ECSMI#_KBC
R400
KBC_GPIO76
R420
SRN4K7J-8-GP
RN46
1
2
BIOS_ID
DY
1
1
DY
DY
100KR2J-1-GP
100KR2J-1-GP
100KR2J-1-GP
100KR2J-1-GP
100KR2J-1-GP
10KR2J-3-GP
10KR2J-3-GP
DY
A00.08/0902
KCOL[0..16]
C204
SC1U10V3KX-3GP
KBC_XI
77
32KX1/32KCLKIN
KBC_XO
AMP_MUTE#
79
30
32KX2
GPIO55/CLKOUT
45
PS_ID_EC
18 PM_PWRBTN#
35 LCD_TST_EN
23
KBC_BEEP
42 BATLOW_LED
35 BRIGHTNESS
63
117
31
32
118
62
GPIO14/TB1
GPIO20/TA2
GPIO56/TA1
GPIO15/A_PWM
GPIO21/B_PWM
GPIO13/C_PWM
44
KB_DET#
35 LCD_CBL_DET#
13
12
11
10
71
72
GPIO12/PSDAT3
GPIO25/PSCLK3
GPIO27/PSDAT2
GPIO26/PSCLK2
GPIO35/PSDAT1
GPIO37/PSCLK1
35
44
44
PLT_RST# 9,16,20,21,37,41
42
42
42
42
C228
1
10KR2J-3-GP
2 OF 2
U20B
LCD_TST
TPDATA
TPCLK
KBSOUT0/JENK#
KBSOUT1/TCK
KBSOUT2/TMS
KBSOUT3/TDI
KBSOUT4/JEN0#
KBSOUT5/TDO
KBSOUT6/RDY#
KBSOUT7
KBSOUT8
KBSOUT9
KBSOUT10
KBSOUT11
KBSOUT12/GPIO64
KBSOUT13/GPIO63
KBSOUT14/GPIO62
KBSOUT15/GPIO61/XOR_OUT
GPIO60/KBSOUT16
GPIO57/KBSOUT17
53
52
51
50
49
48
47
43
42
41
40
39
38
37
36
35
34
33
KCOL0
KCOL1
KCOL2
KCOL3
KCOL4
KCOL5
KCOL6
KCOL7
KCOL8
KCOL9
KCOL10
KCOL11
KCOL12
KCOL13
KCOL14
KCOL15
KCOL16
KCOL17
KBSIN0
KBSIN1
KBSIN2
KBSIN3
KBSIN4
KBSIN5
KBSIN6
KBSIN7
54
55
56
57
58
59
60
61
KROW0
KROW1
KROW2
KROW3
KROW4
KROW5
KROW6
KROW7
VCC_POR#
85
ECRST#
KBC
CPUCORE_ON
C190
SC470P50V2KX-3GP
DY
10KR2J-3-GP
1
2
R509
10KR2J-3-GP
BIOS_ID: Pull High for Discrete
KBC internal Pull Low for UMA
EC_SPI_DI
EC_SPI_DO
EC_SPI_CS#
EC_SPI_CLK
EC_SPI_DI
EC_SPI_DO
EC_SPI_CS#
EC_SPI_CLK
R192 1
2 0R2J-2-GP
86
87
90
EC_SPI_CLK_C 92
F_SDI
F_SDO
F_CS0#
F_SCK
44
TP122
KROW[0..7]
PS/2
FIU
KBC_XI
44
SC15P50V2JN-2-GP
WPCE773LA0DG-GP
ECRST#
C240
1
SC15P50V2JN-2-GP
R203
X3_1 1
33KR3-GP
KBC_XO
A00.08/0903
R170
0R0402-PAD
Wistron Corporation
1
E
10KR2J-3-GP
R173
2
2
1
1
ECRST#_C B
Q10
CH3906PT-GP
25,34 PURE_HW_SHUTDOWN#
DY C453
SC4D7P50V2CN-1GP
<Core Design>
+3.3V_RTC_LDO
R199
20MR3-GP
X1
X-32D768KHZ-38GPU
R410
0R2J-2-GP
KBC_PWRBTN#
R425
LID_CLOSE#
R422
LCD_CBL_DET#
R409
KB_DET#
R406
CAMERA_DET#
R401
KBC_THERMTRIP#
R404
KCOL0
3
1
2
1
2
E51_TxD
R149
4K7R2J-2-GP
1
DY
4
3
R407
PM_LAN_ENABLE 20
TSATN#_KBC 9
S5_ENABLE 34
23
PCLK_KBC
PCLK_KBC_RC
DY
R148
10KR2J-3-GP
BAT_SDA
BAT_SCL
1
2
KBC_VCORF
WPCE773LA0DG-GP
1 R153
2
0R0402-PAD
DY
4
3
SRN4K7J-8-GP
BAS16-1-GP
0R2J-2-GP
KBC CLK EMI

2
+3.3V_RUN
1
2
DY
+3.3V_RTC_LDO
KBC_SCL1
KBC_SDA1
ECSWI#
37
E51_TxD 37
E51_RxD 37
TSATN#_KBC
10KR2J-3-GP
D13
18
BLUETOOTH_EN 41,47
E51_TxD
E51_RxD
RN47
SCD1U16V2KX-3GP
BAS16-1-GP
2
WIFI_RF_EN
4
3
Q9
CH3904PT-GP
BAT_SDA 26,45
BAT_SCL 26,45
KBC_GPIO76
DY
SRN10KJ-5-GP
KBC_SDA1
KBC_SCL1
DY
C199
2
1
5,9,17,34 H_THRMTRIP#
1
10KR2J-3-GP
+3.3V_RUN
0R2J-2-GP
2
0R2J-2-GP
R162
2K2R2J-2-GP
GMCH_BL_ON 13
ECSWI#_KBC
CAP_SCL 42
E51_RxD
R156
2
RN21
17,37
INT_SERIRQ 18
PM_CLKRUN# 18
KBRCIN# 17
KA20GATE 17
R413
0R2J-2-GP
RUNPWROK
DY
R147
LPC_LAD[0..3]
ECSCI#_KBC
84
83
82
91
GPO83/SOUT_CR/BADDR1
GPIO87/SIN_CR
GPO84/BADDR0
SER/IR
PLT_RST1#_1
A00.08/0902
THERM_SCL 25
+1.05V_VCCP
PCLK_KBC 4
LPC_LFRAME# 17,37
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
2
R157
68
67
69
70
SPI
GPIO
GND
GND
GND
GND
GND
GND
VER0
1
R418
PLT_RST1#_1
X00
X01
X02
-1
VER1
KBC_SDA1
D11
MB VERSION ID
VER2
1
R417
124
7
2
3
126
127
128
1
125
8
122
121
29
9
123
GPIO74/SDA2
GPIO73/SCL2
GPIO22/SDA1
GPIO17/SCL1
SMB
SP
BAT_IN# 45
102
VDD
D/A
116
89
78
45
18
5
R151
10KR2J-3-GP
1
2
R138
10KR2J-3-GP
R146
10KR2J-3-GP
1
2
2
PCB_VER2
PCB_VER1
PCB_VER0
AVCC
LPC
MB VERSION ID
DY
U22
4
2N7002SPT
GPIO10/LPCPD#
LRESET#
LCLK
LFRAME#
LAD0
LAD1
LAD2
LAD3
SERIRQ
GPIO11/CLKRUN#
KBRST#
GA20
ECSCI#/GPIO54
GPIO65/SMI#
GPIO67/PWUREQ#
A/D
GPI90/AD0
GPI91/AD1
GPI92/AD2
GPI93/AD3
GPIO05
GPIO04
+3.3V_RUN
0R2J-2-GP
97
98
99
100
108
96
VREF
103
18,25,30,31,32,34,41
42
26
41
18,28 VGATE_PWRGD
DY
2
0R2J-2-GP
41 CAMERA_DET#
DY
PCB_VER0
PCB_VER1
PCB_VER2
CAP_SDA
KBC_SCL1
1 OF 2
KBC_THERMTRIP#
42
C196
DY SC10U6D3V5MX-3GP
AGND
AD_IA
CAPA_INT#
42
115
88
76
46
19
U20A
104
26
SSID = KBC
1
R415
R416
25 THERM_SDA
VCC
VCC
VCC
VCC
VCC
C460
SCD1U10V2KX-4GP
C459
SC10U6D3V5MX-3GP
C458
SCD1U10V2KX-4GP
C194
SCD1U10V2KX-4GP
+3.3V_RUN
VBAT
1
2
C457
SCD1U10V2KX-4GP
1
2
C451
SCD1U10V2KX-4GP
C456
SCD1U10V2KX-4GP
1
2
C465
SCD1U10V2KX-4GP
C466
SC10U6D3V5MX-3GP
DY
2 BLM18AG601SN-3GP
L17
+3.3V_RUN
4
CAP close to VCC-GND pin pair
EC132
SCD1U16V2KX-3GP
+3.3V_RTC_LDO
C214
SC1U10V3KX-3GP

Title
KBC Winbond WPC773L
Size
Document Number
Custom
Sheet
Rev
A00
Roberts
24
of
58
+5V_RUN
R66
R63
10KR2J-3-GP
C389
SCD1U16V2KX-3GP
DY
DY
R348
10KR2J-3-GP
0R2J-2-GP
2
1
2
C386
SC4D7U6D3V5KX-3GP
+5V_RUN
+3.3V_RUN
SSID = Thermal
D6
EMC2102_FAN_TACH
EMC2102_FAN_TACH_1
EMC2102_FAN_TACH_1 36
D
RB551V30-GP
EMC2102_FAN_DRIVE
EMC2102_FAN_DRIVE
+3.3V_RTC_LDO
36
RN3
R346
3
4
DY
49D9R2F-GP
2
1
+3.3V_RUN
SRN4K7J-8-GP
THERM_SCL 24
THERM_SDA 24
+3.3V_RUN
22
23
SMCLK
SMDATA
25
26
24
VDD_5Vb
FANb
FANa
VDD_5Va
DP1
ALERT#
19
ALERT#
DN2
CLK_IN
18
CLK_32K
EMC2102_DP2
DP2
CLK_SEL
17
EMC2102_CLK_SEL
EMC2102_DN3
DN3
RESET#
16
EM2102_RESET#
EMC2102_DP3
DP3
NC#15
15
R88
DY
1 0R2J-2-GP
THERM_SCI# 18
GND = Internal Oscillator Selected

+3.3V = External 32.768kHz Clock Selected
1 10KR2J-3-GP
POWER_OK#
THERMTRIP#
14
13
SYS_SHDN#
12
EMC2102_SHDN
1 10KR2J-3-GP
1 10KR2J-3-GP
2
2
+3.3V_RUN
+3.3V_RUN
+3.3V_RTC_LDO
+3.3V_RUN
2
DY
R362
10KR2J-3-GP
EMC2102_FAN_mode
A00.08/0922
EMC2102_FAN_TACH_1
EMC2102_FAN_DRIVE
C78
SCD1U16V2KX-3GP
R82
10KR2F-2-GP
10KR2J-3-GP
PURE_HW_SHUTDOWN#
GND = Fan is OFF

OPEN = Fan is at 60% full-scale
+3.3V = Fan is at 75% full-scale
24,34
1
1
TRIP_SET Pin Voltage

V_DEGREE=(((Degree-75)/21)
V_DEGREE
R78
2K37R2F-GP
2
C70
SCD1U16V2KX-3GP
TP223
TP72
Q17
2N7002-7F-GP
R71
10KR2J-3-GP
+3.3V_RUN
R347
10KR2J-3-GP
R68
3.HW T8 sensor
10KR2J-3-GP
1
C63
SC470P50V3JN-2GP
DY 1
R87
EMC2102-DZK-GP
R85
R84
R67
2
C63 must be
near EMC2102
TRIP_SET
C
E
C37
SC470P50V3JN-2GP
FAN_MODE
GND = Channel 1
OPEN = Channel 3
+3.3V = Disabled
Layout notice :
Both DN3 and DP3 routing 10 mil
trace width and 10 mil spacing.
C37 must be near Q1
11
C61
SC470P50V3JN-2GP
EMC2102
C61 must be
near EMC2102
DY
R89
8K2R2J-3-GP
10
1
E
C388
SC470P50V3JN-2GP
2.System Sensor, Put between CPU and NB.
20
C388 must be near Q18
Q1
MMBT3904-3-GP
21
GND
EMC2102_DN2
SHDN_SEL
DY
NC#21
DN1
NC#8
Layout notice :
Both DN2 and DP2 routing 10 mil
trace width and 10 mil spacing.
28
VDD_3V
H_THERMDA
Q18
MMBT3904-3-GP
TACH
+3.3V_RUN
C50
SC470P50V3JN-2GP
Layout notice :
Both H_THERMDA and THERMDC routing
10 mil trace width and 10 mil spacing.
H_THERMDC
1
GND
U8
C60
SCD1U16V2KX-3GP
1.For CPU Sensor
29
EMC2102_VDD_3D3
49D9R2F-GP
27
R340
2
T8 shutdown is set 88 deg-C.
32K suspend clock output

+3.3V_ALW
U10
R219
S
Q13
2N7002-7F-GP
CLK_32K
10R2J-2-GP
18,24,30,31,32,34,41
DY
2
CLK_32K_R
PM_SLP_S3#
ICH_SUSCLK
18
EM2102_RESET#
C249
SC4D7P50V2CN-1GP
C82
VCC
DY
DY 1
SCD1U16V2KX-3GP
PM_PWROK 9,18,24
GND
<Core Design>
74LVC1G08GW-1-GP
RUN_POWER_ON
Wistron Corporation
Title
Thermal/Fan Controllor EMC2102 Rev
Size
Document Number
Custom

5
A00
Roberts
Sheet
1
25
of
58
SSID = Charger
1
MAX8731_LDO
+3.3V_RTC_LDO
1
Id=-8A
Qg=17~24nC
Rdson=15~20mohm
R72
100KR2J-1-GP
Layout Trace 300mil

1
100KR2J-1-GP
DLO
20
PGND
19
CSIP
18
MAX8731_CSIP
CSIN
17
MAX8731_CSIN
FBSB
16
FBSA
15
R306
2
IND-5D8UH-GP
D01R2512F-4-GP
DY
R335
MAX8731AETI-GP
BATT_SENSE
BAT_SENSE
100R2F-L1-GP-U
GND
CCV
CCI
CCS
REF
DAC
GND
29
1
2
C59
SCD1U16V2KX-3GP
C51
SC1U10V3KX-3GP
1
2
C55
SCD01U50V2KX-1GP
1
2
C57
SCD01U50V2KX-1GP
1MAX8731_CCV1
C58
SCD01U50V2KX-1GP
1
2
C62
SCD1U16V2KX-3GP
1
2
6
2 10KR2F-2-GP MAX8731_CCV
MAX8731_CCI
5
MAX8731_CCS
4
MAX8731_REF
3
MAX8731_DAC 7
12
G50
GAP-CLOSE-PWR-3-GP
A00.08/0909
R61
2
1
INP
G51
GAP-CLOSE-PWR-3-GP
U44
SI4800BDY-T1
4
3
2
1
AD_IA
R65
10KR2F-2-GP
Layout Trace 300mil
D
D
D
D
BATSEL
CHG_AGND
G
S
S
S
4
3
2
1
MAX8731_LX1
CHG_PWR
L9
G
S
S
S
14
24
EC79
SCD1U50V3KX-GP
2 SCD1U25V3KX-GP
SDA
R44
C34
1R3F-GP
MAX8731_LX 1
2
1
2
C42
SC220P50V2KX-3GP
MAX8731_DLO
C323
SC10U25V6KX-1GP
23
LX
BAT_SDA
24,45 BAT_SDA
+PBATT
MAX8731_DHI
24
DHI
C329
SC10U25V0KX-3GP
SCL
BAT_SCL
24,45 BAT_SCL
SC1U10V3KX-3GP
10
CHG_AGND
CHG_AGND
DY
C331
SC10U25V0KX-3GP
ACOK
C48
1
U45
SI4800BDY-T1
5
6
7
8
13
R45
D5
0R3-0-U-GP
MAX8731_BST 1
2MAX8731_BST1 K
A
MAX8731_LDO
BAS516-1-GP
CHG_AGND
C40
SCD1U25V3KX-GP
25
21
MAX8731_VCC
BST
LDO
VDD
C371
SC10U25V0KX-3GP
27
26
C38
SC1U10V3KX-3GP
5
6
7
8
CSSN
VCC
R49
33R2J-2-GP
D
D
D
D
CSSP
28
CHG_AGND
ACIN
C64
SCD1U25V3KX-GP
ACAV_IN
C41
SCD1U25V3KX-GP
ASNS
DCIN
MAX8731_ACIN
22
11
1
2
2
B
C46
SCD01U50V2KX-1GP
2
1
R48
49K9R2F-L-GP
MAX8731_DCIN
+3.3V_RTC_LDO
R295
470KR2J-2-GP
CHG_AGNDCHG_AGND
U7
2
MAX8731_CSSN
MAX8731_CSSP
C47
SCD1U25V3KX-GP
A00.08/0903
C39
SC1U25V5KX-1GP
8
7
6
5
Q3
2N7002-7F-GP
ACAV_IN
D
D
D
D
U37
S
S
S
G
AO4407A-GP
G56
GAP-CLOSE-PWR-3-GP
R62
DCIN_GATE2
49K9R2F-L-GP
G
R52
365KR3F-GP
G57
GAP-CLOSE-PWR-3-GP
2
D
R64
DCIN_GATE1
Q2
2N7002-7F-GP
1
2
3
4
+DC_IN_SS
DC_IN_D
0R0402-PAD
+PBATT
D01R2512F-4-GP
R59
10KR2J-3-GP
2N7002-7F-GP
+PWR_SRC
R338
AO4407A-GP
ACAV_IN
R46
Layout Trace 300mil
+SDC_IN
1
2
3
4
S
S
S
G
C369
SC10U25V0KX-3GP
U47
D
D
D
D
2
D
8
7
6
5
+DC_IN_SS
Adaptor In Soft-Start Circuit
+DC_IN_SS
Layout Trace 250mil
Q4
AC_IN#
C67
SC1U10V3KX-3GP
24
EC80
SCD1U50V3KX-GP
R341
15K4R2F-GP
EC77
SCD1U50V3KX-GP
ACAV_IN
EC76
SCD1U50V3KX-GP
+PBATT
R339
10KR2F-2-GP
C372
SCD01U50V2KX-1GP
BATT_SENSE 45
<Core Design>
1
G11
GAP-CLOSE-PWR
Wistron Corporation
CHG_AGND
Title
CHARGER MAX8731
Size
Document Number
Custom

5
Rev
A00
Roberts
Sheet
1
26
of
58
+PWR_SRC
SSID = PWR.Plane.Regulator_3p3v5v
PWR_SRC_17020
G17
GAP-CLOSE-PWR
G23
2
1
+PWR_SRC
GAP-CLOSE-PWR
G63
2
1
PWR_SRC_17020
No Install for ISL6236

Install 10 ohm for MAX8778
G19
GAP-CLOSE-PWR
G70
2
1
GAP-CLOSE-PWR
G72
1
2
4
GAP-CLOSE-PWR
G68
2
1
GAP-CLOSE-PWR
G33
1
2
+5V_ALW2
1
1
GAP-CLOSE-PWR
G21
1
2
GAP-CLOSE-PWR
G66
2
1
10R3F-GP
GAP-CLOSE-PWR
G64
2
1
C177
SC4D7U6D3V5KX-3GP
0.1uF for ISL6236,

Install with 1uF for
Max8778
GAP-CLOSE-PWR
G36
1
2
+5V_VCC1
R393
PWR_SRC_17020
GAP-CLOSE-PWR
R397
0R5J-5-GP
+2.0V_REF_3V5VREG
+5V_VCC1
1
2
1
2
C86
SCD1U50V3KX-GP
1
2
C402
SC2200P50V2KX-2GP
3V_ALW +/- 5%
Design Current: 5.4A
Peak current 7.8A
8.58<OCP<10.92A
C401
SC10U25V6KX-1GP
5
6
7
8
DY
8
7
6
5
4
3
2
1
4
3
2
1
4
3
2
1
C149
SCD1U25V3KX-GP
17020_BOOT2 1
8778_LGATE2
2 8778_BOOT2_1
R118
0R3-0-U-GP
DY
1
2
TC2
ST220U6D3VDM-15GP
1
2
C397
SCD1U10V2KX-4GP
1
2
17020_PHASE2
G18
GAP-CLOSE-PWR-3-GP
DY
5
6
7
8
C139
SCD1U25V3KX-GP
MAX8778_3/5V_AGND
PR19 0R2J-2-GP
MAX8778_3/5V_AGND
R86
2D2R5F-2-GP
18778_PHASE2_Sn
DY
MAX8778_3/5V_AGND
A00.08/0903
R106 1
2 0R0402-PAD
1
+5V_VCC1
+3.3V_ALW
G30
GAP-CLOSE-PWR
G32
1
2
GAP-CLOSE-PWR
G31
1
2
GAP-CLOSE-PWR
G27
1
2
GAP-CLOSE-PWR
G26
1
2
C79
SC330P50V2KX-3GP
GAP-CLOSE-PWR
G29
1
2
GAP-CLOSE-PWR
G25
1
2
GAP-CLOSE-PWR
G28
1
2
MAX8778_3/5V_AGND
C172
SC1U25V0KX-GP
237KR2F-GP
+3.3V_ALWP
+3.3V_ALWP
1
2
IND-3D3UH-57GP
G42
GAP-CLOSE-PWR
+5V_ALW2
8778_SECFB
217020_BOOT1
0R3-0-U-GP 17020_LGATE1
17020_REFIN2
17020_ILIM2
17020_OUT2
17020_SKIP#
3V_5V_POK
3V_EN
17020_UGATE2
BST1
DL1
VDD
SECFB
AGND
PGND
DL2
BST2
32
31
30
29
28
27
26
25
17
18
19
20
21
22
23
24
1
2
U17
AO4712-GP
LDOREFIN
LDO
IN
RTC
ONLDO
VCC
TON
REF
9
10
11
12
13
14
15
16
REFIN2
BYP
ILIM2
MAX17020ETJ-GP
OUT1
OUT2
FB1
SKIP#
ILIM1
PGOOD2
PGOOD1
ON2
ON1
DH2
DH1
LX2
LX1
NEC 220uF
6D3V, V Size
ESR=25mohm
L13
CLOSE TO PIN 30
R108
R137
0R0402-PAD
Vout1 = 0.7(Rtop/Rbottom + 1)
C85
SC10U25V6KX-1GP
2
1
2
3V/5V_TON 2
R107
0R2J-2-GP
C179
SCD1U25V3KX-GP
8
7
6
5
D
D
D
D
S
S
S
G
MAX8778_3/5V_AGND
GND
R135
8778_BOOT1_1 1
1
2
3
4
R129
2D2R5F-2-GP
15V_PHASE1_Sn
2
C176
SC330P50V2KX-3GP
U18
U11
AO4712-GP
8
7
6
5
17020_FB
1 R136
2 17020_ILIM1
3V_5V_POK
270KR2F-GP
5V_EN
MAX8778_3/5V_AGND
17020_PHASE1
GAP-CLOSE-PWR
SC1U25V0KX-GP
33
SCD1U25V3KX-GP
DY
R132
0R2J-2-GP
U12
IRF8707PBF-GP
DY
D
D
D
D
S
S
S
G
1
2
3
4
C422
SC10U25V6KX-1GP
1
2
C148
SC10U25V6KX-1GP
1
2
C147
SCD1U50V3KX-GP
1
2
1
2
8778_FB1_1
1
C424
2
C183
1
DY
GAP-CLOSE-PWR
G46
1
2
DY
MAX8778_3/5V_AGND
1
2
IND-3D3UH-57GP
G41
GAP-CLOSE-PWR-3-GP
2 C146
S
S
S
G
GAP-CLOSE-PWR
G47
1
2
DY
SCD1U10V2KX-4GP
1
2
TC20
ST150U6D3VBM-1-GP
GAP-CLOSE-PWR
G48
1
2
ST220U6D3VDM-15GP
GAP-CLOSE-PWR
G43
1
2
TC7
2
DY0R2J-2-GP
A00.08/0903
MAX8778_3/5V_AGND
L15
+5V_ALWP
U15
LDO_EN
0R0402-PAD
D
D
D
D
GAP-CLOSE-PWR
G45
1
2
1 R391
R114
PWR_SRC_17020
A00.08/0902
S
S
S
G
+5V_ALWP
G44
MAX8778_3/5V_AGND
R384
0R0402-PAD
DY
D
D
D
D
+5V_ALW
NEC 220uF
6D3V, V Size
ESR=25mohm
DY
C169
SCD1U50V3KX-GP
CLOSE TO PIN 10 +3.3V_RTC
IRF8707PBF-GP
5V_ALW +/- 5%
Design Current: 6A
Peak current 8.5A
9.35<OCP<12A
C421
SC1KP50V2KX-1GP
PWR_SRC_17020
R387
0R2J-2-GP
R113
0R2J-2-GP
+5V_VCC1
C165
1
2
SC1U25V0KX-GP
3V/5V_VIN
C155
SC1U25V0KX-GP
+3.3V_RTC
R399
0R5J-5-GP
GAP-CLOSE-PWR
GAP-CLOSE-PWR
Vout2 = Vref(Rrefin_top/Rrefin_bottom + 1)
A00.08/0903
+5V_ALW2
MAX8778_3/5V_AGND
R127
2 0R0402-PAD
I/P cap: 10U 25V K1206 X5R/ 78.10622.52L

Inductor: 3.3UH PCMC063T3R3MN CYNTEC DCR 28~30mohm Isat =13.5Arms 68.3R310.20A
O/P cap: 220U 6.3V PSLV0J227M(25) 25mOhm 2.236Arms NEC_TOKIN/77.C2271.00L
O/P cap: 150U 6.3V PSLB20J157M(45) 45mOhm 1.374rms NEC_TOKIN/77.C1571.09L
H/S: IRF8707 SO-8/ 14.2mohm/17.5mOhm@4.5Vgs/ 84.08707.037
L/S: FDS4712 SO-8/ 15mohm/18mOhm@4.5Vgs/ 84.04712.037
A00.08/0903
4/14 modify.
Add RC circuit for power sequence.
A00.08/0903
3V_EN
2 0R0402-PAD
5V_EN
+3.3V_RTC_LDO
DYDY
C180
SCD1U10V2KX-4GP
R109
100KR2J-1-GP
3V_5V_POK
C141
SCD1U10V2KX-4GP
A00.08/0903
2 0R0402-PAD
R134 1
R110 1
3V_5V_EN
34
3V_5V_POK 24
+3.3V_RTC_LDO
+5V_ALW2
ultrasonic
mode
forced-PWM
operation
400kHz
Open
(REF)
400kHz
High
(VCC)
200kHz
CH2 Freq
500kHz
300kHz
300kHz
LDOREFIN
Operating
Mode
GND
GND
VCC
1
2
3
VIN
GND
EN
VOUT
NC#4
4
1
pulse-skipping
mode
High
(VCC or 3.3V)
CH1 Freq
TONSEL
Open/REF (2V)
G9091-330T11U-GP
Operating
Mode
GND
SKIPSEL
C184
SC1U10V3KX-3GP
U19
SC1U10V3KX-3GP
C171
I/P cap: 10U 25V K1206 X5R/ 78.10622.52L

Inductor: 3.3UH PCMC063T3R3MN CYNTEC DCR 28~30mohm Isat =13.5Arms 68.3R310.20A
O/P cap: 220U 6.3V PSLV0J227M(25) 25mOhm 2.236Arms NEC_TOKIN/77.C2271.00L
O/P cap: 150U 6.3V PSLB20J157M(45) 45mOhm 1.374rms NEC_TOKIN/77.C1571.09L
H/S: IRF8707 SO-8/ 14.2mohm/17.5mOhm@4.5Vgs/ 84.08707.037
L/S: FDS4712 SO-8/ 15mohm/18mOhm@4.5Vgs/ 84.04712.037
VLDOREFIN
= 0.5V
<Core Design>
4.90/5.0/5.10
3.23/3.3/3.37 0.96/1.0/1.04
Wistron Corporation
FB1
GND
VCC
Operating
4.925/5.00/5.075 1.482/1.50/1.518
Mode
REFIN2
5V

RTC
(3.3V)
Title
Operating
3.255/3.30/3.345 1.038/1.050 /1.062
Mode
DC to DC 3.3V/5V
Size
A2
Date:
Document Number
Rev
A00
Roberts
Thursday, October 02, 2008
E
Sheet
27
of
58
9,18 DPRSLPVR
CPUCORE_ON
R297
6,9,17 H_DPRSTP#
CPU_VID1
CPU_VID0
0R0402-PAD
0R0402-PAD
2
CPU_VID2
0R0402-PAD
CPU_VID3
0R0402-PAD
CPU_VID6
CPU_VID4
0R0402-PAD
0R0402-PAD
0R0402-PAD
2
0R0402-PAD
37
VID0
38
VID1
39
VID2
VID3
40
41
VID4
42
VID5
6266A_PHASE1 29
C
6266A_UGATE1 29
6266A_PHASE1
6266A_ LGATE1
C345
1
2
+5V_RUN
SC2D2U10V3KX-1GP
6266A_LGATE2
6266A_ LGATE1 29
6266A_LGATE2 29
6266A_PHASE2
6266A_UGATE2
R319
6266A_BOOT2 1
C351
1
2
6266A_UGATE2 29
6266A_PHASE2 29
SCD22U25V3KX-GP
ISEN1
1R3F-GP
6266A_PHASE2
24
ISEN2
23
6266A_PHASE1
6266A_ISEN1 29
C18
SCD22U10V2KX-1GP
6266A_VO
6266A_VO
29
C28
SC1U10V3KX-3GP
6266A_VO
1 2
R300
NTC-10K-9-GP
2
10R3F-GP
R332
2K61R2F-1-GP
R328
11KR2F-L-GP
2
R41
1
6266A_VSUM
C360
SCD047U10V2KX-2GP
2
1
1
10R3F-GP
29 6266A_VSUM
+5V_RUN
2
R331
1 SCD01U50V2KX-1GP
R327 2
1
SCD22U10V2KX-1GP
C19
SCD22U10V2KX-1GP
6266A_ISEN2 29
Place close to 1st
Choke
2
1
0R2J-2-GP
A
C362
SCD01U50V2KX-1GP
R324
1
VSS_SENSE
C20 2
C359
SC330P50V2KX-3GP
R330
1
C27
0R2J-2-GP
C364
1
2
R329
VCC_SENSE
C339
1
R323
2
1
C361
SC330P50V2KX-3GP
SC180P50V2JN-1GP
2
1KR2J-1-GP
DY
SCD22U25V3KX-GP 6266A_UGATE1
1R3F-GP
PWR_SRC_CPU
2
1
PR12
6266A_ISEN1
6266A_ISEN2
GND
VDD
22
21
20
19
18
VDIFF
13
SC2200P50V2KX-2GP
VIN
25
VSUM
NC#25
R322
1KR2F-3-GP
6266A_SOFT
FB2
VO
12
1KR2F-3-GP
2
45
6266A_FB2
R321
1
44
BOOT2
SC270P50V2KX-1GP
VR_ON
FB
26
2
2
DPRSLPVR
27
6266A_VDD
0R0402-PAD
28
UGATE2
C356
100R2F-L1-GP-U
46
6266A_CLK_EN#
PHASE2
COMP
11
R320
31
VW
6266A_VIN
97K6R2F-GP
C348
1
2
32
PVCC
6266A_FB
8K25R2F-1-GP
SC100P50V2JN-3GP
R318
1
2
33
30
1 1KR2F-3-GP
6266A_VO
6266A_VSUM
C349
1
2
PGND1
LGATE1
29
74.06266.073
6266A_VDIFF
PHASE1
34
PGND2
ISL6266AHRZ-GP
OCSET
DFB
R317
UGATE1
35
6266A_COMP 10
36
LGATE2
SOFT
DROOP
C350 1
BOOT1
NTC
16266A_DROOP 16
3K92R2F-GP
6266A_DFB
17
DY
6266A_VO
DY
VR_TT#
RTN
C343 1
Place close to
1st phase choke
6
2 NTC-470K-1-GP 6266A_NTC
C346
2 SCD01U50V2KX-1GP
1
26266A_SOFT 7
SCD015U50V3KX-GP
6266A_OCSET 8
1
2
R38
12K1R2F-L1-GP
6266A_VW
9
2 SC1KP50V2KX-1GP
R299 1
RBIAS
15
2 4K02R2F-GP
R314
PMON
6266A_RTN
DY
A00.08/0903
PSI#
VSEN
SCD1U16V2KX-3GP
R35 2 6266A_PSI#
2
0R0402-PAD
2 6266A_PMON 3
4K99R2F-L-GP
2 6266A_RBIAS 4
147KR2F-GP
5
14
1
R315
1
R316
C341
1
2
5 CPU_PROCHOT#
R37
PSI#
PGOOD
6266A_VSEN
DY
R36
68R2F-GP
A00.08/0903
24
1
R29
6266A_DPRSTP#
1
R307
6266A_DPRSLPVR
1
R169
6266A_VRON
1
R308
6266A_D6
1
R309
6266A_D5
1
R303
6266A_D4
1
R304
6266A_D3
1
R298
6266A_D2
1
R301
6266A_D1
1
R310
6266A_D0
1
R313
6266A_3V3
47
2
1
18,24 VGATE_PWRGD
CLK_EN#
49
U40
GND
R312
1K91R2F-1-GP
+1.05V_VCCP
48
+3.3V_RUN
3V3
C337
SCD1U10V2KX-4GP
A00.08/0903
DPRSTP#
R305
10R3F-GP
0R0402-PAD
499R2F-2-GP
+3.3V_RUN
43
TP22
CPU_VID5
CPU_VID[6..0]
CLK_EN#
2 10KR2J-3-GP
2 10KR2J-3-GP
DY
VID6
PR11 1
+3.3V_RUN
SSID = CPU.Regulator
C358
SCD22U10V2KX-1GP
<Core Design>
0R0402-PAD
Wistron Corporation
6266AGND
Title
CPU VCORE POWER(1/2)
Size
Document Number
Custom

5
Sheet
1
Rev
A00
Roberts
28
of
58
SSID = CPU.Regulator
PWR_SRC_CPU
+PWR_SRC
+PWR_SRC
PWR_SRC_CPU
4
3
2
1
DY
PTC3
SE100U25VM-14GP
DY
2
C21
SCD1U25V3KX-GP
C335
SCD1U25V3KX-GP
1
2
TC10
SE100U25VM-14GP
CPU noise
+VCC_CORE
L8
1
2
IND-D36UH-9-GP
6266A_PHASE1
5
6
7
8
1
2
1
2
G52
GAP-CLOSE-PWR-3-GP
4
3
2
1
G53
GAP-CLOSE-PWR-3-GP
5
6
7
8
4
3
2
1
TC16
SE330U2VDM-L-GP
6266A_ LGATE1
GAP-CLOSE-PWR
G6
1
2
TC1
SE330U2VDM-L-GP
S
S
S
G
28 6266A_ LGATE1
DY
U2
AOL1412-GP
S
S
S
G
GAP-CLOSE-PWR
G7
1
2
TC14
D
D
D
D
D
D
D
D
U38
AOL1412-GP
GAP-CLOSE-PWR
G8
1
2
SE330U2VDM-L-GP
GAP-CLOSE-PWR
G9
1
2
28 6266A_PHASE1
GAP-CLOSE-PWR
G3
1
2
6266A_UGATE1
28 6266A_UGATE1
GAP-CLOSE-PWR
G4
1
2
68.R3610.20C
C4
SCD1U25V3KX-GP
1
2
C2
SC10U25V6KX-1GP
1
2
C354
SC10U25V6KX-1GP
1
2
C333
SC10U25V6KX-1GP
S
S
S
G
S
S
S
G
GAP-CLOSE-PWR
G1
1
2
D
D
D
D
D
D
D
D
U39
AOL1426-GP
GAP-CLOSE-PWR
G2
1
2
U3
AOL1426-GP
5
6
7
8
5
6
7
8
GAP-CLOSE-PWR
G5
1
2
4
3
2
1
1
D
C1
SC10U25V6KX-1GP
G10
GAP-CLOSE-PWR
28 6266A_VSUM
28 6266A_ISEN1
28 6266A_VO
28 6266A_ISEN2
6266A_VSUM
R42
2 3K65R2F-1-GP
6266A_ISEN1
R39
2 10KR2F-2-GP
6266A_VO
R43
2 1R2F-GP
6266A_ISEN2
R40
2 10KR2F-2-GP
C353
SCD1U25V3KX-GP
C334
SCD1U25V3KX-GP
1
2
C23
SC10U25V6KX-1GP
1
2
S
S
S
G
4
3
2
1
4
3
2
1
C355
SC10U25V6KX-1GP
1
U5
AOL1426-GP
S
S
S
G
5
6
7
8
5
6
7
8
D
D
D
D
D
D
D
D
U42
AOL1426-GP
C22
SC10U25V6KX-1GP
PWR_SRC_CPU
+VCC_CORE
I/P cap: 10U 25V K1206 X5R/ 78.10622.52L

Inductor: 0.36UH PCMC104T-R36MN1R05J CYNTEC DCR 1.05(+5%~-5%)mohm
Isat =60Arms 68.R3610.20C
O/P cap: 330U 2V EEFSX0D331ER 9mOhm 3.0Arms Panasonic/79.33719.L01
H/S: AOL1426 PowerPAK/ 10.2mohm/12.5mOhm@4.5Vgs/84.01426.037
L/S: AOL1412 PowerPAK/ 3.8mohm/4.65mOhm@4.5Vgs/ 84.01412.037
1
2
1
2
TC13
SE330U2VDM-L-GP
G55
GAP-CLOSE-PWR-3-GP
4
3
2
1
4
3
2
1
S
S
S
G
6266A_LGATE2
G54
GAP-CLOSE-PWR-3-GP
U43
AOL1412-GP
S
S
S
G
28 6266A_LGATE2
68.R3610.20C
D
D
D
D
D
D
D
D
U6
AOL1412-GP
TC15
SE330U2VDM-L-GP
L10
1
2
IND-D36UH-9-GP
6266A_PHASE2
5
6
7
8
28 6266A_PHASE2
6266A_UGATE2
5
6
7
8
28 6266A_UGATE2
6266A_VSUM
R333 1
2 3K65R2F-1-GP
6266A_ISEN2
R325 1
2 10KR2F-2-GP
6266A_VO
R334 1
2 1R2F-GP
Wistron Corporation
6266A_ISEN1
R326 1
2 10KR2F-2-GP

<Core Design>
Title
CPU VCORE POWER(2/2)
Size
Document Number
Custom

5
Sheet
1
Rev
A00
Roberts
29
of
58
+1.05V_RUNP
SSID = PWR.Plane.Regulator_1p05v
+1.05V_PWR_SRC
GAP-CLOSE-PWR
G58
1
2
GAP-CLOSE-PWR
GAP-CLOSE-PWR
H/S: IRF8707 SO-8/

14.2mohm/17.5mOhm@4.5Vgs
84.08707.037
+5V_ALW
1
1
2
4
3
2
1
U50
IRF8707PBF-GP
2
1
2
1
SCD1U25V3KX-GP
5
6
7
8
5
6
7
8
C398
1
2
+1.05V_LL1
0R3-0-U-GP
S
S
S
G
S
S
S
G
C396
SC1U10V3KX-3GP
D
D
D
D
R365
+5V_ALW
D
D
D
D
U13
IRF8707PBF-GP
4
3
2
1
R364
300R3-GP
GAP-CLOSE-PWR
G76
1
2
GAP-CLOSE-PWR
G75
2
1
GAP-CLOSE-PWR
G24
1
2
GAP-CLOSE-PWR
G20
2
1
GAP-CLOSE-PWR
G34
1
2
GAP-CLOSE-PWR
G37
2
1
GAP-CLOSE-PWR
G38
1
2
GAP-CLOSE-PWR
G22
2
1
GAP-CLOSE-PWR
G39
1
2
GAP-CLOSE-PWR
G65
2
1
GAP-CLOSE-PWR
G40
1
2
GAP-CLOSE-PWR
GAP-CLOSE-PWR
+1.05V_PWR_SRC
C400
SC1U10V3KX-3GP
GAP-CLOSE-PWR
G71
2
1
GAP-CLOSE-PWR
G16
1
2
GAP-CLOSE-PWR
G73
1
2
GAP-CLOSE-PWR
G62
1
2
GAP-CLOSE-PWR
G12
1
2
GAP-CLOSE-PWR
G61
1
2
C411
SC10U25V6KX-1GP
GAP-CLOSE-PWR
G13
1
2
GAP-CLOSE-PWR
G59
1
2
GAP-CLOSE-PWR
G14
1
2
C125
SC10U25V6KX-1GP
G60
GAP-CLOSE-PWR
G74
2
1
+PWR_SRC
+1.05V_VCCP
G69
1
DY
C121
SC2200P50V2KX-2GP
+1.05V_PWR_SRC
G15
+1.05V_RUNP
+PWR_SRC
C412
SC10U25V6KX-1GP
+1.05V_VCCP
G67
2
C120
SCD1U50V3KX-GP
+1.05V_SUSP+/- 5%
Peak current 20.4A
22.44<OCP<28.5
U49
PR15
D19
DY
2
+5V_RUN
PM_SLP_S3#
TI: Non_ASM
RT :ASM
ST330U2D5VDM-13GP
1
2
1
2
+1.05V_VOUT
1
R353
12KR2F-L-GP
DY
2
L/S: FDS8672S SO-8

5.3mOhm/7.0mohm@4.5Vgs
84.08672.A37
+1.05V_VFB
C382
SC18P50V2JN-1-GP
TI: Non_ASM
RT :ASM
Vout=0.75V*(R1+R2)/R2
BAW56-2-GP
RT: Non_ASM
TI: ASM
C429
SC330P50V3KX-GP
+1.05V_LL
TC5
DY 17K4R3F-GP
TC6
ST330U2D5VDM-13GP
+3.3V_RUN
100KR2J-1-GP
TPS51117PWR-GP
C413
SCD1U10V2KX-4GP
R388
2D2R5F-2-GP
R358
1
G35
DY
U51
FDS8672S-GP
GAP-CLOSE-PWR-3-GP
7
8
24,31,32
GND
PGND
TON
TRIP
RUNPWROK
+1.05V_DRVL
+1.05V_VOUT
U16
FDS8672S-GP
9
3
6
1
2
COIL-1UH-33-GP
5
6
7
8
DRVL
VOUT
PGOOD
4
3
2
1
EN_PSV
+1.05V_RUNP
L14
5
6
7
8
VBST
VFB
1
2
2
2
DY
1M1R2J-GP
PR13
1
R366
6K19R2D-1-GP
+1.05V_TON
2
+1.05V_TRIP 11
C378
SCD01U50V2KX-1GP
2 200KR2J-L1-GP
+1.05V_PWR_SRC
R363 1
+1.05V_LL
S
S
S
G
2 100KR2J-1-GP
+1.05V_DRVH
12
D
D
D
D
RT: Non_ASM
TI: ASM
14
5
+1.05V_EN
13
LL
S
S
S
G
PM_SLP_S3#
+1.05V_VBST
+1.05V_VFB
1
D23
R355 1
DRVH
V5FILT
V5DRV
D
D
D
D
18,24,25,31,32,34,41
2 CH751H-40PT
4
10
4
3
2
1
+1.05V_V5FILT
D21
CH551H-30PT-GP
R352
30KR2F-GP
2
I/P cap: 10U 25V K1206 X5R/ 78.10622.52L

Inductor: 1.0UH PCMC104T1R0MN Cyntec DCR:3.0 ~3.5mohm Isat =40Arms 68.1R01A.20A
O/P cap: 330U 2.5V PSLV0E337M(15) 15mOhm 2.886Arms NEC_TOKIN/ 77.C3371.10L
H/S: IRF8707 SO-8/14.2mohm/17.5mOhm@4.5Vgs/ 84.08707.037
L/S: FDS8672S SO-8/ 5.3mOhm/7.0mohm@4.5Vgs/ 84.08672.A37
Switching freq-->350KHz
<Core Design>
Wistron Corporation
Title
Size
Document Number
Custom
DC to DC 1.05V

5
Rev
A00
Roberts
Sheet
1
30
of
58
SSID = PWR.Plane.Regulator_1p8v0p9v
TI TPS51116 for 1.8V and 0.9V
PR6
ILIM
DY 20KR2F-L-GP
14
16
2
1
13
24,30,32 RUNPWROK
18,24,41 PM_SLP_S4#
0D9V_EN
NC#12
11
EN/PSV
10
VTTEN
23
VTTIN
LX
20 TPS51116_PHS
DL
19 TPS51116_LGT
TPS51116_VDDQSNS
FB
51116_VDDQSET
+5V_ALW
6
1
+V_DDR_MCH_REF
+5116_PWR_SRC
0R2J-2-GP
PG8
DY PC10
SC1U10V3KX-3GP
1 PR3
2
0R0603-PAD
PC8
SCD033U16V3KX-GP
PU2
FDS8880-NL-GP
GAP-CLOSE-PWR
PG14
1
2
GAP-CLOSE-PWR
PG13
1
2
GAP-CLOSE-PWR
PG12
1
2
GAP-CLOSE-PWR
GAP-CLOSE-PWR
PG11
1
2
+1.8V_SUS +/- 5%
Peak current 13.9A
15.29<OCP<19.46A
GAP-CLOSE-PWR
PG9
1
2
B
GAP-CLOSE-PWR
PG15
1
2
+0.9V_DDR_VTT
+1.8V_SUS_P
TPS51116_UGT
PL1
TPS51116_PHS
VTTREF
VTT
S0
Hi
Hi
On
On
S3
Lo
Hi
On
On
Off(Hi-Z)
S4/S5
Lo
Lo
Off
Off
Off
PC13
SC330P50V3KX-GP
TPS51116_LGT
TPS51116_VDDQSNS
On
1
2
1
2
GAP-CLOSE-PWR
DY
DY
VDDR
PR5
42K2R2F-L-GP
DY
S5
S3
GAP-CLOSE-PWR
PG17
1
2
PC11
SC18P50V2JN-1-GP
State
PTC1
ST330U2D5VDM-13GP
DY
2
4
3
2
1
S
S
S
G
TPS51116_PHS_SET
PTC2
ST330U2D5VDM-13GP
DY
PC15
SCD1U10V2KX-4GP
D
D
D
D
U14
FDS8672S-GP
PR10
2D2R5F-2-GP
GAP-CLOSE-PWR
PC1
SCD1U25V3KX-GP
GAP-CLOSE-PWR
PG16
1
2
1
2
IND-1D5UH-23-GP
PC14
SC4D7U6D3V5KX-3GP
TPS51116_VBST
GAP-CLOSE-PWR
PG1
1
2
PG18
GAP-CLOSE-PWR-3-GP
PG2
1
5
6
7
8
1
2
+0D9V_DDR_P
PC6
SC10U6D3V5MX-3GP
PC4
SC10U6D3V5MX-3GP
PC5
SC10U6D3V5MX-3GP
1
2
PC3
SCD1U10V2KX-4GP
4
3
2
1
S
S
S
G
+0D9V_DDR_P
GAP-CLOSE-PWR
PG10
1
2
GAP-CLOSE-PWR
PG3
2
1
25
VCCA
+1.8V_SUS
GAP-CLOSE-PWR
PG5
2
1
PR17
VTTS
GND
D
D
D
D
VDDQS
PC20
SC4D7U25V5KX-GP
VTT
DY
TON
+1.8V_SUS_P
GAP-CLOSE-PWR
PG7
2
1
PC18
SCD1U50V3KX-GP
4
24
PGND1
PGND1
PGND2
PC17
SC1KP50V2KX-1GP
GAP-CLOSE-PWR
PG4
2
1
18
17
2 0R0402-PAD
A00.08/0903
+0D9V_DDR_P
NC#7
REF
+1.8V_SUS_P
PR14 1
+5116_PWR_SRC
2
TPS51116RGER-GP-U
1
DY
C89
SCD1U10V2KX-4GP
PG6
VSSA
PR16 1
DH
21 TPS51116_UGT
+PWR_SRC
+5V_ALW
PC2
SC1U10V3KX-3GP
2 1M1R2J-GP
0D9V_EN
2 0R2J-2-GP
2 TPS51116_VBST
ASM
2 0R0402-PAD
DY
0R3-0-U-GP
PR7 Non_ASM
22 TPS51116_VBST1
PGD
12
+1.8V_SUS_P
PR1
BST
PC19
SC10U25V6KX-1GP
2ND
RT
PR8
PU1
1ST
TI
PR9
DY
RT
2 619KR2F-GP
PD1
CH551H-30PT-GP
PC12
SC10U25V6KX-1GP
DY
PM_SLP_S3#
18,24,41 PM_SLP_S4#
5
6
7
8
PR7
A00.08/0903
18,24,25,30,32,34,41
SC1KP50V2KX-1GP
+5V_ALW
+3.3V_ALW
PC7
VDDP
+5116_PWR_SRC
15
VDDP
9K31R2F-GP
SC1U10V3KX-3GP
PC9
2
1
251116_VDD
+5V_ALW
PR2
RT: Non_ASM
TI: ASM
4/14 modify.
Add RC circuit for power sequence.
PR4
5D1R3J-GP
PC16
SC1U10V3KX-3GP
+5V_ALW
51116_VDDQSET
A
<Core Design>
VDDQ (V)
VTTREF and VTT
GND
2.5
VVDDQSNS/2
DDR
V5IN
1.8
VVDDQSNS/2
DDR2
FB Resistors
Adjustable
VVDDQSNS/2
Close to VFB Pin (pin5)
NOTE
PR18
30KR2F-GP
I/P cap: 10U 25V K1206 X5R/ 78.10622.52L

Inductor: 1.5UHPCMC063T-1R5MN Cyntec DCR:14~15mohm Isat =18Arms 68.1R510.10K
O/P cap: 330U 2.5V PSLV0E337M(15) 15mOhm 2.886Arms NEC_TOKIN/ 77.C3371.10L
H/S: FDS8880 SO-8/9.6mohm/ 12mOhm@4.5Vgs/ 84.08880.037
L/S: FDS8672S SO-8/ 5.3mOhm/7.0mohm@4.5Vgs/ 84.08672.A37
Switching freq-->400KHz
1.5 V < VVDDQ < 3 V
DY
Wistron Corporation
VDDQSET

Title
DC to DC 1.8V/0.9V
Size
Document Number
Custom

5
Rev
A00
Roberts
Sheet
1
31
of
58
SSID = PWR.Plane.Regulator_1p5v
Change from +5V_RUN to +5V_ALW,

please confrim it is okay.
1
C205
SC10U6D3V5MX-3GP
DY
2
C208
SC1U10V3KX-3GP
1D5V_SB
+1.8V_SUS
+5V_ALW
C206
SC10U6D3V5MX-3GP
APL5912-KAC-GP
SO-8-P
DY
2
FB
TC23
ST100U6D3VBM-5GP
GND
DY
TC22
ST100U6D3VBM-5GP
C216
SC4700P50V2KX-1GP
VOUT
VOUT
+1.5V_RUN
5
9
3
4
EN
VIN
VIN
C212
SCD01U16V2KX-3GP
POK
Vo=0.8*(1+(R1/R2))
R176
1KR2F-3-GP
PM_SLP_S3#
1D5V_EN
2
2K2R2J-2-GP
18,24,25,30,31,34,41
1
R189
VCNTL
U21
7
24,30,31 RUNPWROK
+1.5V_RUN +/- 5%
Peak current 3.5A
R184
1K13R2F-1-GP
NEC_TOKIN
100uF, 6.3V, B2 Size
Iripple=1.374A, ESR=45mohm
<Core Design>
Wistron Corporation
Title
Size
Document Number
Custom
DC to DC 1.5V

5
Rev
A00
Roberts
Sheet
1
32
of
58
(Blanking)
<Core Design>
Wistron Corporation
Title
Size
Document Number
Custom
VGA Power
Date: Tuesday, September 09, 2008

5
Rev
A00
Roberts
Sheet
1
33
of
58
SSID = Reset.Suspend
D
R161
H_PWRGD_R
1KR2J-1-GP
C198
SCD1U10V2KX-4GP
2
D10
BAS16-1-GP
DY
DY
Q8
CHT2222APT-GP
PURE_HW_SHUTDOWN#
24,25
3V_5V_EN
1
27
B
1
DY
6,17 H_PWRGOOD
R160
200KR2J-L1-GP
1
R168
2
1KR2J-1-GP
S5_ENABLE 24
DY
Run Power
+5V_ALW
+5V_RUN
1
2
3
4
C534
2
B
+PWR_SRC
SCD1U25V3KX-GP
R281
D
D
D
D
8
7
6
5
D
D
D
D
8
7
6
5
AO4468-GP
C314
SC6800P25V2KX-1GP
D16
DY BZX384-C9V1-GP
A
1
G
1 Z_12V_G3
330KR2F-L-GP
2 10KR2J-3-GP
RUN_POWER_ON
100KR2J-1-GP
R458
Z_12V
2
S
10KR2J-3-GP
NDS0610-NL-GP
84.S0610.B31
R275 1
Q22
1
R460
DY1
U30
S
S
S
G
R459
100KR2J-1-GP
R273 1
2 10KR2J-3-GP
Q23
2N7002-7F-GP
18,24,25,30,31,32,41
PM_SLP_S3#
U31
S
S
S
G
AO4468-GP
C316
SCD01U50V2KX-1GP
Q21
2N7002-7F-GP
<Core Design>
+3.3V_ALW
1
2
3
4
Z_12V_D3 2
+3.3V_RUN
Wistron Corporation
Title
Power Plane Enable
Size
Document Number
Custom

5
Rev
A00
Roberts
Sheet
1
34
of
58
SSID = VIDEO
SSID = Inverter
LVDS CONNECTOR
1
C68
SC1KP50V2KX-1GP
1
FUSE-3A32V-7-GP
C69
SCD1U50V3KX-GP
BRIGHTNESS 24
R73
1
VGA_TXBOUT0- 13
VGA_TXBOUT0+ 13
VGA_TXAOUT1- 13
VGA_TXAOUT1+ 13
VGA_TXAOUT2VGA_TXAOUT2+
VGA_TXAOUT2- 13
VGA_TXAOUT2+ 13
VGA_TXACLK-
VGA_TXACLK- 13
VGA_TXACLK+
VGA_TXACLK+ 13
AFTP5
LCD_BRIGHTNESS
LCD_TST
VGA_TXBOUT0VGA_TXBOUT0+
48
IPEX-CONN40-2R-GP
20.F1093.040
1
1
1
1
1
1
1
1
DY
AFTP1
AFTP3
AFTP2
AFTP4
AFTP7
AFTP6
AFTP9
AFTP8
VGA_TXAOUT0- 13
VGA_TXAOUT0+ 13
SSID = VIDEO
EC19
SC33P50V2JN-3GP
VGA_TXBCLK- 13
VGA_TXBCLK+ 13
DY
2
VGA_TXBOUT2- 13
VGA_TXBOUT2+ 13
VGA_TXBOUT1- 13
VGA_TXBOUT1+ 13
EC87
SC33P50V2JN-3GP
100R2F-L1-GP-U
1
2
1 R81
2
0R0402-PAD
BLON_OUT 24
LCD_TST 24
LDDC_CLK 13
LDDC_DATA 13
LBKLT_CTL 13
LCD POWER
For EMI request
+LCDVDD
+3.3V_RUN
U48
D20
2
BAT54CPT-GP
VGA_TXACLKVGA_TXACLK+
ENVDD
49K9R2F-L-GP
IN#1
OUT
EN
GND
GND
IN#8
IN#7
IN#6
IN#5
9
8
7
6
5
1
LCD_TST_EN
24
ENVDD_D 1
1
2
3
4
C73
SC1U10V3KX-3GP
R508
G5281RC1U-GP
2
C392
SCD1U16V2KX-3GP
LCDVDD_EN
R359
49K9R2F-L-GP
13
EC37
SC5D6P50V2CN-1GP
<Core Design>
DY
2
EC38
SC5D6P50V2CN-1GP
DY
2
EC20
SC5D6P50V2CN-1GP
DY
2
EC21
SC5D6P50V2CN-1GP
DY
2
DY
2
DY
EC27
SC5D6P50V2CN-1GP
EC28
SC5D6P50V2CN-1GP
DY
2
DY
EC23
SC5D6P50V2CN-1GP
DY
EC26
SC5D6P50V2CN-1GP
DY
2
EC40
SC5D6P50V2CN-1GP
DY
2
EC39
SC5D6P50V2CN-1GP
DY
2
DY
2
DY
EC35
SC5D6P50V2CN-1GP
EC36
SC5D6P50V2CN-1GP
DY
2
DY
EC29
SC5D6P50V2CN-1GP
EC30
SC5D6P50V2CN-1GP
41
1
50
EC24
SC5D6P50V2CN-1GP
42
DY
RB551V30-GP
LCD_CBL_DET# 24
LCD_TST
LDDC_CLK
LDDC_DATA
LCD_DET_G
+PWR_SRC
F1
D7
K
43
+3.3V_RUN
LCD_BRIGHTNESS
GFX_PWR_SRC
DYR75
10KR2J-3-GP
EC25
SC5D6P50V2CN-1GP
44
+3.3V_RUN
45
1
46
51
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
EC22
SCD1U10V2KX-4GP
49
47
INVERTER POWER
+LCDVDD
C76
SC1U10V3KX-3GP
GFX_PWR_SRC
LCD1
Wistron Corporation
Title
For EMI request
LCD/Inverter Connector
Size
Document Number
Custom
Sheet
Rev
A00
Roberts
35
of
58
SSID = SATA
SATA HDD Connector
G81
1
2
+5V_HDD
G82
C289
SC10U6D3V5MX-3GP
GAP-CLOSE-PWR
1A
2A
3A
V33
V33
V33
7A
8A
9A
V5
V5
V5
13A
14A
15A
V12
V12
V12
GAP-CLOSE-PWR
2
6
C498
SCD1U16V2KX-3GP
Q20
DY
U57
HDD_5V_EN_R
R457
100KR2J-1-GP
R462
DY100KR2J-1-GP
HDD1
DY DY
C508
SC10U6D3V5MX-3GP
+5V_RUN
+5V_HDD
+5V_RUN
+3.3V_RUN
RUN_POWER_ON
+5V_ALW
C277
SCD1U16V2KX-3GP
AFTP11
HDD_5V_EN 24
HDD_PWR_EN
1
DY
2N7002SPT
DY
C527
SCD1U25V3KX-GP
DY
11A
NP1
NP2
FDC655BN-GP
A+
AB+
B-
GND
GND
GND
GND
GND
GND
RESERVED#11A GND
GND
NP1
GND
NP2
GND
S2
S3
SATA_TXP0 17
SATA_TXN0 17
S6
S5
SATA_RXP0
SATA_RXN0
S1
S4
S7
4A
5A
6A
10A
12A
1
2
C254 2
C250 2
1 SC3900P50V2KX-2GP
1 SC3900P50V2KX-2GP
SATA_RXP0_C 17
SATA_RXN0_C 17
AFTP10
SKT-SATA15P+S7-1-GP
20.81107.022
1
1
1
1
1
1
AFTP12
AFTP14
AFTP13
AFTP16
AFTP15
AFTP17
+3.3V_RUN
+5V_HDD
SATA_RXP0
SATA_RXN0
SATA_TXN0
SATA_TXP0
SSID = SATA
1 GAP-CLOSE-PWR
1 GAP-CLOSE-PWR
G85
1 GAP-CLOSE-PWR
G86
1 GAP-CLOSE-PWR
R252
100KR2J-1-GP
DY
2
HDD_5V_EN 24
2N7002SPT
ODD1
P3
P2
1
2
3
4
17 SATA_TXN1
17 SATA_TXP1
17 SATA_RXN1_C
17 SATA_RXP1_C
SI4800BDY-T1
ODD_PWR_EN
DY
DY
C452
SCD1U10V2KX-4GP
C469 2
C467 2
1 SCD01U50V2KX-1GP
1 SCD01U50V2KX-1GP
SATA_RX1-_C
SATA_RX1+_C
+5V
+5V
S3
S2
TXTX+
S5
S6
RXRX+
NP1
NP2
NP1
NP2
8
7
6
5
C295
SCD1U25V3KX-GP
DY
C293
SC4700P50V2KX-1GP
R255
100KR2J-1-GP
DY
SATA_RX- and SATA_RX+ Trace

Length match within 20 mil
DY
D
D
D
D
U28
ODD_5V_EN_R
U58
G
S
S
S
DY
C455
SC10U6D3V5MX-3GP
G84
+5V_MOD
G83
1
+5V_ALW
R251
100KR2J-1-GP
ODD Connector
+5V_RUN
+5V_MOD
+5V_RUN
RUN_POWER_ON
DETECT
P1
MD
P4
GND
GND
GND
GND
GND
GND
GND
P5
P6
S1
S4
S7
8
9
ODD_MD
AFTP18
AFTP19
+5V_MOD
SATA_TXN1
SATA_TXP1
SATA_RX1-_C
SATA_RX1+_C
SKT-SATA7P+6P-40-GP
22.10300.271
1
1
1
1
1
AFTP20
AFTP21
AFTP22
AFTP24
AFTP23
Fan Connector
SSID = Thermal
FAN1
4
3
25 EMC2102_FAN_TACH_1
EMC2102_FAN_TACH_1
25 EMC2102_FAN_DRIVE
EMC2102_FAN_DRIVE
AFTP25
3
2
<Core Design>
*Layout* 15 mil
Wistron Corporation
1
K

5
D4
RB551V30-GP
MLX-CON3-6-GP-U
20.F0700.003
Title
AFTP26
EMC2102_FAN_TACH_1
AFTP27
EMC2102_FAN_DRIVE
C16
SC22U6D3V5MX-2GP
Size
Document Number
Custom
HDD/ODD/FAN
Rev
A00
Roberts
Sheet
36
of
58
8
9
10
4 CLK_PCIE_MINI1#
11
4 CLK_PCIE_MINI1
13
PLT_RST#
R498 1
PCLK_FWH
R499 1
24
E51_RXD
R211 1
24
E51_TXD
R210 1
DY
DY
DY
DY
2 0R2J-2-GP
15
16
2 0R2J-2-GP
2 0R2J-2-GP
E51_RXD_R
17
2 0R2J-2-GP
E51_TXD_R
19
24
LPC_LAD0
0R2J-2-GP
21
21
21
21
21
21
21
21
17,24
24
21
21
21
21
21
21
21
21
+3.3V_RUN
25
26
27
28
29
16
PCIE_TXN2
31
16
PCIE_TXP2
33
30
SMB_CLK
32
SMB_DATA
36
USB_PN4
38
USB_PP4
37
SMB_CLK 18,41
8
9
26
27
28
30
31
32
XD_D0
XD_D1
XD_D2
XD_D3
XD_D4
XD_D5
XD_D6
XD_D7
XD_RDY
SD_DAT2/XD_RE#
XD_CE#
XD_CLE
XD_ALE
SD_DAT3/XD_WE#
XD_WP#
XD_CD#
XD_RDY
SD_DAT2/XD_RE#
XD_CE#
XD_CLE
XD_ALE
SD_DAT3/XD_WE#
XD_WP#
XD_CD#
1
2
3
4
5
6
7
34
XD_R/B
XD_RE
XD_CE
XD_CLE
XD_ALE
XD_WE
XD_WP
XD_CD_SW
NP1
NP2
A00.08/0903
1
AFTP54
AFTP55
43
NP2
52
5
SKT-MINI52P-21-GP
62.10043.581
ITP_TDI
5
5
ITP_TMS
ITP_TRST#
ITP_TCK
5
ITP_TDO
4 CLK_CPU_ITP#
4 CLK_CPU_ITP
5,8 H_CPURST#
ITP_BPM#5
ITP_BPM#4
ITP_BPM#3
ITP_BPM#2
ITP_BPM#1
ITP_BPM#0
C471
SCD1U16V2KX-3GP
1
2
C294
SC10U6D3V5MX-3GP
+1.5V_RUN
C241
SCD1U16V2KX-3GP
1
2
C235
SC10U6D3V5MX-3GP
+3.3V_RUN
EC143
SC220P50V2KX-3GP
1
2
EC144
SC220P50V2KX-3GP
EC146
SC220P50V2KX-3GP
EC147
SC220P50V2KX-3GP
SD_DAT0/XD_D6/MS_D0
XD_D4/SD_DAT1
SD_DAT2/XD_RE#
SD_DAT3/XD_WE#
SD_CMD
SD_CLK
SD_CD_SW
SD_WP_SW
12
24
36
35
SD_CMD
SD_CLK
SD_CD#
SD_WP
MS_DATA0
MS_DATA1
MS_DATA2
MS_DATA3
19
20
18
16
SD_DAT0/XD_D6/MS_D0
XD_D3/MS_D1
XD_D2/MS_D2
XD_D7/MS_D3
MS_BS
MS_INS
MS_SCLK
21
17
15
XD_D5/MS_BS
MS_INS#
MS_CLK
4IN1_GND
4IN1_GND
4IN1_GND
4IN1_GND
13
22
38
37
1
1
1
1
AFTP37
AFTP40
AFTP38
AFTP47
SD_CMD
SD_CLK
SD_CD#
SD_WP
21
21
21
21
1
1
1
AFTP48
AFTP50
AFTP49
AFTP51
MS_INS# 21
MS_CLK 21
AFTP52
NP1
NP2
ITP Connector
1
1
1
1
1
1
1
1
1
1
1
1
1
AFTP56
AFTP59
AFTP58
AFTP61
AFTP65
AFTP64
AFTP67
AFTP69
AFTP72
AFTP71
AFTP73
AFTP75
AFTP74
ITP_TMS
ITP_TRST#
ITP1
R23
R21
R10
ITP_TCK
ITP_TDO
CLK_CPU_ITP#
CLK_CPU_ITP
0R2J-2-GP
DY
0R2J-2-GP
2
2 0R2J-2-GP
0R2J-2-GP
ITP_TMS_1
ITP_TRST#_1
ITP_TDO_1
CLK_CPU_ITP#_1
CLK_CPU_ITP_1
1
1
DY
DY
DY
DY
DY
DY
DY
DY
2
2 1KR2J-1-GP
0R2J-2-GP
2
0R2J-2-GP
2
0R2J-2-GP
2
0R2J-2-GP
2
0R2J-2-GP
2
0R2J-2-GP
2
0R2J-2-GP
H_CPURST#_1
ITP_BPM#5_1
R3
ITP_BPM#2
R5
ITP_BPM#1
R6
R344
2
1K2R2F-1-GP
R11
54D9R2F-L1-GP
R4
R343
1
1
1
1
1
1
ITP_BPM#4_1
ITP_BPM#3_1
ITP_BPM#2_1
ITP_BPM#1_1
ITP_BPM#0_1
ITP_DBRESET#_1
+1.05V_VCCP
18 ITP_DBRESET#_1
DY
30
Wistron Corporation
ITP Connector
TCK(PIN 5)
Title
FBO(PIN 11)
Size
Document Number
Custom
TCK(PIN AC5)
MINICARD(WLAN)/SD/ITP CONNRev

3
<Core Design>
WLAN_ACT
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
MLX-CON28-3-GP
20.K0116.028
+1.05V_VCCP use Decoupling Capacitor close

ITP connector 100 mil ( max )
EC65
SC220P50V2KX-3GP
2
2 22D6R2F-L1-GP
2 0R2J-2-GP
0R2J-2-GP
R15
29
ITP_TDI_1
DY
DY
DY
ITP_BPM#3
+3.3V_RUN
1
R18 1
R345 1
R342
R8
R12
ITP_DBRESET#
1
1
DY
DY
DY
ITP_TCK_1
DY
ITP_BPM#0
R25
1
2
ITP_BPM#5
150R2F-1-GP
ITP_BPM#4
R22
54D9R2F-L1-GP
CPU
H_CPURST# use pull-up Resistor close

ITP connector 500 mil ( max ),
others place near CPU side.
R19
WLAN_ACT
CLK_PCIE_MINI1#
CLK_PCIE_MINI1
E51_TXD_R
E51_RXD_R
PCIE_RXN2
PCIE_TXP2
+3.3V_RUN
+1.5V_RUN
WIFI_RF_EN
PLT_RST#
SMB_CLK
SMB_DATA
1
C468
SCD1U16V2KX-3GP
+3.3V_RUN
+5V_ALW
DY
5 ITP_DBRESET#
ITP_TDI
51
0R3-0-U-GP
R16
54D9R2F-L1-GP
2
1
50
2
54
25
29
10
11
DY
R9
51R2F-2-GP
2
1
R17
54D9R2F-L1-GP
2
1
49
R171
DY
SSID = User.Interface
48
DY
SD_DAT0
SD_DAT1
SD_DAT2
SD_DAT3
+1.05V_VCCP
46
DY
DY
CARD-PUSH-36P-5-GP
20.I0081.011
44
47
DY
DY
USB_PP4 16
45
+5V_ALW
DY
40
42
AFTP53
XD_D0
SD_CLK/XD_D1/MS_CLK
XD_D2/MS_D2
XD_D3/MS_D1
XD_D4/SD_DAT1
XD_D5/MS_BS
SD_DAT0/XD_D6/MS_D0
XD_D7/MS_D3
USB_PN4 16
41
C305
SCD1U16V2KX-3GP
SD_VCC
MS_VCC
XD_VCC
XD_D0
SD_CLK/XD_D1/MS_CLK
XD_D2/MS_D2
XD_D3/MS_D1
XD_D4/SD_DAT1
XD_D5/MS_BS
SD_DAT0/XD_D6/MS_D0
XD_D7/MS_D3
SMB_DATA 18,41
39
+3.3V_RUN
DY
CARD1
23
14
33
34
35
1
2
LPC_LAD1
0R2J-2-GP
AFTP39
PLT_RST# 9,16,20,21,24,41
23
LPC_LAD2
0R2J-2-GP
WIFI_RF_EN
PLT_RST#
22
16 PCIE_RXP2
+3.3V_RUN_CARD
DY
SD_CMD
SD_CD#
SD_WP
MS_INS#
XD_D0
XD_RDY
XD_CE#
XD_CLE
XD_ALE
XD_WP#
XD_CD#
SD_CLK
MS_CLK
SD_CLK/XD_D1/MS_CLK
1
1
1
1
1
1
1
1
1
1
1
1
1
1
AFTP29
AFTP28
AFTP30
AFTP42
AFTP41
AFTP32
AFTP31
AFTP34
AFTP33
AFTP45
AFTP44
AFTP36
AFTP35
AFTP46
LPC_LAD3
0R2J-2-GP
18
20
For EMI
LPC_LFRAME# 17,24
LPC_LAD[0..3]
21
16 PCIE_RXN2
0R2J-2-GP
DY
R20
54D9R2F-L1-GP
2
1
14
DY 2
DY 2
DY 2
DY 2
DY 2
DY
R24
54D9R2F-L1-GP
2
1
9,16,20,21,24,41
12
R493
LPC_LFRAME#_IN1
R494
LPC_LAD3_IN
1
R495
LPC_LAD2_IN
1
R496
LPC_LAD1_IN
1
R497
LPC_LAD0_IN
1
DY
EC145
SC220P50V2KX-3GP
6
7
4 MINI1_CLKREQ#
C274
SC2D2U10V3KX-1GP
DY
BT_ACT
DY
2
C287
SCD1U16V2KX-3GP
41,47
WLAN_ACT
2
41,47
C275
SCD1U16V2KX-3GP
NP1
1
MINI_2_WAKE#
C272
SCD1U16V2KX-3GP
AFTP43
+3.3V_RUN_CARD
EC142
SC220P50V2KX-3GP
+3.3V_RUN
53
+1.5V_RUN
SD_DAT0/XD_D6/MS_D0
XD_D4/SD_DAT1
SD_DAT2/XD_RE#
SD_DAT3/XD_WE#
SD_CMD
SD_CLK
SD_CD#
SD_WP
Mini Card Connector(802.11a/b/g)

MINI1
SD/XD/MS Card Reader
SSID = SDIO
EC74
SC220P50V2KX-3GP
SSID = Wireless
EC75
SC220P50V2KX-3GP
A00
Roberts
Sheet
1
37
of
58
(Blanking)
<Core Design>
Wistron Corporation
Title
MINICARD(WWAN)
Size
Document Number
Custom
Date: Monday, September 22, 2008

5
Rev
A00
Roberts
Sheet
1
38
of
58
(Blanking)
<Core Design>
Wistron Corporation
Title
MINICARD(WPAN)
Size
Document Number
Custom
Date: Monday, September 22, 2008

5
Rev
A00
Roberts
Sheet
1
39
of
58
SSID = AUDIO
SPK1
1
2
C559
SC1U10V3KX-3GP
MIC1
2
3
4
MLX-CON4-15-GP-U
20.F0693.004
DY
MIC IN
1
1
AFTP76
22 AUD_EXT_MIC_L
AUD_EXT_MIC_L
C539 2
1 SC1U10V3KX-3GP
MIC_IN_L_2
R481 2
1 0R3-0-U-GP
MIC_IN_L_C
AUD_EXT_MIC_R
C540 2
1 SC1U10V3KX-3GP
MIC_IN_R_2
R480 1
2 0R3-0-U-GP
MIC_IN_R_C
1
2
6
AUD_SPK_L1_R
AUD_SPK_R2_R
AUD_SPK_R1_R
EC8
SC100P50V2JN-3GP
22 AUD_EXT_MIC_R
3
4
1
1
1
1
AUD_SPK_L2_R
AUD_SPK_L1_R
AUD_SPK_R2_R
AUD_SPK_R1_R
AFTP77
AFTP79
AFTP80
AFTP78
5
7
8
9
10
EC158
SC100P50V2JN-3GP
22 EXT_MIC_JD#
EC157
SC100P50V2JN-3GP
2
1
DY
DY
DY
2 0R3-0-U-GP
2 0R3-0-U-GP
2 0R3-0-U-GP
2 0R3-0-U-GP AUD_SPK_L2_R
1
1
1
EC6
SC100P50V2JN-3GP
R28
R31
R32
R30
AUD_SPK_L1
AUD_SPK_R2
AUD_SPK_R1
EC4
SC100P50V2JN-3GP
AUD_SPK_L2
AUD_SPK_L1
AUD_SPK_R2
AUD_SPK_R1
AUD_SPK_L2
23
23
23
EC3
SC100P50V2JN-3GP
23
R470
4K7R2J-2-GP
Speaker Connector
R471
4K7R2J-2-GP
2
1
22 AUD_VREFOUT_B
PHONE-JK284-GP
22.10133.D01
AFTP81
MIC_IN_L_C
AFTP82
MIC_IN_R_C
AFTP83
EXT_MIC_JD#
LINE1 OUT
Internal Microphone
LOUT1
1
AFTP84
AUD_HP1_JACK_L2
AUD_HP1_JACK_L1
AUD_HP1_JACK_R
AUD_HP1_JACK_R2
AUD_HP1_JACK_R1
L19
L20
BLM18BD601SN1D-GP
R474
60D4R2F-GP
DY
600ohm 100MHz
200mA 0.5ohm DC
DY
2
23 AUD_HP1_JACK_R
2
EC160
SC1KP50V2KX-1GP
60D4R2F-GP
R475
2
AUD_HP1_JD#
EC156
SC100P50V2JN-3GP
23 AUD_HP1_JACK_L
AUD_HP1_JACK_L
22,23 AUD_HP1_JD#
CN6
MICROPHONE-40-GP-U1
23.42143.001
EC155
SC100P50V2JN-3GP
1
2
INT_MIC_L_R
1
22 INT_MIC_L_R
B
BLM18BD601SN1D-GP
4
5
7
8
9
10
PHONE-JK284-GP
22.10133.D01
AFTP85
AUD_HP1_JD#
AFTP86
AUD_HP1_JACK_L1
AFTP87
AUD_HP1_JACK_R1
<Core Design>
Wistron Corporation
Title
Size
Document Number
Custom
5
Audio Jack
Rev
A00
Roberts
Sheet
1
40
of
58
AUD_DMIC_IN0_R
R70
1
2 33R2J-2-GP
+3.3V_CAMERA
USB_PN11
USB_PP11
CAMERA_DET# 24
AUD_DMIC_CLK_G 22
2 33R2J-2-GP
AUD_DMIC_IN0
R69
22
L2
DLW21SN900SQ2LUGP
DY
1
AFTP107
C65
SC4D7P50V2CN-1GP
DY
DY
2
ACES-CON8-3-GP-U
20.F0779.008
1
9
DY
NEWCARD_CLKREQ#
+3.3V_CARD
PERST#
+3.3V_CARDAUX
PCIE_WAKE#
+1.5V_CARD
SMB_DATA
SMB_CLK
AUD_DMIC_CLK_G_R
1
1
1
1
1
1
1
1
USB_PN11 16
8
7
6
5
4
3
2
AFTP105
AFTP106
AFTP108
AFTP110
AFTP109
AFTP112
AFTP111
AFTP113
CAMERA1
10
PCIE_TXP5
PCIE_TXN5
PCIE_RXP5
PCIE_RXN5
CLK_PCIE_NEW
CLK_PCIE_NEW#
+3.3V_ALW
LID_CLOSE#
CPUSB#
USB_PP7
USB_PN7
1
1
1
1
1
1
1
1
1
1
1
C505
SCD1U16V2KX-3GP
1
2
+3.3V_CARDAUX
C502
SCD1U16V2KX-3GP
C262
SC10U6D3V5MX-3GP
1
2
+1.5V_CARD
C486
SCD1U16V2KX-3GP
1
2
C484
SC10U6D3V5MX-3GP
+3.3V_CARD
C256
SC4D7U6D3V5KX-3GP
1
2
DY
C487
SCD1U16V2KX-3GP
C504
SCD1U16V2KX-3GP
C499
SCD1U16V2KX-3GP
+3.3V_RUN
+1.5V_RUN
AFTP92
AFTP96
AFTP95
AFTP98
AFTP97
AFTP100
AFTP99
AFTP101
AFTP102
AFTP103
AFTP104
Camera Connector
EC18
SC33P50V2JN-3GP
Place them Near to Chip

+3.3V_ALW
SSID = ExpressCard
EC17
SC33P50V2JN-3GP
USB_PP11 16
Digital Mic Power

+3.3V_CAMERA
16
14
13
5
4
20
8
9
10
6
SHDN#
PERST#
CPUSB#
CPPE#
SYSRST#
PERST#
CPUSB#
CPPE#
NRST
15
17
11
12
3
2
+3.3V_CARDAUX
+3.3V_ALW
+1.5V_CARD
PM_SLP_S4# 18,24,31
RN24
3
4
DY
2
DY
C66
SC4D7U6D3V3KX-GP
EC14
SC220P50V2KX-3GP
DY
2
21
19
18
1
NC#16
1_5VIN
1_5VOUT
3_3VOUT
3_3VIN
DY
2
1
+3.3V_ALW
AFTP89
AFTP88
AFTP90
AFTP91
AFTP93
AFTP94
SRN100KJ-6-GP
AUXOUT
AUXIN
1_5VOUT
1_5VIN
3_3VOUT
3_3VIN
+1.5V_RUN
+1.5V_CARD
+3.3V_CARD
+3.3V_RUN
EC16
SCD1U16V2KX-3GP
AUD_DMIC_CLK_G_R
GND
OC#
RCLKEN
STBY#
GND
U55
AUD_DMIC_IN0_R
1 R77
2
0R0603-PAD
AFTP114
PM_SLP_S3# 18,24,25,30,31,32,34
NEWCARD_OC#
EC15
SC220P50V2KX-3GP
+3.3V_RUN
R435 2
1 0R2J-2-GP
C494 2
1 SC22P50V2JN-4GP
PLT_RST# 9,16,20,21,24,37
CAMERA_DET#
AUD_DMIC_CLK_G_R
AUD_DMIC_IN0_R
+3.3V_CAMERA
USB_PN11
USB_PP11
1
1
1
1
1
1
DY
G577BR91U-GP
+3.3V_RUN
+3.3V_CARD
+1.5V_RUN
Bluetooth Module conn.
+1.5V_CARD Max. 650mA, Average 500mA.

+3.3V_CARD Max. 1300mA, Average 1000mA
+3.3V_CARDAUX Max. 275mA
B
BT1
+3.3V_RUN
11
1
37,47
BT_ACT
37,47 WLAN_ACT
18,37 SMB_DATA
18,37 SMB_CLK
AFTP123
AFTP122
1
1
CONN_TP2
CONN_TP3
FOX-CONN30A-9GP
20.F0908.030
EC32
SC220P50V2KX-3GP
12
FOX-CON10-GP-U
20.F0711.010
DY
2
DY
2
DY
EC31
SC22P50V2JN-4GP
DY
EC33
SC22P50V2JN-4GP
USB_PP6
USB_PN6
BLUETOOTH_EN
WLAN_ACT
+3.3V_RUN
1
1
1
1
1
C77
SC2D2U10V3KX-1GP
AFTP116
AFTP115
AFTP117
AFTP118
AFTP119
PCIE_TXP5 16
PCIE_TXN5 16
AFTP120
R83
10KR2J-3-GP
1
4
6
8
10
12
14
16
18
20
22
24
26
28
30
PCIE_RXP5 16
PCIE_RXN5 16
CLK_PCIE_NEW
CLK_PCIE_NEW#
4
4
+3.3V_ALW
LID_CLOSE# 24
LID_CLOSE#
CPUSB#
DY
EC70
SC5P50V2CN-2GP
<Core Design>
USB_PP7 16
USB_PN7 16
Wistron Corporation
+3.3V_CARDAUX
18,20 PCIE_WAKE#
+1.5V_CARD
DY
2
PERST#
3
5
7
9
11
13
15
17
19
21
23
25
27
29
NP2
32
CPPE#
NEWCARD_CLKREQ#
AFTP121
4 NEWCARD_CLKREQ#
+3.3V_CARD
NEW1
31
NP1
1
R74
100KR2J-1-GP
16
USB_PP6
16
USB_PN6
24,47 BLUETOOTH_EN
New Card Connector
2
3
4
5
6
7
8
9
10

EC69
SC5P50V2CN-2GP
Title
Bluetooth/CAM/New Card
Size
Document Number
Custom

5
Rev
A00
Roberts
Sheet
1
41
of
58
SSID = Flash.ROM
SPI FLASH ROM (16M bits)
+3.3V_RTC_LDO
C472
SCD1U16V2KX-3GP
Power Dash Board to Board CONN

1
24 KBC_PWRBTN#
0R2J-2-GP
2 0R2J-2-GP
2 0R2J-2-GP
1
2
3
4
EC_SPI_WP#
CS#
DO
WP#
GND
EC_SPI_HOLD#
R414 1
AFTP124
2
3
4
DY
8
7
6
5
VCC
HOLD#
CLK
DIO
KBC_PWRBTN#_IN
EC161
SC220P50V2KX-3GP
6
ACES-CON4-10-GP-U
20.K0320.004
EC_SPI_CLK 24
EC_SPI_DO 24
2 33R2J-2-GP
EC133
SC4D7P50V2CN-1GP
W25X16AVSSIG-GP
2
EC135
SC4D7P50V2CN-1GP
R419 1
R482 1
EMI REQUEST
+3.3V_RTC_LDO
EC_SPI_CS#
24 EC_SPI_CS#
24 EC_SPI_DI
24 EC_SPI_WP#_R
R500
EC_SPI_HOLD#
U23
CN1
2
1
1
2
DY
C470
SCD1U16V2KX-3GP
C454
SC10U6D3V5MX-3GP
RN50
SRN100KJ-6-GP
2
R476
100KR2J-1-GP
3
4
+3.3V_RTC_LDO
EC134
SC4D7P50V2CN-1GP
SSID = RBATT
Power/Battery LED
+5V_ALW
POWER LED
LED1
R491
Q12
B
PWRLED
DY
2
R2
PDTC124EU-1-GP
PWR_LED_B
RTC Connector
White
330R2J-3-GP
24
LED_PWR#
R1
EC62
SC220P50V2KX-3GP
+3.3V_RTC_LDO
Amber
U24
+RTC_CELL
R492
R1
R2
PDTC124EU-1-GP
DY
2
BAT_LED_B
LED_BAT#
RTC_PWR_L
+RTC_VCC
RTC1
0R2J-2-GP
R220
1
C519
SC1U10V3KX-3GP
RTC_PWR
24
24
+3.3V_RUN
R33
+5V_RUN
R34
1
1
DY 2
0R3-0-U-GP
DY 2
FUSE-D5A32V-5-GP
+RTC_VCC
CN2
7
CAP_SCL
CAP_SDA
EC7
SC220P50V2KX-3GP
1
2
3
4
5
6
DY
8
ACES-CON6-12-GP
20.K0358.006
DY
2
EC5
SC220P50V2KX-3GP
CAPA_INT#
DY
AFTP129
AFTP131
AFTP130
AFTP132
1
1
1
1
+5V_RUN
CAP_SCL
CAP_SDA
CAPA_INT#
<Core Design>
Wistron Corporation
Title
FWH/LED/Power Dash/RTC/Cap
Size
Document Number
Custom

5
PWR
GND
NP1
NP2
BAT-CON2-1-GP-U
62.70001.011
Width=20mils
EC61
SC220P50V2KX-3GP
CAP_SCL
CAP_SDA
24
1
2
NP1
NP2
Capacitive Button
AFTP128
AFTP125
1KR2J-1-GP
SDMG0340LC7F-GP-U
AFTP126
270R2J-L
24 BATLOW_LED
BATT LED
Q11
R227
LED-OW-3-GP
Sheet
1
Rev
A00
Roberts
42
of
58
SSID = USB
Right USB Port CONN
+5V_USB2
USB_PN2
CN3
USB_PN2
16
4
3
2
L1
L-63UH-GP
16
AFTP127
AFTP133
AFTP135
AFTP134
1
1
1
USB_PP2
USB_PP2
MLX-CON4-15-GP-U
20.F0693.004
DY
+5V_USB2
USB_PN2
USB_PP2
+5V_USB2
+5V_ALW
U1
16
TC11
ST100U6D3VBM-7GP
C327
SC1U10V3KX-3GP
1
2
DY
RT9711BPF-GP
8
7
6
5
VOUT
VOUT
VOUT
FLG#
C328
SCD1U16V2KX-3GP
at least 80 mil
GND
VIN
VIN
EN/EN#
R296
100KR2J-1-GP
1
2
3
4
1
2
DY
EC78
SCD1U50V3KX-GP
TC12
ST100U6D3VBM-8GP
at least 80 mil
USB_OC#2
24,45 USB_PWR_EN#
<Core Design>
Wistron Corporation
Title
Size
Document Number
Custom
5
USB
Rev
A00
Roberts
Sheet
1
43
of
58
SSID = KBC
SSID = Touch.Pad
TouchPad Connector
D
AFTP137
AFTP136
AFTP138
AFTP140
AFTP139
AFTP142
AFTP141
AFTP144
AFTP143
AFTP145
AFTP150
AFTP148
AFTP147
AFTP149
AFTP151
AFTP153
AFTP152
AFTP154
AFTP156
AFTP155
AFTP158
AFTP157
AFTP159
AFTP160
AFTP162
AFTP164
KB_DET# 24
AFTP166
28
JAE-CON27-GP
20.K0291.027
RN18
SRN10KJ-5-GP
TPAD1
5
1
3
4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
24
24
KROW[0..7]
24
KCOL[0..16]
24
TPCLK
TPDATA
AFTP146
2
3
4
1
1
KCOL10
KCOL11
KCOL9
KCOL14
KCOL13
KCOL15
KCOL16
KCOL12
KCOL0
KCOL2
KCOL1
KCOL3
KCOL8
KCOL6
KCOL7
KCOL4
KCOL5
KROW0
KROW3
KROW1
KROW5
KROW2
KROW4
KROW6
KROW7
C174
SC33P50V2JN-3GP
C163
SC33P50V2JN-3GP
2
2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
2
1
KB1
29
C168
SC1U10V3KX-3GP
+5V_RUN
1
2
Internal KeyBoard Connector
C167
SCD1U16V2KX-3GP
+5V_RUN
AFTP161
AFTP163
AFTP165
1
1
1
6
ACES-CON4-10-GP-U
20.K0320.004
+5V_RUN
TPCLK
TPDATA
For EMS
<Core Design>
EC124
SC220P50V2KX-3GP
DY
Wistron Corporation
DY
2
EC126
SC220P50V2KX-3GP
DY
2
DY
EC128
SC220P50V2KX-3GP
EC130
SC220P50V2KX-3GP
DY
DY
2
DY
KROW7
KROW6
KROW5
KROW4
EC120
SC220P50V2KX-3GP
DY
EC113
SC220P50V2KX-3GP
EC111
SC220P50V2KX-3GP
DY
2
1
2
DY
KCOL16
EC118
SC220P50V2KX-3GP
EC123
SC220P50V2KX-3GP
DY
EC129
SC220P50V2KX-3GP
1
2
EC125
SC220P50V2KX-3GP
DY
KCOL15
KCOL14
KCOL13
KCOL12
EC115
SC220P50V2KX-3GP
DY
2
DY
EC119
SC220P50V2KX-3GP
EC121
SC220P50V2KX-3GP
EC114
SC220P50V2KX-3GP
DY
2
EC116
SC220P50V2KX-3GP
DY
DY
2
DY
KCOL7
KCOL6
KCOL5
KCOL4
KROW3
KROW2
KROW1
KROW0
EC127
SC220P50V2KX-3GP
EC112
SC220P50V2KX-3GP
DY
EC109
SC220P50V2KX-3GP
EC103
SC220P50V2KX-3GP
DY
2
DY
2
DY
2
KCOL11
KCOL10
KCOL9
KCOL8
EC105
SC220P50V2KX-3GP
EC102
SC220P50V2KX-3GP
DY
2
DY
EC107
SC220P50V2KX-3GP
EC104
SC220P50V2KX-3GP
DY
EC110
SC220P50V2KX-3GP
KCOL3
KCOL2
KCOL1
KCOL0
Title
KeyBoard/Touch Pad
Size
Document Number
Custom

5
Sheet
1
Rev
A00
Roberts
44
of
58
SSID = PWR.Support
R98
15KR2J-1-GP
D9
BAV99-4-GP
DY
+3.3V_ALW
1
PSID_DISABLE#_R
R99
+5V_ALW
E
1
2
R95
100KR2J-1-GP
I/O Board Connector
DY
R93
10KR2J-3-GP
CH3904PT-GP
Q7
B
D
+5V_ALW
PSID_DISABLE# 24
R91
D
PS_ID
D8
BAV99-4-GP
Q6
FDV301N-NL-GP
R90
2K2R2J-2-GP
0R2J-2-GP
PS_ID_EC 24
33R2J-2-GP
R92
1
CN4
+5V_USB1
20
20
MDI1+
MDI1-
24
USB_PP0
USB_PN0
USB_PP1
USB_PN1
MDI0+
MDI0+2.5V_LOM
1
IN
AD_OFF
16
16
16
16
3 OUT
R1
DY
R2
2 GND
DY
C379
SC10U25V6KX-1GP
1
2
1
2
Id=17A
Qg=100~150nC
Rdson=5.4~6.5mohm
Q16
Q5
C381
SCD01U50V2KX-1GP
GMCH_HSYNC 13
GMCH_VSYNC 13
DDC_DATA_CON 13
DDC_CLK_CON 13
DDC_DATA_CON
DDC_CLK_CON
AO4407A-GP
C380
SCD01U50V2KX-1GP
+5V_RUN
8
7
6
5
C332
SCD1U50V3KX-GP
D
D
D
D
DY
1
AFTP169
+DC_IN_SS
U46
S
S
S
G
C375
SCD01U50V2KX-1GP
13
1
2
3
4
R337
240KR3-GP
M_BLUE
M_BLUE
+DC_IN
M_GREEN
AFTP167
M_GREEN
PDTA124EU-1-GP
R336
47KR3J-L-GP
DDTC124EUA-7F-GP
20
20
13
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
55
56
C373
SC1U25V5KX-1GP
M_RED
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
NP2
54
M_RED
This cap should be used

only as last resort for
EMI suppression.
AFTP168
13
R1
DY
33R2J-2-GP
53
52
R2
51
NP1
+3.3V_RTC_LDO
2
USB Power
U9
1
2
3
4
24,43 USB_PWR_EN#
GND
OC1#
IN
OUT1
EN1/EN1# OUT2
EN2/EN2# OC2#
3
1
BAV99-4-GP
at least 80 mil
8
7
6
5
DY
G546B2P1UF-GP
USB_OC#0 16
USB_OC#1 16
at least 80 mil
BAT_SCL
+5V_USB1
D3
DY
2
+5V_ALW
EC84
SCD1U16V2KX-3GP
C33
SCD01U16V2KX-3GP
+5V_USB1
USB_PP0
USB_PN0
USB_PP1
USB_PN1
MDI1+
MDI1MDI0+
MDI0M_RED
M_BLUE
GMCH_VSYNC
DDC_DATA_CON
DDC_CLK_CON
M_GREEN
GMCH_HSYNC
+5V_RUN
+2.5V_LOM
1
C342
SCD01U16V2KX-3GP
+2.5V_LOM
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
TC18
ST100U6D3VBM-8GP
+5V_RUN
B
D2
AFTP170
AFTP173
AFTP172
AFTP174
AFTP171
AFTP176
AFTP175
AFTP177
AFTP178
AFTP179
AFTP181
AFTP180
AFTP182
AFTP183
AFTP185
AFTP184
AFTP186
AFTP187
ACES-CONN50A-GP
20.F1318.050
BAT_SDA
3
1
BAV99-4-GP
D1
2
BAT_IN#
3
1
BAV99-4-GP
Batt Connecter
AFTP188
AFTP189
AFTP191
AFTP190
BATT1
D18
2
PBAT_ALARM#
AFTP193
PBAT_PRES1#
PBAT_SMBDAT1
PBAT_SMBCLK1
R1
Place near DCIN1
+3.3V_RTC_LDO
+DC_IN
470KR2J-2-GP
2 100R2F-L1-GP-U
RN1
4
3
1
2 SRN100J-3-GP
BAT_IN# 24
BAT_SDA 24,26
BAT_SCL 24,26
R2
C325
SC2200P50V2KX-2GP
1 0R3-0-U-GP
<Core Design>
+PBATT
C326
SCD1U50V3KX-GP
Wistron Corporation
C330
SCD01U50V2KX-1GP

BATT_SENSE 26
Title
LEFT IO/DCIN/BATT CONN
Size
Document Number
Custom

5
BAV99-4-GP
PBAT_ALARM#
Reserved for EMI
R294
AFTP192
TYCO-CON9-1-GP
20.80959.009
PBAT_PRES1#
PBAT_SMBDAT1
PBAT_SMBCLK1
+PBATT
1
1
11
10
9
8
7
6
5
4
3
2
1
GND
GND
GND2
GND1
BAT_ALERT
SYS_PRES#
BATT_PRS#
DAT_SMB
CLK_SMB
BATT2+
BATT1+
1
1
1
1
Sheet
1
Rev
A00
Roberts
45
of
58
SSID = LOM
SSID = VIDEO
(Blanking)
<Core Design>
Wistron Corporation
Title
LAN CONNECTOR / CRT
Size
Document Number
Custom
Date: Tuesday, September 09, 2008

5
Sheet
1
Rev
A00
Roberts
46
of
58
SPR2
SPRING-24-GP
34.45T31.001
SPR3
SPRING-24-GP
34.45T31.001
1
SPR5
SPRING-58-GP
34.4B312.002
SPR4
SPRING-24-GP
34.45T31.001
SPR1
SPRING-24-GP
34.45T31.001
BOSS Placement
DY
DY
DY
DY
DY
DY
DY
DY
DY
DY
Spring
DY
DY
DY
DY
DY
Size
Document Number
Custom
DY
DY
Sheet
47
DY
Roberts
MISC
of
1
EC95
SCD1U16V2KX-3GP
EC100
SCD1U16V2KX-3GP
DY
1
EC91
SCD1U16V2KX-3GP
DY
EC131
SCD1U16V2KX-3GP
EC2
SCD1U16V2KX-3GP
EC89
SCD1U16V2KX-3GP
EC51
SCD1U16V2KX-3GP
EC138
SCD1U16V2KX-3GP
EC49
SCD1U16V2KX-3GP
EC94
SCD1U50V3KX-GP
EC1
SCD1U50V3KX-GP
EC13
SCD1U50V3KX-GP
EC97
SCD1U50V3KX-GP
C324
SCD1U50V3KX-GP
EC92
SCD1U50V3KX-GP
EC99
SC47P50V2JN-3GP
EC96
SCD1U16V2KX-3GP
EC53
SCD1U16V2KX-3GP
EC60
SCD1U16V2KX-3GP
DY
EC73
SCD1U16V2KX-3GP
1
EC108
SCD1U16V2KX-3GP
DY
DY
EC52
SCD1U16V2KX-3GP
EC66
SCD1U16V2KX-3GP
1
EC117
SCD1U16V2KX-3GP
DY
EC42
SCD1U16V2KX-3GP
DY
EC59
SCD1U16V2KX-3GP
1
EC106
SCD1U16V2KX-3GP
+1.8V_SUS
EC122
SCD1U16V2KX-3GP
DY
EC63
SCD1U16V2KX-3GP
DY
EC67
SCD1U16V2KX-3GP
DY
EC98
SCD1U16V2KX-3GP
DY
EC72
SCD1U16V2KX-3GP
DY
EC148
SCD1U16V2KX-3GP
EC71
SCD1U16V2KX-3GP
DY
EC55
SCD1U16V2KX-3GP
DY
DY
EC152
SCD1U16V2KX-3GP
EC46
SCD1U16V2KX-3GP
EC9
SCD1U16V2KX-3GP
DY
EC136
SCD1U16V2KX-3GP
+PWR_SRC
EC153
SCD1U16V2KX-3GP
DY
DY
EC149
SCD1U16V2KX-3GP
DY
EC68
SCD1U16V2KX-3GP
EC47
SCD1U16V2KX-3GP
DY
DY
EC141
SCD1U16V2KX-3GP
DY
EC50
SCD1U16V2KX-3GP
1
EC44
SCD1U16V2KX-3GP
EC64
SCD1U16V2KX-3GP
DY
DY
EC11
SCD1U16V2KX-3GP
1
EC45
SCD1U16V2KX-3GP
EC93
SC47P50V2JN-3GP
DY
EC86
SCD1U16V2KX-3GP
+3.3V_RUN
1
EC43
SCD1U16V2KX-3GP
DY
EC10
SCD1U16V2KX-3GP
EC88
SCD1U16V2KX-3GP
DY
DY
EC90
SCD1U16V2KX-3GP
+5V_RUN
EC58
SCD1U16V2KX-3GP
DY
DY
EC82
SCD1U16V2KX-3GP
EC34
SCD1U16V2KX-3GP
+0.9V_DDR_VTT
EC159
SCD1U16V2KX-3GP
EC150
SCD1U16V2KX-3GP
1
EC41
SCD1U16V2KX-3GP
+DC_IN_SS
EC174
SCD1U25V2ZY-1GP
34.4W001.001
NB Thermal BOSS
DY
EC170
SCD1U25V2ZY-1GP
2
1
H19
HOLE
DY
DY
DY
DY
DY
EC172
SCD1U25V2ZY-1GP
For TP button holder touch.
DY
DY
SCD1U16V2KX-3GP
2
EC101
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
DY2
2
DY
+3.3V_ALW
EC137
SCD1U16V2KX-3GP
EC169
1
SCD1U16V2KX-3GP
2
EC85
SCD1U16V2KX-3GP
+5V_ALW
DY
H1
HOLE
H20
HOLE355X355R111-S1-GP
EC168
1
DY
DY
EC166
SCD1U16V2KX-3GP
EC167
1
DY
34.4W004.001
New Card BOSS
1
+5V_MOD
DY
EC171
SCD1U25V2ZY-1GP
H16
HOLE
DY
EC83
SCD1U16V2KX-3GP
H8
HOLE
H17
H15
HOLE355X355R111-S1-GP HOLE355X355R111-S1-GP
EC81
SCD1U16V2KX-3GP
+5V_ALW
H14
HOLE
EC165
SCD1U16V2KX-3GP
EC173
SCD1U25V2ZY-1GP
DY
DY
SW1
SPRING-24-GP
+3.3V_RUN
H7
HOLE
H4
H13
EC164
SCD1U25V2ZY-1GP
DY
H10
H5
EC163
SCD1U25V2ZY-1GP
24,41 BLUETOOTH_EN
37,41 WLAN_ACT
37,41
BT_ACT
DY
34.4W005.001
Mini Card BOSS
1
H2
HOLE
DY
H6
HOLE
DY
EC151
SCD1U16V2KX-3GP
DY
H3
HOLE
1
EC162
SCD1U25V2ZY-1GP
DY
H9
H11
2
EC54
SCD1U16V2KX-3GP
DY
H12
H18
+3.3V_RTC_LDO
DY
5
1
SSID = Mechanical
+1.05V_VCCP
+3.3V_RUN
C
C
+5V_RUN
+3.3V_RUN
B
+PWR_SRC
<Core Design>
A
Wistron Corporation

Title
Rev
58
A00
Adapter
+PWR_SRC
TPS51116
ISL6266AHRZ
TPS5117
+1.8V_SUS
LDO
P2003EVG
Charger
+VCC_CORE
MAX8731A
Battery
+1.05V_VCCP
APL5912
+V_DDR_MCH_REF
+PBATT
+0.9V_DDR_VTT
+1.5V_RUN
MAX17020
+5V_ALW2
+5V_ALW
G577BR91U
+3.3V_ALW
+1.5V_CARD
G9091
+3.3V_RTC_LDO
G546B2P1UF
AO4468
RT9711BPF
AO4468
G577BR91U
AO3403
+5V_USB1
+5V_RUN
+5V_USB2
+3.3V_RUN
+3.3V_CARDAUX
+3.3V_LAN
88E8040
G9091
MAX9789A
FDC655BN
SI4800BDY
G5281RC1U
G577BR91U
RTS5158E
+3.3V_CRT_LDO
+VDDA
+5V_HDD
+5V_MOD
+LCDVDD
+3.3V_CARD
+3.3V_RUN_CARD
+2.5V_LOM
+1.2V_LOM
Power Shape
Regulator
LDO
Switch
<Core Design>
Wistron Corporation
Title
Power Block Diagram
Size
Document Number
Custom

5
Sheet
1
Rev
A00
Roberts
48
of
58
ICH9M SMBus Block Diagram
KBC SMBus Block Diagram

+5V_RUN
SRN10KJ-5-GP
TouchPad Conn.
+3.3V_ALW
PSDAT1
TPDATA
PSCLK1
TPCLK
+3.3V_RUN
TPDATA
TPDATA
TPCLK
TPCLK
+3.3V_RTC_LDO
+3.3V_RUN
SRN2K2J-1-GP
SRN2K2J-1-GP
ICH9M
SMBCLK
SMBDATA
SMB_CLK
SMB_DATA
SRN4K7J-8-GP
DIMM 1
ICH_SMBDATA
ICH_SMBCLK
SCL
Battery Conn.
SRN100J-3-GP
SCL1 BAT_SCL
SDA
SDA1 BAT_SDA
SMBus Address:A0
PBAT_SMBCLK1
CLK_SMB
PBAT_SMBDAT1
DAT_SMB
SMBus address:16
2N7002SPT
DIMM 2
ICH_SMBCLK
ICH_SMBDATA
SCL
SDA
MAX8731
KBC
SCL
SMBus address:12
SDA
SMBus Address:A4
WPC773L
Express
Card
SMB_CLK
SMB_DATA
SMB_CLK
SMB_DATA
+3.3V_RUN
Clock
Generator
ICH_SMBCLK
ICH_SMBDATA
+3.3V_RTC_LDO
+3.3V_RUN
SCLK
SRN4K7J-8-GP
SDATA
SMBus address:D2
ICH_SMBCLK
ICH_SMBDATA
Minicard
WLAN
SMB_CLK
GPIO61/SCL2
KBC_SCL1
GPIO62/SDA2
KBC_SDA1
Thermal
SRN4K7J-8-GP
THERM_SCL
SCL
THERM_SDA
SDA
SMBus address:7A
2N7002DW-1-GP
SMB_DATA
0R2J-2-GP
Capacity
Button
0R2J-2-GP
SMBus address:86
+3.3V_RUN
SRN2K2J-1-GP
LDDC_CLK
LDDC_CLK
LDDC_DATA
LDDC_DATA
LCD Conn.
+3.3V_RUN
+5V_CRT_RUN
+3.3V_RUN
SRN2K2J-1-GP
CTRL_DDC_CLK
GMCH_DDCCLK
CTRL_DDC_DATA
GMCH_DDCDATA
2N7002DW-1-GP
Charger Board CONN.
GMCH
SRN2K2J-1-GP
DDC_CLK_CON
DDC_DATA_CON
CRT CONN
4
<Core Design>
Wistron Corporation
Title
Size
C
Date:
SMBUS Block Diagram
Document Number
Sheet
E
Rev
A00
Roberts
Thursday, October 02, 2008
49
of
58
Thermal Block Diagram
Audio Block Diagram
SPEAKER
OUTR+
OUTROUTLOUTL+
PORT_D_L
SPKR_INL
PORT_D_R
SPKR_INR
MAX9789A
CPU
DP1
H_THERMDA
DN1
H_THERMDC
DP2
EMC2102_DP2
HP_INL
HPL
PORT_A_R
HP_INR
HPR
HP
OUT
THRMDA
SC470P50V3JN-2GP
PORT_A_L
Codec
92HD71B7
THRMDC
Thermal
EMC2102
MIC
IN
PORTB_L
PORTB_R
MMBT3904-3-GP
VREFOUT_B
SC470P50V3JN-2GP
DN2
EMC2102_DN2
System sensor, put

between CPU and NB.
Digital
MIC
Array
DMIC_CLK
VOL_UP/DMIC_0/GPIO1
DP3
EMC2102_DP3
DN3
EMC2102_DN3
MMBT3904-3-GP
SC470P50V3JN-2GP
PORTC_L
Place near the CPU

and GMCH.
PORTC_R
VREFOUT_C
Analog
MIC
<Core Design>
Wistron Corporation
Title
Thermal/Audio Block Diagram
Size
Document Number
Custom

A
Sheet
E
Rev
A00
Roberts
50
of
58
(Blanking)
<Core Design>
Wistron Corporation
Title
Size
Document Number
Custom
VGA-PCIE(1/4)

5
Rev
A00
Roberts
Sheet
1
51
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58
(Blanking)
<Core Design>
Wistron Corporation
Title
VGA-VRAM(2/4)
Size
Document Number
Custom

5
Rev
A00
Roberts
Sheet
1
52
of
58
(Blanking)
<Core Design>
Wistron Corporation
Title
VGA-HDMI/STRAP(3/4)
Size
Document Number
Custom

5
Sheet
1
Rev
A00
Roberts
53
of
58
(Blanking)
<Core Design>
Wistron Corporation
Title
VGA-LVDS/TV/CRT/(4/4)
Size
Document Number
Custom

5
Sheet
1
Rev
A00
Roberts
54
of
58
(Blanking)
<Core Design>
Wistron Corporation
Title
VRAM
Size
Document Number
Custom
5
Rev
A00
Roberts
Sheet
1
55
of
58
DATE
VERSON
06/03
D
NO
PAGE
Modified List
06/10
C
06/12
06/16
Issue Description
CN4 Pin.51 from +DC_IN change to GND.
CN4 Pin.51 should be ground.
24
Dummy R422
LID SW is push-pull type, no need pull high.
EE
41
CAMERA1 conn reduce from 10 to 8 pin.
Follow camera design.
EE
06/19
EE
42
RTC1 CONN change p/n: 22.70031.001 to 62.70001.011.
Qty issue to change another.
EE
46
Exchange H14 and H6 names.
Correction. H14 for mini card boss ; H6 is hole.
EE
42
Reverse LED1.
Correction. Amber for BAT_LED_B ; White for PWR_LED_B.
EE
37,41
Remove CN5 and related circuit in page.41.

Add dummy R: R493, R494, R495, R496, R497, R498, R499
Remove debug board connector.

For debug mini card, change LPC Bus to mini card base.
Set dummy res to avoid damaging MB or additional mini card.
EE
37
Dummy R210, R211
For debug mini card.

Set dummy res to avoid damaging MB or additional mini card.
PCB Version for SB.
EE
24
Dummy R150. Staff R151.
10
42
CN1 Pin.2 set to NC.
11
24
Add R500 and dummy EC161.
Dummy R406.
Change R425, R422, R409, R406, R401, R404 to 100K ohm.
Update HDD symbol.
EE
EE
Change All TP near connectors to AFTP (ZZ.AFT30.101).
For AFTE test pad.
EE
EE
36
13
35~45
14
04
Change C461 and C462 from 15pF to 12pF.
For X3 cap choice by report suggestion.
EE
15
17
Change C520 and C522 from 15pF to 12pF.
For X4 cap choice by report suggestion.
EE
16
24,42
Add 0 ohm R482 on EC_SPI_WP# and link to KBC/GPIO30.

Change RN50 to 100k and Add R476 for EC_SPI_WP#.
KBC can control WP# of Flash ROM.

R change to 100k for save power.
EE
17
40
Change L19 and L20 to 68.00082.531.
For EMI.
EE
18
45
Avoiding noise to impact CRT signals.
EE
19
47
Change M_RED to CN4 Pin.17 ; M_GREEN to CN4

CN4 Pin.23 and Pin.27 to GND.
Add H20.
Add square GND for TP button holder touch.
EE
20
42
Dummy CN2, R34.
Cap. button function is disable.
EE
21
47
Add dummy EC162, EC163, EC164.

Add dummy EC165, EC166.
Add dummy EC167, EC168, EC169.
For EMI.
EE
22
04
Change R216 to 22 ohm.
The same clock dirve to U25 and U34.
EE
23
44
Dummy EC110, EC104, EC107, EC102, EC105, EC103, EC109, EC112, EC127, EC125,
EC129, EC123, EC118, EC116, EC114, EC121, EC119, EC115, EC111, EC113, EC120,
EC130, EC128, EC126, EC124.
For EMI.
EE
24
43
Short R26, R27.
No need 0 ohm R.
EE
25
47
Add SW1.
ME request.
EE
26
35
LCD1.38 link to GFX_PWR_SRC ; LCD1.37 set NC ; LCD1.35 link to +LCDVDD ;

LCD1.34 link to +3.3V_RUN ; LCD1.33 link to LCD_BRIGHTNESS ; LCD1.32 to GND ;
LCD1.31 link to LCD_CBL_DET#.
For LED backlight panel.
EE
27
18
Dummy R179, R423.
SW check vender ID by SMBus.
EE
28
24
Dummy R416, R418.
Cap. button function is disable.
EE
29
40
30
17,18
Pin.21 ; M_BLUE to CN4 Pin.25.
EE
Avoid shorting between KBC_PWRBTN# and GND.

New R and C are for EMC pre-location.
Dummy R406 for no keyboard detect function.
R change to 100k for save power.
Update symbol and footprint for only SATA HDD. (no co-layout)
12
06/18
OWNER
45
X01
06/17
06/05
06/06
Change LOUT1 and MIC1 to 22.10133.D01.
Change jack source.
EE
Avoiding abnormal action in U25(ICH9-M).
EE
For T8 shutdown is set 88 deg-C.
EE
31
25
Dummy U25.B10 link R506 to GND; U25.C18 link R501 to GND;

Dummy U25.C21 link R502 to GND; U25.C11 link R503 to GND;
Dummy U25.AE18 link R504 to GND; U25.AF21 link R505 to GND.
Dummy R421, R424.
Change R82 to 20K 1% ; Change R78 to 10K 1%.
06/23
32
47
Add dummy EC170, EC171, EC172, EC173, EC174.
For EMI.
EE
06/27
33
42
Change U23 to 72.25X16.A01.
Better performance.
EE
<Core Design>
Wistron Corporation
Title
Size
A3
Change List - EE (1/2)
Document Number

5
Sheet
1
Rev
A00
Roberts
56
of
58
DATE
VERSON
PAGE
34
18
Staff R421, R424. (PT build cut-in)
Avoiding always issue interrupt event.
EE
35
23
Dummy R290 ; Staff R291. (PT build cut-in)
Adjust audio amp. gain value.
EE
36
20
Add dummy R507.
Add RUN power for LAN.
EE
37
21
Short R253, R254.
No need 0 ohm R.
EE
38
24
Staff R138, R150 ; Dummy R141, R151.
PCB Version for SC.
EE
39
35
Add R508 ; Change R359 to 49.9k ohm.
For LCD power sequence.
EE
22,23
Move C535 (Change 0.033uF), R472 to page.23.

Remove C536 (Change 0.033uF), C542.
Add R484 to gnd ; Add C566 for AUD_SET, C567 for AUD_BIAS.
C565 for 6040 only.
For PC beep.
40
41
36
Material change: HDD1
ME request.
EE
42
37
Material change: CARD1
ME request.
EE
43
47
Material change: SPR4
ME request.
EE
44
09
Add TP271 for U52/ SDVO_CTRLDATA.
TP.
EE
45
41
Short R79, R80.
No need 0 ohm R.
EE
46
04
Symbol change: U54.
For clock generator co-layout.
EE
47
Change to close line:

R204, R200, R356, R139, R152, R408, R394, R390, R403, R402, R96, R120, R378,
R360, R140, R373, R97, R405, R155, R154, R262, R266, R439, R265, R226, R269,
R174, R175, R183, R432, R433, R434, R430, R431, R437, R191, R177, R270, R188,
R436, R452, R259, R282, R250, R249, R467, R153, R81, R77.
No need 0 ohm R.
EE
08/06
C
Modified List
NO
07/30
X02
Issue Description
OWNER
EE
48
24,32
Move R182 to page.24.
Movement.
EE
49
37
Short R428, R426 ; Add DY L21.
Pre-location for Minicard USB trace.
EE
50
Short R139, R96 , R155, R154, R226, R174, R175, R432, R433.
No need 0 ohm R.
EE
51
19
Staff C488.
For DMI.
EE
52
23
Use 2.2uF C564 and C557 for Maxim U62 IC.
For improving bobo sound.
EE
08/11
53
32
Material change: TC23. (DY)
Material issue.
EE
08/15
54
11
Material change: TC19, TC21.
Material issue.
EE
55
21
USB_PP10 for U34.5 ; USB_PN10 for U34.4. (ST build cut-in)
Schematic modification.
EE
56
24
Staff R151 ; Dummy R150.
PCB Version for -1(Xbuild).
EE
57
24
Add dummy R509 to gnd for KBC GPIO24. (09/10 update)
For GM45.
EE
58
05,17
Dummy R76 ; Staff R167
For H_THRMTRIP# to SB.
EE
59
12,20,
24
37

R115, R246, R182, R158, R159, R170.
Remove L21.
No need 0 ohm R.
EE
08/07
09/02
09/03
A00
No need L21.
EE
61
19
Staff R453, C511 ; DY C521.
Follow Intel DG 2.0.
EE
62
04
Short RN42, RN43, RN44, RN45, RN48, RN22, RN23, RN54, RN53, RN52, RN51.
No need 0 ohm R.
EE
63
21
For U34 power bounce issue.
EE
64
04
Add dummy R510 and C568.

Staff R282 0 ohm.
Dummy R196.
For debug. Normally, no need it.
EE
65
25
R82 change to 10k ; R78 change to 2.37k.
For T8 thermal shutdown setting.
EE
66
23
Staff R288 ; Dummy R289.
For Audio amp. gain.
EE
67
21
Dummy R284, C318.

Staff R282 to Bead 68.00082.531.
Staff R510 to 2.2K ; Staff C568.
For U34 power bounce issue.
EE
60
09/09
09/10
09/22
10/02
<Core Design>
Wistron Corporation
Title
Size
A3
Change List - EE (2/2)
Document Number

5
Sheet
1
Rev
A00
Roberts
57
of
58
DATE
VERSON
06/03
NO
PAGE
32
2
3
Modified List
Issue Description
06/10
06/18
06/23
3
07/30
08/11
09/03
X02
OWNER
For +1.5V_RUN sequence.
Power EE
30
C378 change to 0.01uF.
For +1.05V_VCCP sequence.
Power EE
34
C316 change from 4.7nF to 0.01uF.
Power EE
34
Staff C314 and change from 4.7nF to 6.8nF.
36
Dummy Q20, U57, R462, R457, C527 and U58, U28, R251, R252, C293, C295
Change R258, R256 to G81, G82
Change R278, R279, R277, R276 to G83, G84, G85, G86
For +3.3V_RUN sequence and improve +3.3V_ALW voltage drop

due to SW(U31) turn on quickly (higher loading).
For +5V_RUN sequence and improve +5V_ALW voltage drop
due to SW(U30) turn on quickly (higher loading).
No sniffer function, no control HDD & ODD power.
27
R136 change to 270k and R108 change to 237k
For 5V/3.3V OCP
Power EE
28
31
R38 change to 12.1k

R323 change to 3.92k , C360 change to 0.047 uF 10V X7R
PC9 to GND.
06/05
X01
R189 change to 2.2K ohm, C216 dummy.
06/06
Power EE
4
Power EE
31
PR2 change to 9.31k ohm.
R38 for VCORE OCP

R323 and C360 for transient and load line.
PC9 to GND otherwise DC-DC IC can not obtain power to
generate 1.8V/0.9V output.
For 1.8V OCP.
10
30
Add D23.
For power sequence.
Power EE
11
18,24
Remove U60, R482, R476 and change trace name VRMPWRGD to VGATE_PWRGD.
For power sequence.
Power EE
12
31
PR7.1 link to +5116_PWR_SRC.
Reserve for other source.
Power EE
13
30
Rename "+1.05V_SUSP" to "+1.05V_RUNP"
Correct naming.
Power EE
14
26,45
Material change: U37, U46, U47.
NIKO-SEM P2003EVG component has some risk.
Power EE
15
31
Change PR7 value from 622k to 619k ohm.
For 2nd source.
Power EE
16
26,45
Material change: U37, U46, U47.
Power team request.
Power EE
17
26,27,
28,31

R46 ,R137 ,R127,R106 ,R384 ,R391 ,R35 ,R29 ,R307 ,R308 ,R309 ,R303 ,R304 ,
R298 ,R301 ,R310 ,R313 ,PR14.
No need 0 ohm R.
Power EE
26
R61 change 4.7k to 10k.
Power team request.
Power EE
23
Power EE
24
Power EE
25
Power EE
A00
18
Power EE
Power EE
Power EE
xx
19
20
xx
21
22
xx
xx
<Core Design>
Wistron Corporation
Title
Size
A3
Change List - Power
Document Number

A
Rev
A00
Roberts
Sheet
E
58
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58

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5

DR1 (Roberts) Schematics Document

Date: Thursday, October 02, 2008

Roberts Block Diagram

Project code : 91.4AQ01.001

Intel Mobile CPU

DDRII 667/800 Channel A

AGTL+ CPU I/F

DDR Memory I/F

DDR II 667/800 Channel B

PCIE x 1 & USB 2.0 x 1

Digital Mic Array

SATA ports (4)

Internal Analog MIC

PCI Express ports (6)

High Definition Audio

USB 2.0/1.1 ports (12)

Thermal & Fan

Date: Thursday, October 02, 2008

ICH9M Functional Strap Definitions

ICH9 EDS 642879

Montevina Platform Design guide 22339 Rev.0.5

FSB Frequency Select 000 = FSB1067

XOR Chain Entrance/

PCIE config1 bit0,

iTPM Host Interface

0 = The iTPM Host Interface is enabled (Note 2)

0 = Transport Layer Security (TLS) cipher

PCIE Graphics Lane

The pull-up or pull-down

0 = Reserved Lanes, 15->0, 14->1 ect..

PCIE Loopback enable 0 = Enable (Note 3)

This signal has a weak internal pull-down.

PCIE config2 bit2,

This signal has a weak internal pull-up.

This signal should not be pulled high.

Sampled low: Top-Block Swap mode (inverts A16 for

Boot BIOS Destination

Cantiga chipset and ICH9M I/O controller

ICH9 EDS 642879

ICH9 Integrated pull-up

Controllable via Boot BIOS Destination bit

The signal is required to be low for desktop

PCI Express Lane

Signal has weak internal pull-up. Sets bit 27

If sampled high, the system is strapped to the

XOR Chain Entrance.

This signal should not be pull low unless using

FSB Dynamic ODT

0 = Dynamic ODT Disabled

DMI Lane Reversal

0 = Normal operation (Default): Lane Numbered in

Digital Display Port 0 = Only Digital Display Port or PCIE is

0 = No SDVO Card Present (Default)

Date: Thursday, October 02, 2008

Main source: 71.08513.003 (SLG8SP513VTR)

Overclocking of CPU and SRC allowed

Overclocking of CPU and SRC not allowed

SEL2 SEL1 SEL0

Clock Generator SLG8SP513VTR

Date: Thursday, October 02, 2008

H_THERMDA, H_THERMDC routing together,

H_THRMTRIP# should connect to

Date: Thursday, October 02, 2008