dsk6416 TechRef

TMS320C6416T DSK Technical Reference
2004
DSP Development Systems
TMS320C6416T DSK Technical Reference
508035-0001 Rev. A November 2004
SPECTRUM DIGITAL, INC. 12502 Exchange Drive, Suite 440 Stafford, TX. 77477 Tel: 281.494.4505 Fax: 281.494.5310 sales@spectrumdigital.com www.spectrumdigital.com
IMPORTANT NOTICE Spectrum Digital, Inc. reserves the right to make changes to its products or to discontinue any product or service without notice. Customers are advised to obtain the latest version of relevant information to verify that the data being relied on is current before placing orders. Spectrum Digital, Inc. warrants performance of its products and related software to current specifications in accordance with Spectrum Digitals standard warranty. Testing and other quality control techniques are utilized to the extent deemed necessary to support this warranty. Please be aware that the products described herein are not intended for use in life-support appliances, devices, or systems. Spectrum Digital does not warrant nor is Spectrum Digital liable for the product described herein to be used in other than a development environment. Spectrum Digital, Inc. assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or services described herein. Nor does Spectrum Digital warrant or represent any license, either express or implied, is granted under any patent right, copyright, or other intellectual property right of Spectrum Digital, Inc. covering or relating to any combination, machine, or process in which such Digital Signal Processing development products or services might be or are used. WARNING This equipment is intended for use in a laboratory test environment only. It generates, uses, and can radiate radio frequency energy and has not been tested for compliance with the limits of computing devices pursuant to subpart J of part 15 of FCC rules, which are designed to provide reasonable protection against radio frequency interference. Operation of this equipment in other environments may cause interference with radio communications, in which case the user at his own expense will be required to take whatever measures necessary to correct this interference.
Copyright 2004 Spectrum Digital, Inc.
Contents
Introduction to the TMS320C6416T DSK Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Provides you with a description of the TMS320C6416T DSK Module, key features, and block diagram. 1.1 Key Features .......................................................... 1.2 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 Basic Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 Configuration Switch Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.6 Power Supply ......................................................... 2 Board Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Describes the operation of the major board components on the TMS320C6416T DSK. 2.1 CPLD (programmable Logic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.1 CPLD Overview .................................................... 2.1.2 CPLD Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.3 USER_REG Register .............................................. 2.1.4 DC_REG Register .................................................. 2.1.5 Version Register .................................................. 2.1.6 MISC Register ..................................................... 2.2 Codec Interface ..................................................... 2.3 SRAM Interface ..................................................... 2.4 Flash ROM Interface ................................................ 2.5 LEDs and DIP Switches .............................................. 2.6 Daughter Card Interface .............................................. 2.7 CPU and EMIFA Clcok Generation ..................................... 3 Physical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Describes the physical layout of the TMS320C6416T DSK and its connectors. 3.1 Board Layout ........................................................ 3.2 Connector Index .................................................... 3.3 Expansion Connectors ................................................ 3.3.1 J4, Memory Expansion ............................................. 3.3.2 J3, Peripheral Expansion ............................................ 3.3.3 J1, HPI Expansion Connector ........................................ 3.4 Audio Connectors ..................................................... 3.4.1 J301, Microphone Connector ......................................... 3.4.2 J303, Audio Line In Connector ........................................ 3.4.3 J304, Audio Line Out Connector ...................................... 3.4.4 J302, Headphone Connector .......................................... 3.5 Power Connectors ..................................................... 3.5.1 J5, +5V Main Power Connector ....................................... 3.5.2 J6, Optional Power Connector .........................................
1-1
1-2 1-3 1-4 1-5 1-6 1-7 2-1 2-2 2-2 2-3 2-3 2-4 2-4 2-5 2-6 2-7 2-7 2-7 2-8 2-8 3-1 3-2 3-3 3-3 3-4 3-5 3-6 3-7 3-7 3-7 3-8 3-8 3-9 3-9 3-9
A B
3.6. Miscellaneous Connectors ........................................... 3.6.1 J201, USB Port .................................................... 3.6.2 J8, External JTAG Connector ........................................ 3.6.3 JP3, PLD Programming Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7 System LEDs ....................................................... 3.8 Reset Switch ....................................................... Schematics .............................................................. Contains the schematics for the TMS320C6416T DSK Mechanical Information .................................................. Contains the mechanical information about the TMS320C6416T DSK
3-10 3-10 3-10 3-11 3-11 3-11 A-1 B-1
About This Manual This document describes the board level operations of the TMS320C6416T DSP Starter Kit (DSK) module. The DSK is based on the Texas Instruments TMS320C6416T Digital Signal Processor. The TMS320C6416T DSK is a table top card to allow engineers and software developers to evaluate certain characteristics of the TMS320C6416T DSP to determine if the processor meets the designers application requirements. Evaluators can create software to execute onboard or expand the system in a variety of ways. Notational Conventions
This document uses the following conventions. The TMS320C6416T DSK will sometimes be referred to as the DSK, C6416T DSK, or TMS320C6416 DSK. Program listings, program examples, and interactive displays are shown is a special italic typeface. Here is a sample program listing. equations !rd = !strobe&rw;
Information About Cautions This book may contain cautions. This is an example of a caution statement. A caution statement describes a situation that could potentially damage your software, or hardware, or other equipment. The information in a caution is provided for your protection. Please read each caution carefully. Related Documents Texas Instruments TMS320C64xx DSP CPU Reference Guide Texas Instruments TMS320C64xx DSP Peripherals Reference Guide
Table 1: Manual History Revision A Initial Release History
Chapter 1 Introduction to the TMS320C6416T DSK
Chapter One provides a description of the TMS320C6416T DSK along with the key features and a block diagram of the circuit board.
Topic
1.1 1.2 1.3 1.4 1.5 1.6 Key Features Functional Overview Basic Operation Memory Map Configuration Switch Settings Power Supply
Page
1-2 1-3 1-4 1-5 1-6 1-7
1-1
Spectrum Digital, Inc

1.1 Key Features The C6416T DSK is a low-cost standalone development platform that enables users to evaluate and develop applications for the TI C64xx DSP family. The DSK also serves as a hardware reference design for the TMS320C6416T DSP. Schematics, logic equations and application notes are available to ease hardware development and reduce time to market.
LINE OUT HP OUT LINE IN MIC IN
Memory Exp McBSPs EMIFA EMIFB

8 8 64 32
JP2 3.3V
JTAG Voltage Reg

JP4 5V
MUX
6416T DSP
HPI
ENDIAN BOOTM 1 BOOTM 0 SPARE PLL_SEL1 PLL_SEL2 PLL_SEL3 PLL_SEL4
Embedded JTAG Ext. JTAG
Peripheral Exp
PWR
USB
Config SW3
LED
0123
SDRAM DIP
JP1 1.2V
1 2 3 4 5 6 7 8
0123
Figure 1-1, Block Diagram C6416T DSK The DSK comes with a full compliment of on-board devices that suit a wide variety of application environments. Key features include: A Texas Instruments TMS320C6416T DSP operating at 1 Gigahertz. An AIC23 stereo codec 16 Mbytes of synchronous DRAM 512 Kbytes of non-volatile Flash memory 4 user accessible LEDs and DIP switches Software board configuration through registers implemented in CPLD Configured boot options and clock input selection Standard expansion connectors for daughter card use JTAG emulation through on-board JTAG emulator with USB host interface or external emulator Single voltage power supply (+5V) 1-2 TMS320C6416T DSK Module Technical Reference
Host Port Int
AIC23 Codec
MUX
CPLD
Flash

1.2 Functional Overview of the TMS320C6416T DSK The DSP on the 6416T DSK interfaces to on-board peripherals through one of two busses, the 64-bit wide EMIFA and the 8-bit wide EMIFB. The SDRAM, Flash and CPLD are each connected to one of the busses. EMIFA is also connected to the daughter card expansion connectors which is used for third party add-in boards. An on-board AIC23 codec allows the DSP to transmit and receive analog signals. McBSP1 is used for the codec control interface and McBSP2 is used for data. Analog I/O is done through four 3.5mm audio jacks that correspond to microphone input, line input, line output and headphone output. The codec can select the microphone or the line input as the active input. The analog output is driven to both the line out (fixed gain) and headphone (adjustable gain) connectors. McBSP1 and McBSP2 can be re-routed to the expansion connectors in software. A programmable logic device called a CPLD is used to implement glue logic that ties the board components together. The CPLD also has a register based user interface that lets the user configure the board by reading and writing to the CPLD registers. The DSK includes 4 LEDs and 4 position DIP switch as a simple way to provide the user with interactive feedback. Both are accessed by reading and writing to the CPLD registers. An included 5V external power supply is used to power the board. On-board switching voltage regulators provide the 1.2V DSP core voltage and 3.3V I/O supplies. The board is held in reset until these supplies are within operating specifications. A separate regulator powers the 3.3V lines on the expansion interface. Code Composer communicates with the DSK through an embedded JTAG emulator with a USB host interface. The DSK can also be used with an external emulator through the external JTAG connector.
1-3

1.3 Basic Operation The DSK is designed to work with TIs Code Composer Studio development environment and ships with a version specifically tailored to work with the board. Code Composer communicates with the board through the on-board JTAG emulator. To start, follow the instructions in the Quick Start Guide to install Code Composer. This process will install all of the necessary development tools, documentation and drivers. After the install is complete, follow these steps to run Code Composer. The DSK must be fully connected to launch the DSK version of Code Composer. 1) Connect the included power supply to the DSK. 2) Connect the DSK to your PC with a standard USB cable (also included). 3) Launch Code Composer from its icon on your desktop. Detailed information about the DSK including a tutorial, examples and reference material is available in the DSKs help file. You can access the help file through Code Composers help menu. It can also be launched directly by double-clicking on the file c6416Tdsk.hlp in Code Composers docs\hlp subdirectory.
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TMS320C6416T DSK Module Technical Reference

1.4 Memory Map The C64xx family of DSPs has a large byte addressable address space. Program code and data can be placed anywhere in the unified address space. Addresses are always 32-bits wide. The memory map shows the address space of a generic 6416T processor on the left with specific details of how each region is used on the right. By default, the internal memory sits at the beginning of the address space. Portions of memory can be remapped in software as L2 cache rather than fixed RAM. Each EMIF (External Memory Interface) has 4 separate addressable regions called chip enable spaces (CE0-CE3). The SDRAM occupies CE0 of EMIFA while the CPLD and Flash are mapped to CE0 and CE1 of EMIFB respectively. Daughter cards use CE2 and CE3 of EMIFA.
Address
0x00000000
Generic 6416 Address Space Internal Memory
6416 DSK Internal Memory Reserved or Peripheral CPLD Flash
0x00100000
Reserved Space or Peripheral Regs

0x60000000
EMIFB CE0
0x64000000 0x68000000
EMIFB CE1 EMIFB CE2
0x6C000000
EMIFB CE3
0x80000000
EMIFA CE0
0x90000000 0xA0000000
SDRAM
EMIFA CE1 EMIFA CE2
0xB0000000
EMIFA CE3
Daughter Card
Figure 1-2, Memory Map, C6416T DSK
1-5

1.5 Configuration Switch Settings The DSK has 8 configuration switches that allows users to control the operational state of the DSP when it is released from reset. The configuration switch block is labeled SW3 on the DSK board, next to the reset switch. Configuration switch 1 controls the endianness of the DSP while switches 2 and 3 configure the boot mode that will be used when the DSP starts executing. Position 4 on SW3 is a spare. Positions 5-8 on SW3 control the CPU and EMIFA clocking frequencies. By default all switches are off which corresponds to EMIFB boot (out of 8-bit Flash) in little endian mode at 1 gigahertz CPU frequency and 125 Mhz. EMIFA frequency. The following 2 tables show these settings. Table 1: Boot/Endian Configuration Switch Settings SW3-4 * x x x x x x * SW3-4 is spare ** Default SW3-3 Off Off On On SW3-2 Off On Off On Off On SW3-1 Configuration Description EMIF boot from 8-bit Flash ** No Boot Reserved HPI boot Little endian ** Big endian
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The following table shows the switch position settings for desired CPU and EMIFA frequencies. Table 2: CPU and EMIFA Frequency Configuration Switch Settings SW3-8 Off Off Off Off Off Off Off Off On On On On On On On On SW3-7 Off Off Off Off On On On On Off Off Off Off On On On On SW3-6 Off Off On On Off Off On On Off Off On Off Off On On On SW3-5 Off On Off On Off On Off On Off On Off On Off On Off On CPU Frequency 1 Ghz. Reserved Reserved 720 Mhz. 850 Mhz. Reserved Reserved 1.2 Ghz. Reserved 500 Mhz. 600 Mhz. Reserved Reserved Reserved Reserved Reserved EMIFA Frequency 125 Mhz. ** Reserved Reserved 125 Mhz. 125 Mhz. Reserved Reserved 125 Mhz. Reserved 100 Mhz. 100 Mhz. Reserved Reserved Reserved Reserved Reserved
** Default 1.6 Power Supply The DSK operates from a single +5V external power supply connected to the main power input (J5). Internally, the +5V input is converted into +1.2V and +3.3V using a dual voltage regulator. The +1.2V supply is used for the DSP core while the +3.3V supply is used for the DSP's I/O buffers and all other chips on the board. The power connector is a 2.5mm barrel-type plug. There are three power test points on the DSK at JP1, JP2 and JP4. All 6416T I/O current passes through JP2 while all core current passes through JP1. All system current passes through JP4. Normally these jumpers are closed. To measure the current passing through remove the jumpers and connect the pins with a current measuring device such as a multimeter or current probe. The DSK provides +3.3V, up to 1A for the daughter card. The +3.3V supply is derived from the +5V power source via the main +3.3 volt regulator. It is also possible to provide the daughter card with +12V and -12V when the external power connector (J6) is used. 1-7
1-8
Chapter 2 Board Components
This chapter describes the operation of the major board components on the TMS320C6416T DSK.
Topic
2.1 2.1.1 2.1.2 2.1.3 2.1.4 2.1.5 2.1.6 2.2 2.3 2.4 2.5 2.6 2.7 CPLD (Programmable Logic) CPLD Overview CPLD Registers USER_REG Register DC_REG Register Version Register MISC Register AIC23 Codec Sychronous DRAM Flash Memory LEDs and DIP Switches Daughter Card Interface DSP and EMIFA Clock Generation
Page
2-2 2-2 2-3 2-3 2-4 2-4 2-5 2-6 2-7 2-7 2-7 2-8 2-8
2-1

2.1 CPLD (Programmable Logic) The C6416T DSK uses an Altera EPM3128TC100-10 Complex Programmable Logic Device (CPLD) device to implement: 4 Memory-mapped control/status registers that allow software control of various board features. Address decode and memory access logic. Control of the daughter card interface and signals. Assorted "glue" logic that ties the board components together.
2.1.1 CPLD Overview The CPLD logic is used to implement functionality specific to the DSK. Your own hardware designs will likely implement a completely different set of functions or take advantage of the DSPs high level of integration for system design and avoid the use of external logic completely. The CPLD implements simple random logic functions that eliminate the need for additional discrete devices. In particular, the CPLD aggregates the various reset signals coming from the reset button and power supervisors and generates a global reset. The EPM3128TC100-10 is a 3.3V (5V tolerant), 100-pin QFP device that provides 128 macrocells, 80 I/O pins, and a 10 ns pin-to-pin delay. The device is EEPROM-based and is in-system programmable via a dedicated JTAG interface (a 10-pin header on the DSK). The CPLD source files are written in the industry standard VHDL (Hardware Design Language) and included with the DSK.
2-2

2.1.2 CPLD Registers The 4 CPLD memory-mapped registers allows users to control CPLD functions in software. On the C6416T DSK the registers are primarily used to access the LEDs and DIP switches and control the daughter card interface. The registers are mapped into EMIFB data space at address 0x60000000. They appear as 8-bit registers with a simple asynchronous memory interface. The following table gives a high level overview of the CPLD registers and their bit fields: The table below shows the bit definitions for the 4 registers in CPLD. Table 1: CPLD Register Definitions
Offset
0
Name
USER_REG
Bit 7
USR_SW3 R DC_DET R
Bit 6
USR_SW2 R 0
Bit 5
USR_SW1 R DC_STAT1 R
Bit 4
USR_SW0 R DC_STAT0 R
Bit 3
USR_LED3 R/W 0(Off) DC_RST R 0(No reset) 0
Bit 2
USR_LED2 R/W 0(Off) 0
Bit 1
USR_LED1 R/W 0(Off) DC_CNTL1 R/W 0(low)
Bit 0
USR_LED0 R/W 0(Off) DC_CNTL0 R/W 0(low)
DC_REG
4 6
VERSION MISC McBSP2_EN R (MCBSP2 enabled)
CPLD_VER[3.0] R DSP_PLL_ Select4 R 1 DSP_PLL_ Select3 R 1 DSP_PLL_ Select2 R 1
BOARD VERSION[2.0] R FLASH_PAGE R/W 0 (A19=0) McBSP2 ON/OFF Board R/W 0 (Onboard) McBSP1 ON/OFF Board R/W 0 (Onboard)
DSP_PLL_ Select1 R 1
2.1.3 USER_REG Register USER_REG is used to read the state of the 4 DIP switches and turn the 4 LEDs on or off to allow the user to interact with the DSK. The DIP switches are read by reading the top 4 bits of the register and the LEDs are set by writing to the low 4 bits. Table 2: CPLD USER_REG Register
Bit 7 6 5 4 3 2 1 0 Name USER_SW3 USER_SW2 USER_SW1 USER_SW0 USER_LED3 USER_LED2 USER_LED1 USER_LED0 R/W R R R R R/W R/W R/W R/W Description User DIP Switch 3(1 = Off, 0 = On) User DIP Switch 2(1 = Off, 0 = On) User DIP Switch 1(1 = Off, 0 = On) User DIP Switch 0(1 = Off, 0 = On) User-defined LED 3 Control (0 = Off, 1 = On) User-defined LED 2 Control (0 = Off, 1 = On) User-defined LED 1 Control (0 = Off, 1 = On) User-defined LED 0 Control (0 = Off, 1 = On)
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2.1.4 DC_REG Register DC_REG is used to monitor and control the daughter card interface. DC_DET detects the presence of a daughter card. DC_STAT and DC_CNTL provide simple communications with the daughter card through readable status lines and writable control lines. The daughter card is released from reset when the DSP is released from reset. DC_RST can be used to put the card back in reset. Table 3: DC_REG Register
Bit 7 6 5 4 3 2 1 0 Name DC_DET 0 DC_STAT1 DC_STAT0 DC_RST 0 DC_CNTL1 DC_CNTL0 R/W R R R R R/W R R/W R/W Description Daughter Card Detect (1= Board detected) Always 0 Daughter Card Status 1 (0=Low, 1 = High) Daughter Card Status 0 (0=Low, 1 = High) Daughter Card Reset (0=No Reset, 1 = Reset) Always zero Daughter Card Control 1(0 = Low, 1 = High) Daughter Card Control 0(0 = Low, 1 = High)
2.1.5 VERSION Register The VERSION register contains two read only fields that indicate the BOARD and CPLD versions. This register will allow your software to differentiate between production releases of the DSK and account for any variances. This register is not expected to change often, if at all. Table 4: Version Register Bit Definitions
Bit # 7 6 5 4 3 2 1 0 Name CPLD_VER3 CPLD_VER2 CPLD_VER1 CPLD_VER0 0 DSK_VER2 DSK_VER1 DSK_VER0 R/W R R R R R R R R Description Most Significant CPLD Version Bit CPLD Version Bit CPLD Version Bit Least Significant CPLD Version Bit Always 0 Most Significant DSK Board Version Bit DSK Board Version Bit Least Significant DSK Board Version Bit
2-4

2.1.6 MISC Register The MISC register is used to provide software control for miscellaneous board functions. On the C6416T DSK, the MISC register controls how auxiliary signals are brought out to the daughter-card connectors. McBSP1 and McBSP2 are usually used as the control and data ports of the on-board AIC23 codec. The power-on state of these bits (both 0s) represents that configuration. Set MCBSP1SEL or MCBSP2SEL to route the McBSPs to the daughter card connectors rather than the codec. The Flash and CPLD share CE1 which means that the highest address bit (A21) is used to differentiate between the two. In this configuration 512Kbytes of 8-bit Flash are visible at the beginning of CE1 which matches the chip on the production board. If the Flash is replaced with a 1Mbyte chip, only 512Kbytes of Flash will still be visible but FLASH_PAGE can be used to select between the top and bottom halves. FLASH_PAGE replaces the address bit (A21) that is lost sharing CE1 with the CPLD. An on-board PLL is used to generate the DSPs input clock frequency. The DSPPLL_SELECT bits are read-only versions of the PLL configuration signals. DSPLL_SELECT1-4 (set by configuration switch 3, positions 5-8) allows selection of one of the following CPU frequencies: 500,600,720,850,1000, and 1200 Mhz. Only the 1 Ghz. operation is directly supported in the software that ships with the DSK. The 6416Ts PCI interface and McBSP2 share some pins. The McBSP2_EN signal is used to disable McBSP2 when the PCI interface is active. McBSP2_EN is generated on the board when an appropriate daughter card that uses PCI is plugged in, it can be read through this CPLD bit. The scratch bits are unused. They can be set to any value. Table 5: MISC Register
Bit 7 6 5 4 3 2 1 0 Name McBSP2_EN DSP_PLL SELECT4 DSP_PLL SELECT3 DSP_PLL SELECT2 DSP_PLL SELECT1 FLASH_PAGE MCBSP2SEL MCBSP1SEL R/W R R R R R R/W R/W R/W Description Value of McBSP2_EN from PCI header Used to read frequency selection, see table 2 Used to read frequency selection, see table 2 Used to read frequency selection, see table 2 Used to read frequency selection, see table 2 Flash address bit 19 McBSP2 on/off board (0 = on-board, 1 = off-board) McBSP1 on/off board (0 = on-board, 1 = off-board)
2-5

2.2 AIC23 Codec The DSK uses a Texas Instruments AIC23 (part #TLV320AIC23) stereo codec for input and output of audio signals. The codec samples analog signals on the microphone or line inputs and converts them into digital data so it can be processed by the DSP. When the DSP is finished with the data it uses the codec to convert the samples back into analog signals on the line and headphone outputs so the user can hear the output. The codec communicates using two serial channels, one to control the codecs internal configuration registers and one to send and receive digital audio samples. McBSP1 is used as the unidirectional control channel. It should be programmed to send a 16T-bit control word to the AIC23 in SPI format. The top 7 bits of the control word should specify the register to be modified and the lower 9 should contain the register value. The control channel is only used when configuring the codec, it is generally idle when audio data is being transmitted, McBSP2 is used as the bi-directional data channel. All audio data flows through the data channel. Many data formats are supported based on the three variables of sample width, clock signal source and serial data format. The DSK examples generally use a 16T-bit sample width with the codec in master mode so it generates the frame sync and bit clocks at the correct sample rate without effort on the DSP side. The preferred serial format is DSP mode which is designed specifically to operate with the McBSP ports on TI DSPs. The codec has a 12MHz system clock. The 12MHz system clock corresponds to USB sample rate mode, named because many USB systems use a 12MHz clock and can use the same clock for both the codec and USB controller. The internal sample rate generate subdivides the 12MHz clock to generate common frequencies such as 48KHz, 44.1KHz and 8KHz. The sample rate is set by the codecs SAMPLERATE register. The figure below shows the codec interface on the C6416T DSK.
AIC23 Codec
0 1 2 3 4 5 6 7 8 9 15 LEFTINVOL RIGHTINVOL LEFTHPVOL RIGHTHPVOL ANAPATH DIGPATH POWERDOWN DIGIF SAMPLERATE DIGACT RESET
FSX1 CLKX1 TX1
McBSP1
SPI Format Digital
CS SCLK SDIN
Control Registers
MIC IN
LINE IN
Analog LINE OUT MIC IN LINE IN
DR2 FSX2 CLKR CLKX FSR2 DX2
McBSP2
DSP Format
DOUT LRCOUT BCLK LRCIN DIN
ADC
DAC
LINE OUT HP OUT HP OUT
Figure 2-1, TMS320C6416T DSK CODEC INTERFACE 2-6 TMS320C6416T DSK Module Technical Reference

2.3 Synchronous DRAM The DSK uses a pair of industry standard 64 megabit SDRAMs in CE0 of EMIFA. The two devices are used in parallel to create a 64-bit wide interface. Total available memory is 16 megabytes. The DSK uses a factory setting EMIFA clock at 125 MHz. The integrated SDRAM controller is started by configuring the EMIF in software. Timings can be found in the SDRAM data sheet and the DSK help file. When using the SDRAM, note that one row of the memory array must be refreshed at least every 15.6 microseconds to maintain the integrity of its contents.
2.4 Flash Memory The DSK uses a 512Kbyte external Flash as a boot option. It is connected to CE1 of EMIFB with an 8-bit interface. Flash is a type of memory which does not lose its contents when the power is turned off. When read it looks like a simple asynchronous read-only memory (ROM). Flash can be erased in large blocks commonly referred to as sectors or pages. Once a block has been erased each word can be programmed once through a special command sequence. After than the entire block must be erased again to change the contents. The Flash requires 70ns for both reads and writes. The general settings used with the DSK use 8 cycles for both read and write strobes (80ns) to leave a little extra margin.
2.5 LEDs and DIP Switches The DSK includes 4 software accessible LEDs (D7-D10) and DIP switches (SW1) that provide the user a simple form of input/output. Both are accessed through the CPLD USER_REG register.
2-7

2.6 Daughter Card Interface The DSK provides three expansion connectors that can be used to accept plug-in daughter cards. The daughter card allows users to build on their DSK platform to extend its capabilities and provide customer and application specific I/O. The expansion connectors are for memory, peripherals, and the Host Port Interface (HPI) The memory connector provides access to the DSPs asynchronous EMIF signals to interface with memories and memory mapped devices. It supports byte addressing on 32 bit boundaries. The peripheral connector brings out the DSPs peripheral signals like McBSPs, timers, and clocks. Both connectors provide power and ground to the daughter card. The HPI is a high speed interface that can be used to allow multiple DSPs to communicate and cooperate on a given task. The HPI connector brings out the HPI specific control signals as well as McBSP2. Most of the expansion connector signals are buffered so that the daughter card cannot directly influence the operation of the DSK board. The use of TI low voltage, 5V tolerant buffers, and CBT interface devices allows the use of either +5V or +3.3V devices to be used on the daughter card. Other than the buffering, most daughter card signals are not modified on the board. However, a few daughter card specific control signals like DC_RESET and DC_DET exist and are accessible through the CPLD DC_REG register. The DSK also multiplexes the McBSP1 and McBSP2 of on-board or external use. This function is controlled through the CPLD MISC register.
2.7 DSP and EMIFA Clock Generation The C6416T DSK incorporates a multiple clocking input to the DSP via a selector switch, CPLD, PLL, and multiple oscillators. The oscillators are input to the CPLD and SW3-5 to SW3-8 are also input to the CPLD. Depending on the value of the selector switch the CPLD outputs the appropriate codes to the ICS512 PLL devices and appropriate frequency to generate the frequencies in table 2. The same technique is used for the EMIFA clock. This allows the DSK to support 500,600,720, 850, 1000, and 1200 megahertz CPU clocks. However, the default configuration is 1 gigahertz and the software shipped with the DSK assumes the default configuration
2-8
Chapter 3 Physical Description
This chapter describes the physical layout of the TMS320C6416T DSK and its connectors.
Topic
3.1 3.2 3.3 3.3.1 3.3.2 3.3.3 3.4 3.4.1 3.4.2 3.4.3 3.4.4 3.5 3.5.1 3.5.2 3.6 3.6.1 3.6.2 3.6.3 3.7 3.8 Board Layout Connector Index Expansion Connectors J4, Memory Expansion Connector J3, Peripheral Expansion Connector J1, HPI Expansion Connector Audio Connectors J301, Microphone Connector J303, Audio Line In Connector J304, Audio Line Out Connector J302, Headphone Connector Power Connectors J5, +5 Volt Connector J6, Optional Power Connector Miscellaneous Connectors J201, USB Connector J8, External JTAG Connector JP3, PLD Programming Connector System LEDs Reset Switch
Page
3-2 3-3 3-3 3-4 3-5 3-6 3-7 3-7 3-7 3-8 3-8 3-9 3-9 3-9 3-10 3-10 3-10 3-11 3-11 3-11
3-1

3.1 Board Layout The C6416T DSK is a 8.75 x 4.5 inch (210 x 115 mm.) multi-layer board which is powered by an external +5 volt only power supply. Figure 3-1 shows the layout of the C6416T DSK.
J301
J303
J304
J302
J3
J4
J1
J2
J6
J5
J201
JP3
SW1 D7-10
SW2
J8
Figure 3-1, TMS320C6416T DSK
3-2

3.2 Connector Index The TMS320C6416T DSK has many connectors which provide the user access to the various signals on the DSK. Table 1: TMS320C6416T DSK Connectors
Connector J4 J3 J1 J301 J303 J304 J303 J5 J6 * J8 J201 JP3 SW3 # Pins 80 80 80 3 3 3 3 2 4 14 5 10 8 Memory Peripheral HPI Microphone Line In Line Out Headphone +5 Volt Optional Power Connector External JTAG USB Port CPLD Programming DSP Configuration Switch Function
Note: * Not populated 3.3 Expansion Connectors The TMS320C6416T DSK supports three expansion connectors that follow the Texas Instruments interconnection guidelines. The expansion connector pinouts are described in the following three sections. The three expansion connectors are all 80 pin 0.050 x 0.050 inches low profile connectors from Samtec or AMP. The Samtec SFM Series (surface mount) connectors are designed for high speed interconnections because they have low propagation delay, capacitance, and cross talk. The connectors present a small foot print on the DSK. Each connector includes multiple ground, +5V, and +3.3V power signals so that the daughter card can obtain power directly from the DSK. The peripheral expansion connector additionally provides both +12V and -12V to the daughter card. The recommended mating connector, whose part number is TFM-140-32-S-D-LC, is a surface mount connector that provides a 0.465 mated height. Note: I is on an Input pin O is on an Output pin Z is on a High Impedance pin
3-3

3.3.1 J4, Memory Expansion Connector Table 2: J4, Memory Expansion Connector
Pin
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79
Signal
5V AEA21 AEA19 AEA17 AEA15 GND AEA13 AEA11 AEA9 AEA7 5V AEA5 AEA3 ABE3# ABE1# GND AED31 AED29 AED27 AED25 3.3V AED23 AED21 AED19 AED17 GND AED15 AED13 AED11 AED9 GND AED7 AED5 AED3 AED1 GND AARE# AAOE# ACE3# GND
I/O
Vcc O O O O Vss O O O O Vcc O O O O Vss I/O I/O I/O I/O Vcc I/O I/O I/O I/O Vss I/O I/O I/O I/O Vss I/O I/O I/O I/O Vss O O O Vss
Description
5V voltage supply pin EMIF address pin 21 EMIF address pin 19 EMIF address pin 17 EMIF address pin 15 System ground EMIF address pin 13 EMIF address pin 11 EMIF address pin 9 EMIF address pin 7 5V voltage supply pin EMIF address pin 5 EMIF address pin 3 EMIF byte enable 3 EMIF byte enable 1 System ground EMIF data pin 31 EMIF data pin 29 EMIF data pin 27 EMIF data pin 25 3.3V voltage supply pin EMIF data pin 23 EMIF data pin 21 EMIF data pin 19 EMIF data pin 17 System ground EMIF data pin 15 EMIF data pin 13 EMIF data pin 11 EMIF data pin 9 System ground EMIF data pin 7 EMIF data pin 5 EMIF data pin 3 EMIF data pin 1 System ground EMIF async read enable EMIF async output enable Chip enable 3 System ground
Pin
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80
Signal
5V AEA20 AEA18 AEA16 AEA14 GND AEA12 AEA10 AEA8 AEA6 5V AEA4 AEA2 ABE2# ABE0# GND AED30 AED28 AED26 AED24 3.3V AED22 AED20 AED18 AED16 GND AED14 AED12 AED10 AED8 GND AED6 AED4 AED2 AED0 GND AAWE# AARDY ACE2# GND
I/O
Vcc O O O O Vss O O O O Vcc O O O O Vss I/O I/O I/O I/O Vcc I/O I/O I/O I/O Vss I/O I/O I/O I/O Vss I/O I/O I/O I/O Vss O I O Vss
Description
5V voltage supply pin EMIF address pin 20 EMIF address pin 18 EMIF address pin 16 EMIF address pin 14 System ground EMIF address pin 12 EMIF address pin 10 EMIF address pin 8 EMIF address pin 6 5V voltage supply pin EMIF address pin 4 EMIF address pin 2 EMIF byte enable 2 EMIF byte enable 0 System ground EMIF data pin 30 EMIF data pin 28 EMIF data pin 26 EMIF data pin 24 3.3V voltage supply pin EMIF data pin 22 EMIF data pin 20 EMIF data pin 18 EMIF data pin 16 System ground EMIF data pin 14 EMIF data pin 12 EMIF data pin 10 EMIF data pin 8 System ground EMIF data pin 6 EMIF data pin 4 EMIF data pin 2 EMIF data pin 0 System ground EMIF async write enable EMIF asynchronous ready Chip enable 2 System ground
3-4

3.3.2 J3, Peripheral Expansion Connector Table 3: J3, Peripheral Expansion Connector
Pin
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79
Signal
12V GND 5V GND 5V N/C N/C N/C N/C 3.3V CLKX0 FSX0 GND CLKR0 FSR0 GND CLKX2 FSX2 GND CLKR2 FSR2 GND TOUT0 N/C TOUT1 GND EXT_INT4 N/C N/C RESET GND CNTL1 STAT1 EXT_INT6 ACE3# N/C N/C DC_DET# GND GND
I/O
Vcc Vss Vcc Vss Vcc Vcc I/O I/O Vss I/O I/O Vss I/O I/O Vss I/O I/O Vss O O Vss I O Vss O I I O Vss Vss Vss
Description
12V voltage supply pin System ground 5V voltage supply pin System ground 5V voltage supply pin No connect No connect No connect No connect 3.3V voltage supply pin McBSP0 transmit clock McBSP0 transmit frame sync System ground McBSP0 receive clock McBSP0 receive frame sync System ground McBSP2 transmit clock McBSP2 transmit frame sync System ground McBSP2 receive clock McBSP2 receive frame sync System ground Timer 0 output No connect Timer 1 output System ground External interrupt 4 No connect No connect System reset System ground Daughtercard control 1 Daughtercard status 1 External interrupt 6 Chip enable 3 No connect No connect System ground System ground System ground
Pin
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80
Signal
-12V GND 5V GND 5V N/C N/C N/C N/C 3.3V CLKS0 DX0 GND N/C DR0 GND CLKS2 DX2 GND N/C DR2 GND TINP0 EXT_INT5 TINP1 GND N/C N/C N/C N/C GND CNTL0 STAT0 EXT_INT7 N/C N/C N/C GND ECL KOUT GND
I/O
Vcc Vss Vcc Vss Vcc Vcc I O Vss I Vss I O Vss I Vss I I I Vss Vss O I I Vss O Vss
Description
-12V voltage supply pin System ground 5V voltage supply pin System ground 5V voltage supply pin No connect No connect No connect No connect 3.3V voltage supply pin McBSP0 clock source McBSP0 transmit data System ground No connect McBSP0 receive data System ground McBSP2 clock source McBSP2 transmit data System ground No connect McBSP2 receive data System ground Timer 0 input External interrupt 5 Timer 1 input System ground No connect No connect No connect No connect System ground Daughtercard control Daughtercard status External interrupt 7 No connect No connect No connect System ground EMIF Clock System ground
3-5

3.3.3 J1, HPI Expansion Connector Table 4: J1, HPI Expansion Connector
Pin
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79
Signal
PCI_EN GND XSP_CS GND AD1 AD3 AD5 AD7 GND AD8 AD10 AD12 AD14 GND PCBE1# GND PSERR# GND PPERR# GND PDEVSEL# GND PIRDY# GND PCBE2# AD17 AD19 AD21 AD23 PCBE3# GND AD25 AD27 AD29 AD31 GND PREQ# GND PCLK GND
I/O
I Vss O Vss I/O I/O I/O I/O
Description
PCI enable System ground PCI serial System ground PCI address/data 1 PCI address/data 3 PCI address/data 5 PCI address/data 7 System ground
Pin
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80
Signal
BSP2_EN HPI_RS# BEA13 GND PCBE0# AD0 AD2 AD4 AD6 GND AD9 AD11 AD13 AD15 GND PPAR GND PSTOP# GND PTRDY# GND PFRAME# GND AD16 AD18 AD20 AD22 GND PIDSEL AD24 AD26 AD28 AD30 PGNT# GND PRST# GND PINTA# GND N/C
I/O
I I I Vss I/O I/O I/O I/O I/O Vss I/O I/O I/O I/O Vss I/O Vss I/O Vss I/O Vss I/O Vss I/O I/O I/O I/O Vss I I/O I/O I/O I/O I Vss I Vss O Vss -
Description
MCBSP2_EN HPI reset PCI EEPROM auto-init System ground PCI command/byte ena 0 PCI address/data 0 PCI address/data 2 PCI address/data 4 PCI address/data 6 System ground PCI address/data 9 PCI address/data 11 PCI address/data 13 PCI address/data 15 System ground PCI parity System ground PCI stop System ground PCI target ready System ground PCI Frame System ground PCI address/data 16 PCI address/data 18 PCI address/data 20 PCI address/data 22 System ground PCI init device select PCI address/data 24 PCI address/data 26 PCI address/data 28 PCI address/data 30 PCI bus grant System ground PCI reset System ground PCI interrupt A System ground No connect
I/O I/O I/O I/O Vss I/O Vss I/O Vss I/O Vss I/O Vss I/O Vss I/O I/O I/O I/O I/O I/O Vss I/O I/O I/O I/O Vss O Vss I Vss
PCI address/data 8 PCI address/data 10 PCI address/data 12 PCI address/data 14 System ground PCI command/byte ena 1 System ground PCI system error System ground PCI parity error System ground PCI device select System ground PCI initiator ready System ground PCI command/byte ena 2 PCI address/data 17 PCI address/data 19 PCI address/data 21 PCI address/data 23 PCI command/byte ena 3 System ground PCI address/data 25 PCI address/data 27 PCI address/data 29 PCI address/data 31 System ground PCI bus request System ground PCI Clock System ground
3-6

3.4 Audio Connectors The C6416T DSK has 4 audio connectors. They are described in the following sections. 3.4.1 J301, Microphone Connector The input is a 3.5 mm. stereo jack. Both inputs are connected to the microphone so it is monaural. The signals on the plug are shown in the figure below.
Ground Microphone In Microphone Bias Figure 3-2, Microphone Stereo Jack 3.4.2 J303, Audio Line In Connector The audio line in is a stereo input. The input connector is a 3.5 mm stereo jack. The signals on the mating plug are shown in the figure below.
Ground Right Line In Left Line In Figure 3-3, Audio Line In Stereo Jack
3-7

3.4.3 J304, Audio Line Out Connector The audio line out is a stereo output. The output connector is a 3.5 mm stereo jack. The signals on the mating plug are shown in the figure below.
Ground Right Line Out Left Line Out Figure 3-4, Audio Line Out Stereo Jack
3.4.4 J303, Headphone Connector Connector J4 is a headphone/speaker jack. It can drive standard headphones or a high impedance speaker directly. The standard 3.5 mm jack is shown in the figure below.
Ground Right Headphone Left Headphone Figure 3-5, Headphone Jack
3-8

3.5 Power Connectors The C6416T DSK has 2 power connectors. They are described in the following sections.
3.5.1 J5, +5 Volt Connector Power (+5 volts) is brought onto the TMS320C6416T DSK via connector J5. The connector has an outside diameter of 5.5 mm. and an inside diameter of 2.5 mm. The A diagram of J5 is shown below. +5V J5 Ground PC Board Front View Figure 3-6, TMS320C6416T DSK Power Connector 3.5.2 J6, Optional Power Connector Connector J6 is an optional power connector. It will operate with the standard personal computer power supply. To populate this connector use a Molex #15109-0410 or Tyco #174552-1. The table below shows the voltages on the respective pins. Table 5: J6, Optional Power Connector Pin # 1 2 3 4 Voltage Level +12 Volts -12 Volts Ground +5 Volts
WARNING ! Do not plug into J5 and J6 at the same time.
3-9

3.6 Miscellaneous Connectors The C6416T DSK has 3 additional connectors to aid the user in developing with this product. They are described in the following sections.
3.6.1 J201, USB Connector Connector J201 provides a Universal Serial Bus (USB) Interface to the embedded JTAG emulation logic on the DSK. This allows for code development and debug without the use of an external emulator. The signals on this connector are shown in the below. Table 6: J201, USB Connector Pin # 1 2 3 4 5 6 USB Signal Name USBVdd D+ DUSB Vss Shield Shield
3.6.2 J8, External JTAG Connector The TMS320C6416T DSK is supplied with a 14 pin header interface, J8. This is the standard interface used by JTAG emulators to interface to Texas Instruments DSPs. The pinout for the connector is shown figure 3-6 below.
TMS TDI PD (+3.3V) TDO TCK-RET TCK EMU0
1 3 5 7 9 11 13
2 4 6 8 10 12 14
TRSTGND no pin (key) GND GND GND EMU1
Header Dimensions Pin-to-Pin spacing, 0.100 in. (X,Y) Pin width, 0.025-in. square post Pin length, 0.235-in. nominal
Figure 3-7, JTAG INTERFACE
3-10

3.6.3 JP3, PLD Programming Connector This connector interfaces to the Altera CPLD, U12. It is used in the in the factory for the programming of the CPLD. This connector is not intended to be used outside the factory.
3.7 System LEDs TheTMS320C6416T DSK has four system light emitting diodes (LEDs). These LEDs indicate various conditions on the DSK. These function of each LED is shown in the table below. Table 7: System LEDs
Reference Designator D4 D3 D6 DS201 Color Green Green Orange Green Function USB Emulation in use. When External JTAG Emulator is used this LED is off. +5 Volt present RESET Active USB Active, Blinks during USB data transfer On Signal State 1 1 1 1
3.8 Reset Switch There are three resets on the TMS320C6416T DSK. The first reset is the power on reset. This circuit waits until power is within the specified range before releasing the power on reset pin to the TMS320C6416T. External sources which control the reset are push button SW2, and the on board embedded USB JTAG emulator.
3-11
3-12
Appendix A Schematics
This appendix contains the schematics for the TMS320C6416T DSK. Board components with designators between 200 and 299 (e.g. DS201, R211) are part of Spectrum Digitals embedded JTAG emulator and are not included in these schematics.
A-1
A-2
The TMS320C6416T DSK design is based on TMS320C6416T device device d ata sheet SPRS226C. This schematic is subject to change without notification. Spectrum Digital Inc. assumes no liability for applications assistance, customer product design or infringement of patents described herein.
SCHEMATIC CONTENTS: 1 COVER SHEET 2 CPLD 3 OPTIONS/USER SWITCHES/LEDS 4 6416T CONTROL 5 6416T EMIFA/SDRAM 6 6416T EMIFB/FLASH 7 6416T MCBSP INTERFACE 8 6416T UTOPIA AND HPI INTERFACES 9 DSK DAUGHTERCARD BUFFERS 10 DSK DAUGHTERCARD INTERFACE 11 DSK POWER SUPPLIES 12 6416T POWER AND DECOUPLING CAPS 13 EMULATION CONNECTIONS 14 HIERARCHICAL BLOCKS 15 AIC23 CODEC
DWN DATE
01-November-2004
REVISION STATUS OF SHEETS CHK DATE
R.R.P. R.R.P. NOV 01,2004

DATE ENGR
NOV 01,2004
REV
A J.T.C. NOV 01,2004

DATE ENGR-MGR
SH
15 A
QA DATE
SPECTRUM DIGITAL INCORPORATED

Title
REV
A 14
MFG DATE
A C.M.D. NOV 01,2004 NOV 01,2004

DATE NEXT ASSY USED ON RLSE APPLICATION
R.R.P.
NOV 01,2004
SH
8 A 7 T.M.K. NOV 01,2004 C.M.D.
10
11
12
13
TMS320C6416TDSK
Document Number Size B Date:
REV
508032
Wednesday, November 10, 2004 Sheet 1 of 15
Rev A
SH
3.3V USB_DSP_RST# DC_EMIFA_OE# CPLD_MCBSP1_MUX CPLD_MCBSP2_MUX DC_STAT0 DC_STAT1 3.3V R100 R101 39 91 U12 VCCIO1 VCCIO2 VCCIO3 VCCIO4 VCCIO5 VCCIO6 3 18 34 51 66 82 100 100 DSP_PLL_CLK (4) EMIF_PLL_CLK (4) BRD_RST# FLASH_PAGE R24 1K R39 1K DSP_RST# R22 1K TBED0 TBED1 TBED2 TBED3 TBED4 TBED5 TBED6 TBED7 R35 R56 R40 R23 R97 R98 10K 10K 10K 10K 10K 10K
(6) TBED[7..0]
(6) TBEA[3..1] TBED7 SPARE_ENABLE (4) SPARE_ENABLE (4) CLKMODE1 TBED3 TBED1 USER_LED3 USER_LED1 TBEA2
TBEA1 TBEA2 TBEA3
(9) DC_EMIFA_DIR (9) DC_CNTL_OE# (6) DSP_PLL_SELECT1 (4) CLKMODE0 (6) FLASH_PAGE PIN52 PIN54 PIN55 PIN56 PIN57 PIN58 PIN1 PIN2 PIN5 PIN6 PIN7 PIN8 PIN9 PIN10 1 2 5 6 7 8 9 10 TACE3#
VCCINT1 VCCINT2
52 54 55 56 57 58
USB_DSP_RST# (17) TASDWE# (5,9) TASDCAS# (5,9) TACE2# (5,9) (5,9) TASDRAS# (5,9) DSP_PLL_S0 PWB_REV0 DSP_PLL_S1 PWB_REV1 DSP_PLL_S1 PWB_REV1 (3) SPARE_SELECT PWB_REV2 SPARE_SELECT DC_STAT0 (10) EMIF_PLL_S1 (4) EMIF_PLL_S0 (4) PWB_REV2 (3) SPARE_ENABLE PULLUP/DOWN TO KEEP LOGIC IN RESET WHEN THE CPLD IS NOT PROGRAMMED.
DGND
(3) USER_LED3 (3) USER_LED1 (8) CPLD_MCBSP1_MUX USER_LED0
60 61 63 64 67 68 69 PIN60 PIN61 PIN63 PIN64 PIN67 PIN68 PIN69
TP10 TP DSP_RSn_LED PUSHB_RS
(6) DSP_PLL_SELECT2 (3) USER_LED0 (6) DSP_PLL_SELECT3 (10) DC_CNTL0 (6) BRD_RST# (6) DSP_PLL_SELECT4 (10) DC_RST# PIN70 PIN71 PIN72 PIN75 PIN76 PIN77 PIN79
70 71 72 75 76 77 79
TBAOE# (6) TBARE# (6) PWB_REV0 (3) DSPPLL_S1 (4)
TP20 TP TP15 TP TP19 TP TP16 TP
PIN12 PIN13 PIN14 PIN16 PIN17 PIN19 PIN20 PIN21 PIN22 PIN23 PIN24 PIN25 PIN26 PIN28 PIN29 PIN30 PIN31 PIN32 PIN35 PIN36 PIN37 30 31 32 35 36 37
12 13 14 16 17 19 20 21 22 23 24 25 27 28 29
(10) DC_CNTL1 (7) CPLD_MCBSP2_MUX (3) DSP_RSn_LED (4) DSP_RST# (3) PUSHB_RS (3) USER_SW1 (3) USER_SW2 (10) DC_STAT1 (3) USER_SW3 (6) TBCE0# (8) HPI_RESET# TBEA3
80 81 83 84 85 92 93 94 96 97 98 99 100 PIN80 PIN81 PIN83 PIN84 PIN85 PIN92 PIN93 PIN94 PIN96 PIN97 PIN98 PIN99 PIN100
SPARE_SELECT (6) DC_DET (10) MCBSP2_EN (7,8) USER_SW0 (3) SVS_RST# (11,17) DC_EMIFA_OE# (9)
(14,15) CODEC_CLK (6) TBAWE# ISR_TCK ISR_TMS ISR_TDI 62 15 4 TCK TMS TDI
DGND
88 89 87 90 IN/OE1 IN/GCLR IN/GCLK1 IN/OE2/GCLK2
PIN40 PIN41 PIN42 PIN44 PIN45 PIN46 PIN47 PIN48 PIN49 PIN50 GNDINT1 GNDINT2 GNDIO1 GNDIO2 GNDIO3 GNDIO4 GNDIO5 GNDIO6 GNDIO7 GNDIO8 GNDIO9 GNDIO10 TDO 38 86 11 26 33 43 53 59 65 74 78 95
40 41 42 44 45 46 47 48 49 50 73
TBEA1 TBED2 TBED0 TBED4 TBED5 TBED6 USER_LED2 DSP_PLL_S0
USER_LED2 (3) DSPPLL_S0 (4) OPT_CLK1 (3) OPT_CLK2 (3) ISR_TDO
EPM3128ATC100
3.3V
JP3
DGND
CPLD
3.3V C38 0.1 C68 0.1 C69 0.1 C71 0.1 C72 0.1 C39 0.1 C70 0.1 C40 0.1 Title
2 4 6 8 10
1 3 5 7 9
ISR_TCK ISR_TMS ISR_TDI ISR_TDO
SPECTRUM DIGITAL INCORPORATED TMS320C6416T DSK

Document Number DGND Size B Date:
DGND
HEADER 5X2
10K 10K 10K
RN19A RN19B RN19C
508032
Rev A
A-3
3.3V 3.3V 10K 10K 10K 10K 3 D11 R84 10K MMBD4148 U8 5 SN74AHC1G14 1 2 4 PUSHB_RS (2) SW2 1 2 RESET DGND PUSHBUTTON 33 C119 0.1uF DGND L6 3.3V 3.3V BLM21P221SN C128 R53 1K R34 NU R33 1K DGND 3 4 3 R83 5 6 7 8 USER_SW3 USER_SW2 USER_SW1 USER_SW0 (2) (2) (2) (2) SW DIP-4/SM PADDLE SWITCH SW1 4 3 2 1 RN19D RN19E RN19F RN19G
A-4
DGND U27 1 OFFn VCC R54 NU R120 OPT_CLK1 (2) 100 R37 1K R36 NU GND 25 MHz ICS512 FUNCTION TABLE L7 S1 S0 MULTIPLIER 3.3V 0 4X 5.33X R78 150 5X 2.5X D6 DGND U28 1 OFFn VCC 1 0 Z 1 8X 3X 4 GND 1 1 8 MHz CLK OPT_CLK2 (2) (2) (2) (2) (2) USER_LED3 USER_LED2 USER_LED1 USER_LED0 5 R121 USER_LED3 USER_LED2 USER_LED1 USER_LED0 100 6X (2) DSP_RSn_LED DSP_RSn_LED 8 Z 1 3.33X 0.1uF Z Z 2X YELLOW GREEN GREEN GREEN GREEN D7 D8 D9 D10 R79 150 R80 150 R81 150 R82 150 BLM21P221SN C129 0 Z 0 1 0 Z 0 DGND CLK 5 4 8 0.1uF DUE TO PREVIOUS 6416 DSKS STARTING BOARD REVISION FOR 6416T IS 101binary PWB_REV2 PWB_REV1 PWB_REV0 PWB_REV2 (2) PWB_REV1 (2) PWB_REV0 (2)
DGND
DGND
3.3V
DGND
CPU FREQ 20 ZZ 0 0 0 0 0 1 0 1 0 1 0 1 OFF OFF ON ON OFF ON ON OFF OFF ON Z 0 1 Z 0 Z 0 0 0 1 125 MHz 25 MHz 5 125 MHz 25 MHz 5 125 MHz 25 MHz 5 125 MHz 25 MHz 5 100 MHz 25 MHz 4 100 MHz 25 MHz 4 ON OFF 20 20 20 20 20 5 4 5.33 3 2.5 2
PLL IN-CLK
CPU MULT
PLL MULT
PLL CODE
EMIF FREQ
PLL IN-CLK
PLL MULT
PLL CODE
SW3 -5
SW3 -6
SW3 -7 OFF OFF OFF ON OFF ON
SW3 -8 ON ON OFF OFF OFF OFF SPECTRUM DIGITAL INCORPORATED

Title
500 MHz
12.5 MHz
600 MHz
12 MHz
720 MHz
12 MHz
850 MHz
8 MHz
1000 MHz
12.5 MHz
1200 MHz
12 MHz
TMS320C6416T DSK
Size B Date: Document Number
508032
Rev A
C121 (7,13) XDS_4.1V U21 Vcc 24 0.1 DGND
(10) (10) (10) (10) (10) 1A1 1A2 1A3 1A4 1A5 1B1 1B2 1B3 1B4 1B5 S1 0 0 0 M M M 1 1 1 (2) EMIF_PLL_CLK S0 0 M 1 0 M 1 0 M 1 1OE 1
DC_EINT4 DC_EINT5 DC_EINT6 DC_EINT7 DC_TINP0
3 4 7 8 11
2 5 6 9 10
EINT4 EINT5 EINT6 EINT7 TINP0
MULTIPLIER 4X 5.33X 5X 2.5X 2X 3.33X 6X 3X 8X
(10) DC_TINP1 (10) DC_TOUT0 (10) DC_TOUT1 2A1 2A2 2A3 2A4 2A5 2B1 2B2 2B3 2B4 2B5 GND 12 2OE SN74CBTD3384PW R77 360 Place all PLL external components as close to the DSP. All PLL external components must be on a single side of the board. R51 U10E EXCCET103U E1 EMI FILTER (2) DSP_RST# TP28 AC7 RESET 1 GND I CT10 + 10 C92 0.1 O 3 C401 NU TP5 TP6 TP8 TP7 NU DGND Maximize the distance between switching signals and the PLL external components.
14 17 18 21 22 13
15 16 19 20 23
TINP1 TOUT0 TOUT1
DGND
3.3V DGND DGND C400 NU 1 1 A Y1 NO-POP D6 B5 A4 U400 TP27 3.3V TDO EMU10 EMU11 AE19 AD18 AC18 DSP_TDO (13) DSP_EMU10 (13) DSP_EMU11 (13) C402 .01UF 1 2 3 4 X1/CLK VDD GND REF ICS512 DGND 2 X2 S1 S0 CLK 8 7 6 5 1 JP402 JPSMT B C A 33 OHM A TO B ( DEFAULT) PLACE COMPONENTS ON BACKSIDE OF PWB AS CLOSE TO U10 PIN H25 AS POSSIBLE. 3 DGND 2 C B JP400 JPSMT NOT USED 2 B C 3 DSP_EMU0 DSP_EMU1 DSP_EMU2 DSP_EMU3 DSP_EMU4 DSP_EMU5 DSP_EMU6 DSP_EMU7 DSP_EMU8 DSP_EMU9 (13) (13) (13) (13) (13) (13) (13) (13) (13) (13) DGND AECLKIN 3-PIN SMT JUMPERS ACCEPT 603 RESISTORS. MUST DRIVE 1/0/Z, Z FOR OPEN (2) EMIF_PLL_S1 (2) EMIF_PLL_S0 JP502 1 JPSMT A A JP401 JPSMT NOT USED 3 AF15 AC15 AE16 AD16 AC16 AE17 AD17 AF17 AC17 AE18
(11,12) DSPIO_3.3V
3.3V 2
B4 AF5 AE5 AD5 AF4 NMI EXTINT4_GP04 EXTINT5_GP05 EXTINT6_GP06 EXTINT7_GP07 GP00 GP01_CLKOUT4 GP02_CLKOUT6 GP03 AF6 AE6 AD6 AC6 C6 A5 C5 TINP0 TINP1 TINP2 TOUT0 TOUT1 TOUT2 TDI TMS TCLK TRST PLLV CLKMODE1 CLKMODE0
R29 1K DGND (13) DSP_TDI (13) DSP_TMS (13) DSP_TCK (13) DSP_TRST# J6 G1 H2 C22 3.3V NO-POP NO-POP DGND OPTIONAL R17 H4 H25 A11 AF18 AB16 AF16 AB15 TP29
R30 1K
(2) CLKMODE1 (2) CLKMODE0
CLKMODE1 CLKMODE0
R28 NU
R27 NU
CLKMODE[1:0]: Core CLKIN multiples 00 = x1 01 = x6 10 = x12 11 = x20 ( Default ) THESE INPUTS ARE DRIVEN BY THE CPLD CLKIN AECLKIN BECLKIN
DGND
EMU0 EMU1 EMU2 EMU3 EMU4 EMU5 EMU6 EMU7 EMU8 EMU9 TMS320C6416TGLZ
C500 A Y500 B C C NOT USED 3 2 B 2 NO-POP U500 X1/CLK DGND DSPPLL_S1 (2) DSPPLL_S0 (2) R50 33 DSP_CORE_CLK VDD GND REF ICS512 CLK 5 S0 6 S1 7 X2 8 3 NOT USED DGND NO-POP JP500 JPSMT A JP501 JPSMT
C501
DGND NO-POP
(2) DSP_PLL_CLK
3.3V
L5
MUST DRIVE 1/0/Z, Z FOR OPEN
SEE OPTIONS PAGE FOR INPUT CLOCK INFORMATION
Ferrite Chip
C114 0.1
C113 0.01
3.3V
DGND
(2) SPARE_ENABLE
B C
NOT USED

Title 3
TMS320C6416T DSK
DGND Size B Date: Document Number
508032
Rev A
A-5
RN6A RN6B RN6C RN6D RN6E RN6F RN6G RN6H RN5A RN5B RN5C RN5D RN5E RN5F RN5G RN5H RN4A RN4B RN4C RN4D RN4E RN4F RN4G RN4H RN3A RN3B RN3C RN3D RN3E RN3F RN3G RN3H
TAED32 TAED33 TAED34 TAED35 TAED36 TAED37 TAED38 TAED39 TAED40 TAED41 TAED42 TAED43 TAED44 TAED45 TAED46 TAED47 TAED48 TAED49 TAED50 TAED51 TAED52 TAED53 TAED54 TAED55 TAED56 TAED57 TAED58 TAED59 TAED60 TAED61 TAED62 TAED63
33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33
U10A NEAR DSP AED32 AED33 AED34 AED35 AED36 AED37 AED38 AED39 AED40 AED41 AED42 AED43 AED44 AED45 AED46 AED47 AED48 AED49 AED50 AED51 AED52 AED53 AED54 AED55 AED56 AED57 AED58 AED59 AED60 AED61 AED62 AED63
NEAR DSP
AD26 AC26 AC25 AB25 AB24 AB26 AA24 AA25 AA23 AA26 Y24 Y25 Y23 Y26 W23 W24 AD19 AC19 AF20 AC20 AE20 AD20 AF21 AC21 AE21 AD21 AF22 AD22 AE22 AE23 AF23 AF24
AED32 AED33 AED34 AED35 AED36 AED37 AED38 AED39 AED40 AED41 AED42 AED43 AED44 AED45 AED46 AED47 AED48 AED49 AED50 AED51 AED52 AED53 AED54 AED55 AED56 AED57 AED58 AED59 AED60 AED61 AED62 AED63
A24 A23 B23 B22 C22 A22 C21 B21 D21 A21 C20 B20 D20 A20 D19 C19 H24 H23 G26 G23 G25 G24 F26 F23 F25 F24 E26 E24 E25 D25 D26 C26
RN11A RN11B RN11C RN11D RN11E RN11F RN11G RN11H RN14H RN14G RN14F RN14E RN14D RN14C RN14B RN14A RN10A RN10B RN10C RN10D RN10E RN10F RN10G RN10H RN13H RN13G RN13F RN13E RN13D RN13C RN13B RN13A
33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33
TAED0 TAED1 TAED2 TAED3 TAED4 TAED5 TAED6 TAED7 TAED8 TAED9 TAED10 TAED11 TAED12 TAED13 TAED14 TAED15 TAED16 TAED17 TAED18 TAED19 TAED20 TAED21 TAED22 TAED23 TAED24 TAED25 TAED26 TAED27 TAED28 TAED29 TAED30 TAED31
A-6
TAEA[22..3] (9) TAED[63..0] (9) NEAR SDRAM TABE3# TABE2# TABE1# TABE0# TACE3# TACE2# TASDCAS# TASDRAS# TASDWE# (9) (9) (9) (9) (2,9) (2,9) (2,9) (2,9) (2,9) U13 TAEA15 TAEA14 TAEA16 TAEA13 TAEA12 TAEA11 TAEA10 TAEA9 TAEA8 TAEA7 TAEA6 TAEA5 TAEA4 TAEA3 3.3V R41 TABE3# TABE2# TABE1# TABE0# 59 28 71 16 DQM3 DQM2 DQM1 DQM0 NC NC NC NC CS RAS CAS WE 73 57 30 14 TACE0# TASDRAS# TASDCAS# TASDWE# 20 19 18 17 23 22 21 24 66 65 64 63 62 61 60 27 26 25 BA1 BA0 NC A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 BA1 BA0 NC A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 U9 23 22 21 24 66 65 64 63 62 61 60 27 26 25 TAEA15 TAEA14 TAEA16 TAEA13 TAEA12 TAEA11 TAEA10 TAEA9 TAEA8 TAEA7 TAEA6 TAEA5 TAEA4 TAEA3 ABE7 ABE6 ABE5 ABE4 ABE3 ABE2 ABE1 ABE0 33 33 33 10K TACE0# TACE3# TACE2# T23 T24 R25 R26 M25 M26 L23 L24 ABE7# ABE6# ABE5# ABE4# ABE3# ABE2# ABE1# ABE0# 33 33 33 33 33 33 33 33 RN7A RN7B RN7C RN7D RN7E RN7F RN7G RN7H TABE7# TABE6# TABE5# TABE4# TABE3# TABE2# TABE1# TABE0# TMS320C6416TGLZ T22 V24 V25 V26 U23 U24 U25 U26 T25 T26 R23 R24 P23 P24 P26 N23 N24 N26 M23 M24 AEA22 AEA21 AEA20 AEA19 AEA18 AEA17 AEA16 AEA15 AEA14 AEA13 AEA12 AEA11 AEA10 AEA9 AEA8 AEA7 AEA6 AEA5 AEA4 AEA3 ACE3 ACE2 ACE1 ACE0 L26 ACE3# K23 ACE2# K24 K25 ACE0# R46 R43 TP17 R44 APDT ABUSREQ0 AHOLDA ASOE3 A_ARE/SDCAS/SADS/SRE A_AOE/SDRAS/SOE A_AWE/SDWE/SWE 33 33 33 TASDCKE TAECLKOUT1 TAECLKOUT2 (9) TAEA17 TAECLKOUT1 TASDCKE TASDCAS# TASDRAS# TASDWE# ASDCKE AECLKOUT1 AECLKOUT2 R49 L25 ASDCKE J26 AECLKOUT1 R42 J23 AECLKOUT2 R26 33 33 33 70 69 68 67 NC NC CLK CKE M22 TP18 P22 TP11 N22 TP13 R22 TP12 ASDCAS# R47 J25 ASDRAS# R45 J24 ASDWE# R48 K26 DQM3 DQM2 DQM1 DQM0 NC NC NC NC CS RAS CAS WE 59 28 71 16 73 57 30 14 20 19 18 17 TACE0# TASDRAS# TASDCAS# TASDWE# DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 2 4 5 7 8 10 11 13 74 76 77 79 80 82 83 85 31 33 34 36 37 39 40 42 45 47 48 50 51 53 54 56 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 TAED0 TAED1 TAED2 TAED3 TAED4 TAED5 TAED6 TAED7 TAED8 TAED9 TAED10 TAED11 TAED12 TAED13 TAED14 TAED15 TAED16 TAED17 TAED18 TAED19 TAED20 TAED21 TAED22 TAED23 TAED24 TAED25 TAED26 TAED27 TAED28 TAED29 TAED30 TAED31 2 4 5 7 8 10 11 13 74 76 77 79 80 82 83 85 31 33 34 36 37 39 40 42 45 47 48 50 51 53 54 56 NC NC CLK CKE TAED32 TAED33 TAED34 TAED35 TAED36 TAED37 TAED38 TAED39 TAED40 TAED41 TAED42 TAED43 TAED44 TAED45 TAED46 TAED47 TAED48 TAED49 TAED50 TAED51 TAED52 TAED53 TAED54 TAED55 TAED56 TAED57 TAED58 TAED59 TAED60 TAED61 TAED62 TAED63 TABE7# TABE6# TABE5# TABE4# AARDY AHOLD 70 69 68 67 TAEA17 TAECLKOUT1 TASDCKE 86 72 58 44 84 78 52 46 38 32 12 6 DGND 3.3V NEAR SDRAM C41
+ +
TAEA22 TAEA21 TAEA20 TAEA19 TAEA18 TAEA17 TAEA16 TAEA15 TAEA14 TAEA13 TAEA12 TAEA11 TAEA10 TAEA9 TAEA8 TAEA7 TAEA6 TAEA5 TAEA4 TAEA3
33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33
RN8A RN8B RN8C RN8D RN8E RN8F RN8G RN8H RN9A RN9B RN9C RN9D RN9E RN9F RN9G RN9H RN12A RN12B RN12C RN12D
AEA22 AEA21 AEA20 AEA19 AEA18 AEA17 AEA16 AEA15 AEA14 AEA13 AEA12 AEA11 AEA10 AEA9 AEA8 AEA7 AEA6 AEA5 AEA4 AEA3
9)
TAARDY
TAARDY R25
33
TP14
AARDY L22 V23
VSS VSS VSS VSS VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ
VDD VDD VDD VDD VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ MT48LC2M32B2TG-6
43 29 15 1 81 75 55 49 41 35 9 3
3.3V
43 29 15 1 81 75 55 49 41 35 9 3
VDD VDD VDD VDD VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
VSS VSS VSS VSS VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ MT48LC2M32B2TG-6
86 72 58 44 84 78 52 46 38 32 12 6 DGND
CT13 10
CT5 10
C43 0.1 0.1
C73 0.1
C75 0.1
C95 0.1
C97 0.1
C44 0.1
C42 0.1
C74 0.1
C45 0.1
EMIFA & SDRAM

Title
DGND

508032
Rev A
SPARE_SELECT
(2)
3.3V 3.3V OFF - OPEN ON - CLOSED SW3 R85 R86 R87 R503 1K 1K 1K 1K R105 10K R104 10K
ENDIAN BOOT-1 BOOT-0
3.3V
R68 NU
R69 NU
R70 NU
R71 NU
R72 1K
R75 1K
R504 NU
R103 10K
R102 10K
TBEA20 TBEA19 TBEA18 TBEA17 TBEA16 TBEA15 TBEA14 TBEA13 DGND TBEA13 TBEA11 SW DIP-8/SM PENCIL SWITCH DGND R73 NU R74 NU R505 1K INPUT CLOCK FREQUENCY SELECT DGND (8) (8) 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9
LIL_ENDIAN BOOT_MODE1 BOOT_MODE0 AECLKIN_SEL1 AECLKIN_SEL0 BECLKIN_SEL1 BECLKIN_SEL0 EEAI IPU IPU IPD IPD IPD IPD IPD
DSP_PLL_SELECT1 DSP_PLL_SELECT2 DSP_PLL_SELECT3 DSP_PLL_SELECT4
(2) (2) (2) (2)
TBEA11
UTOPIA_EN
TBEA9 TBEA8
TBCE0# TBARE# TBAOE# TBAWE# TBEA[3..1]
(2) (2) (2) (2) (2) 3.3V C93 0.1 U15
NEAR DSP
U10B
BBE1 BBE0 NEAR DSP R63 R59 33TBCE1# 33TBCE0#
D13 C13
VCC
37
DGND
TMS320C6416TGLZ
BCE3 BCE2 BCE1 BCE0
A13 C12 B12 BCE1# A12 BCE0#
TBED0 TBED1 TBED2 TBED3 TBED4 TBED5 TBED6 TBED7
TBEA20 TBEA19 TBEA18 TBEA17 TBEA16 TBEA15 TBEA14 TBEA13 TBEA12 TBEA11 TBEA10 TBEA9 TBEA8 TBEA7 TBEA6 TBEA5 TBEA4 TBEA3 TBEA2 TBEA1 E16 D18 C18 B18 A18 D17 C17 B17 A17 D16 C16 B16 A16 D15 C15 B15 A15 D14 C14 A14 BEA20 BEA19 BEA18 BEA17 BEA16 BEA15 BEA14 BEA13 BEA12 BEA11 BEA10 BEA9 BEA8 BEA7 BEA6 BEA5 BEA4 BEA3 BEA2 BEA1 BPDT BBUSREQ0 BHOLDA BSOE3 B_ARE/SDCAS/SADS/SRE B_AOE/SDRAS/SOE B_AWE/SDWE/SWE 33 33 33 TBARE# TBAOE# TBAWE# 3.3V (2) FLASH_PAGE BARDY BHOLD BECLKOUT1 BECLKOUT2 BED0 BED1 BED2 BED3 BED4 BED5 BED6 BED7 BED8 BED9 BED10 BED11 BED12 BED13 BED14 BED15 D12 BECLKOUT1 R58 D11 BECLKOUT2 R60 33 33 TBECLKOUT1 TBECLKOUT2 R57 TP23 TP30 10K E12 E14 E13 E15 A10 BARE# B11 BAOE# C11 BAWE# TP26 TP24 TP25 TP22 R64 R61 R62
33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33
RN15A RN15B RN15C RN15D RN15E RN15F RN15G RN15H RN16A RN16B RN16C RN16D RN16E RN16F RN16G RN16H RN17A RN17B RN17C RN17D
BEA20 BEA19 BEA18 BEA17 BEA16 BEA15 BEA14 BEA13 BEA12 BEA11 BEA10 BEA9 BEA8 BEA7 BEA6 BEA5 BEA4 BEA3 BEA2 BEA1
TBEA2 TBEA3 TBEA4 TBEA5 TBEA6 TBEA7 TBEA8 TBEA9 TBEA10 TBEA11 TBEA12 TBEA13 TBEA14 TBEA15 TBEA16 TBEA17 TBEA18 TBEA19 TBEA20
TP21
E11 B19
25 24 23 22 21 20 19 18 8 7 6 5 4 3 2 1 48 17 16 9
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15/A-1 RY/BY NC1 NC2 NC3 TBCE1# TBAOE# TBAWE# (2) BRD_RST# 47 26 28 11 12 BYTE CE OE WE RESET AM29LV400B VSS VSS
29 31 33 35 38 40 42 44 30 32 34 36 39 41 43 45 15 10 13 14 27 46
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19
TBEA1
B10 D10 A9 C10 B9 D9 B8 C9 A7 C8 B7 D8 A6 C7 B6 D7
DGND RN18A BED0 RN18B BED1 RN18C BED2 RN18D BED3 RN18E BED4 RN18F BED5 RN18G BED6 RN18H BED7 DGND
TBED[7..0] (2) NEAR DSP
33 33 33 33 33 33 33 33
EMIFB & FLASH

Title
TBED0 TBED1 TBED2 TBED3 TBED4 TBED5 TBED6 TBED7
TMS320C6416T DSK
508032

Rev A
A-7
1.6K D1 LM4040DCIM3-4.1
A-8
5V R1 DCISO-4.1V (4,13) XDS_4.1V DGND C13 U4 VCC DGND U20 U10D AE4 AB1 AC2 CLKS2_GP08 CLKR2 CLKX2_XSPCLK DR2_XSPDI DX2_XSPDO FSR0 FSX0 C1 E3 FSR0 FSX0 1 DR0 DX0 D2 E2 1OE DC_FSR0 DC_FSX0 2A1 2A2 2A3 2A4 2A5 13 7 9 12 MCBSP2_EN (2,8) S OE GND 8 DGND SN74CBT3257PW R12 360 DGND R55 1K R76 360 DGND 2OE 2B1 2B2 2B3 2B4 2B5 GND (10) (10) DR0 DX0 CLKS0 CLKR0 CLKX0 AB3 AA2 1A1 1A2 1A3 1A4 1A5 F4 D1 E1 CLKS0 CLKR0 CLKX0 3 4 7 8 11 1B1 1B2 1B3 1B4 1B5 Vcc 24 DGND 1A 2A 3A 4A GND FSR2 FSX2 TMS320C6416TGLZ 3.3V AC1 AB2 AF3 FSR2 FSX2 MCBSP2_EN 8 12 9 7 4 16 0.1 C120 0.1 (10) DC_CLKS2 (10) DC_CLKR2 (10) DC_CLKX2 (10) DC_DR2 1 15 S OE SN74CBT3257PW U3 VCC 1A 2A 3A 4A 4 16 14 17 18 21 22 CLKS2 CLKR2 CLKX2 DR2 DX2 2 3 5 6 11 10 14 13 1B1 1B2 2B1 2B2 3B1 3B2 4B1 4B2 2 5 6 9 10 DC_CLKS0 DC_CLKR0 DC_CLKX0 DC_DR0 DC_DX0 (10) (10) (10) (10) (10) (10) (10) (10) DC_FSX2 DC_FSR2 DC_DX2 15 16 19 20 23 12 SN74CBTD3384PW 2 3 5 6 11 10 14 13 1B1 1B2 2B1 2B2 3B1 3B2 4B1 4B2 1 15 DGND
(15) BCLK
(15) AIC23SDATAOUT
(15) AIC23SDATAIN
(15) LRCOUT
(15) LRCIN
(2) CPLD_MCBSP2_MUX
MCBSP
Title
TMS320C6416T DSK
508032
Rev A
5V 16 VCC UXADDR4 UXADDR3 URADDR4 CTL_CLKX1 (15) PIRDYn PFRAMEn P4 R4 PIRDY_HRDY PFRAME_HINT CTL_FSX1 (15) CTL_DX1 (15) 1A 2A 3A 4A GND SN74CBT3257PW DGND R18 360 S OE PRSTn PCLK PINTAn PGNTn PREQn PCBE3n PIDSEL G3 F2 G4 J3 F1 L2 M3 PRST_GP15 PCLK_GP14 PINTA_GP13 PGNT_GP12 PREQ_GP11 PCBE3_GP10 PIDSEL_GP9 XSP_CS PCBE0 AD1 W3 XSP_CS DGND PCBE0n 1 15 CPLD_MCBSP1_MUX (2) DX1 4 7 9 12 8 C28 0.1 CLKX1 DGND FSX1 AA3 AA1 Y4 Y2 Y3 Y1 W4 W2 V2 V3 V1 V4 U2 U3 U1 U4 P5 N1 N5 M1 N4 M2 M4 L1 L4 K1 L3 K2 K4 J1 K3 J2 1B1 1B2 2B1 2B2 3B1 3B2 4B1 4B2 2 3 5 6 11 10 14 13 AD0_HD0 AD1_HD1 AD2_HD2 AD3_HD3 AD4_HD4 AD5_HD5 AD6_HD6 AD7_HD7 AD8_HD8 AD9_HD9 AD10_HD10 AD11_HD11 AD12_HD12 AD13_HD13 AD14_HD14 AD15_HD15 AD16_HD16 AD17_HD17 AD18_HD18 AD19_HD19 AD20_HD20 AD21_HD21 AD22_HD22 AD23_HD23 AD24_HD24 AD25_HD25 AD26_HD26 AD27_HD27 AD28_HD28 AD29_HD29 AD30_HD30 AD31_HD31 U1
LOCATE NEAR UTOPIA HEADER/DSP
R3
1.6K
D2 LM4040DCIM3-4.1
PAD0 PAD1 PAD2 PAD3 PAD4 PAD5 PAD6 PAD7 PAD8 PAD9 PAD10 PAD11 PAD12 PAD13 PAD14 PAD15 PAD16 PAD17 PAD18 PAD19 PAD20 PAD21 PAD22 PAD23 PAD24 PAD25 PAD26 PAD27 PAD28 PAD29 PAD30 PAD31
PDEVSEL_HCNTL1 PSTOP_HCNTL0 PTRDY_HHWIL PCBE2_HR/W PSERR_HDS1 PCBE1_HDS2 PPERR_HCS PPAR_HAS
R1 T4 R3 P1 T1 T2 R2 T3
PDEVSELn PSTOPn PTRDYn PCBE2n PSERRn PCBE1n PPERRn PPAR
DGND
PCI_EN U10C UTOPIA Interface TMS320C6416TGLZ J1 PCI_EN XSP_CS URADDR4 URADDR2 URADDR0 PAD1 PAD3 PAD5 PAD7 MCBSP2_EN (2,7) TBEA13 (6) 3.3V J2
AA4
PCI_EN
HPI DAUGHTER CARD CAN RESET DSP VIA THIS SIGNAL. SIGNAL IS COMBINED WITH OTHER DSP RESET SOURCES.
URADDR3 URADDR1
PCBE0n PAD0 PAD2 PAD4 PAD6 PAD8 PAD10 PAD12 PAD14 PCBE1n PSERRn PAD9 PAD11 PAD13 PAD15 PPAR PSTOPn PPERRn PTRDYn PDEVSELn PFRAMEn PIRDYn PCBE2n PAD17 PAD19 PAD21 PAD23 PCBE3n PAD16 PAD18 PAD20 PAD22
R19 10K
U10F UXADDR0 UXADDR1_DR1 UXADDR2_FSR1 UXADDR3_FSX1 UXADDR4_DX1 URDATA7 URDATA5 URDATA3 URDATA1 URCLAV URENB# UXCLK UXCLAV UXDATA1 UXDATA3 UXDATA5 UXDATA7 URCLK UXENB# UXDATA0 UXDATA2 UXDATA4 UXDATA6 UXSOC URSOC URDATA6 URDATA4 URDATA2 URDATA0 UXDATA0 UXDATA1 UXDATA2 UXDATA3 UXDATA4 UXDATA5 UXDATA6 UXDATA7 UXCLK UXCLAV UXENB UXSOC UXADDR0 UXADDR2 UXADDR4 AD11 AC14 AE15 AC13 UXCLK UXCLAV UXENB# UXSOC AD7 AE7 AF7 AF9 AE8 AD8 AD9 AD10 UXDATA0 UXDATA1 UXDATA2 UXDATA3 UXDATA4 UXDATA5 UXDATA6 UXDATA7 AE9 AF11 AC9 AB13 AB11 UXADDR0 UXADDR1 UXADDR2 FSX1 DX1
URADDR0 URADDR1 URADDR2 URADDR3 CLKX1
AE10 AF10 AC10 AC8 AB12
URADDR0 URADDR1 URADDR2_CLKR1 URADDR3_CLKS1 URADDR4_CLKX1
PAD8/PAD10 WERE SWAPPED ON REV A/B PWB.
HPI_RESET# (2)
URDATA0 URDATA1 URDATA2 URDATA3 URDATA4 URDATA5 URDATA6 URDATA7
AD13 AD14 AE12 AC12 AC11 AF13 AE11 AF12
URDATA0 URDATA1 URDATA2 URDATA3 URDATA4 URDATA5 URDATA6 URDATA7
URCLK URCLAV URENB# URSOC
AD12 AF14 AD15 AB14
URCLK URCLAV URENB URSOC
TMS320C6416GLZ
UXADDR1 UXADDR3
PAD25 PAD27 PAD29 PAD31 PREQn PCLK
PIDSEL PAD24 PAD26 PAD28 PAD30 PGNTn PRSTn PINTAn
(6)
TBEA11
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 SFM-140-L2-S-D-LC DGND DGND
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 SFM140L2SDLC DGND
2 1
REMOVE HARDWIRE OF TBEA11 ON REV E PWB B A JP503 SOLDER_JUMPER
DGND
UTOPIA & HOST PORT I/F

Title
TMS320C6416T DSK
508032
Rev A
A-9
A-10
DC_D[31..0] 3.3V 3.3V 3.3V U17 7 18 Vcc Vcc 42 31 Vcc Vcc 3.3V C17 0.1 0.1 C15 C16 0.1 C14 0.1 Vcc Vcc Vcc Vcc 42 31 R13 10K U5 7 18 DC_A[21..2] (10) (10) DGND 2 3 5 6 8 9 11 12 13 14 16 17 19 20 22 23 1B1 1B2 1B3 1B4 1B5 1B6 1B7 1B8 2B1 2B2 2B3 2B4 2B5 2B6 2B7 2B8 TAEA18 TAEA17 TAEA16 TAEA15 TAEA14 TAEA13 TAEA12 TAEA11 TAEA10 TAEA9 TAEA8 TAEA7 TAEA6 TAEA5 TAEA4 TAEA3 47 46 44 43 41 40 38 37 36 35 33 32 30 29 27 26 1A1 1A2 1A3 1A4 1A5 1A6 1A7 1A8 2A1 2A2 2A3 2A4 2A5 2A6 2A7 2A8 1B1 1B2 1B3 1B4 1B5 1B6 1B7 1B8 2B1 2B2 2B3 2B4 2B5 2B6 2B7 2B8 C20 0.1 C19 0.1 C21 0.1 2 3 5 6 8 9 11 12 13 14 16 17 19 20 22 23 DC_A17 DC_A16 DC_A15 DC_A14 DC_A13 DC_A12 DC_A11 DC_A10 DC_A9 DC_A8 DC_A7 DC_A6 DC_A5 DC_A4 DC_A3 DC_A2 1A1 1A2 1A3 1A4 1A5 1A6 1A7 1A8 2A1 2A2 2A3 2A4 2A5 2A6 2A7 2A8 3.3V C18 0.1 1OE 1DIR 2OE 2DIR 48 1 25 24 1OE 1DIR 2OE 2DIR GND GND GND GND SN74LVTH16245A DGND 3.3V 3.3V 0.1 U16 7 18 Vcc Vcc TAEA22 TAEA21 TAEA20 TAEA19 Vcc Vcc Vcc Vcc Vcc Vcc 42 31 42 31 7 18 DC_A21 DC_A20 DC_A19 DC_A18 C118 0.1 C98 0.1 C99 0.1 U6 DGND 0.1 0.1 0.1 DGND C116 C115 C94 C96 GND GND GND GND 28 34 39 45 4 10 15 21 DGND 48 1 25 24 47 46 44 43 41 40 38 37 36 35 33 32 30 29 27 26 DC_D0 DC_D1 DC_D2 DC_D3 DC_D4 DC_D5 DC_D6 DC_D7 DC_D15 DC_D14 DC_D13 DC_D12 DC_D11 DC_D10 DC_D9 DC_D8 28 34 39 45 GND GND GND GND SN74LVTH16245A GND GND GND GND DGND 4 10 15 21 DGND 3.3V 3.3V C117 0.1 TAED16 TAED17 TAED18 TAED19 TAED20 TAED21 TAED22 TAED23 TAED31 TAED30 TAED29 TAED28 TAED27 TAED26 TAED25 TAED24 (5) TABE3# (5) TABE2# (5) TABE1# (5) TABE0# (2,5) TACE3# (2,5) TACE2# (2,5) TASDCAS# (2,5) TASDRAS# (2,5) TASDWE# (10) DC_ARDY (5) TAECLKOUT2 R14 1K 2 3 5 6 8 9 11 12 13 14 16 17 19 20 22 23 1B1 1B2 1B3 1B4 1B5 1B6 1B7 1B8 2B1 2B2 2B3 2B4 2B5 2B6 2B7 2B8 1A1 1A2 1A3 1A4 1A5 1A6 1A7 1A8 2A1 2A2 2A3 2A4 2A5 2A6 2A7 2A8 1A1 1A2 1A3 1A4 1A5 1A6 1A7 1A8 2A1 2A2 2A3 2A4 2A5 2A6 2A7 2A8 1B1 1B2 1B3 1B4 1B5 1B6 1B7 1B8 2B1 2B2 2B3 2B4 2B5 2B6 2B7 2B8 47 46 44 43 41 40 38 37 36 35 33 32 30 29 27 26 DC_D16 DC_D17 DC_D18 DC_D19 DC_D20 DC_D21 DC_D22 DC_D23 DC_D31 DC_D30 DC_D29 DC_D28 DC_D27 DC_D26 DC_D25 DC_D24 47 46 44 43 41 40 38 37 36 35 33 32 30 29 27 26 2 3 5 6 8 9 11 12 13 14 16 17 19 20 22 23 DC_BE3# DC_BE2# DC_BE1# DC_BE0# DC_CE3# DC_CE2# DC_ARE# DC_AOE# DC_AWE# TAARDY R15 (10) (10) (10) (10) (10) (10) (10) (10) (10) (5) 22 DGND DC_ECLKOUT (10) 1OE 1DIR 2OE 2DIR 28 34 39 45 GND GND GND GND SN74LVTH16245A DGND DC_EMIFA_DIR = 0 FOR WRITES GND GND GND GND DGND 4 10 15 21 DGND 48 1 25 24 48 1 25 24 4 10 15 21 DGND 1OE 1DIR 2OE 2DIR GND GND GND GND GND GND GND GND SN74LVTH16245A 28 34 39 45 DGND R403 1K 3.3V #OE L L H DIR L H X OPERATION A <-- B A --> B ISOLATION
(5) TAEA[22..3]
(5) TAED[63..0]
TAED0 TAED1 TAED2 TAED3 TAED4 TAED5 TAED6 TAED7 TAED15 TAED14 TAED13 TAED12 TAED11 TAED10 TAED9 TAED8
(2) DC_EMIFA_OE#
DAUGHTERCARD BUFFERING
Title
(2) DC_EMIFA_DIR
TMS320C6416T DSK
Document Number Size B Date:
(2) DC_CNTL_OE#
508032
Rev A
(9) DC_D[31..0] (9) DC_A[21..2] 5V -12V 3.3V External Peripheral Interface 5V DC_A20 DC_A18 DC_A16 DC_A14 DC_A12 DC_A10 DC_A8 DC_A6 DC_CLKX0 (7) DC_FSX0 (7) DC_CLKR0 (7) DC_FSR0 (7) DC_CLKX2 (7) DC_FSX2 (7) DC_CLKR2 (7) DC_FSR2 (7) DC_TOUT0 (4) DC_TOUT1 (4) DC_EINT4 DC_RST# DC_CNTL1 (2) DC_STAT1 (2) DC_EINT6 (4) R65 10K DC_DET (2) (9) DC_ARDY (9) DC_CE2# 3.3V (2) 3.3V R16 4.7K (9) DC_AWE# (4) (9) (9) DC_BE2# DC_BE0# DC_D30 DC_D28 DC_D26 DC_D24 DC_D22 DC_D20 DC_D18 DC_D16 DC_D14 DC_D12 DC_D10 DC_D8 DC_D6 DC_D4 DC_D2 DC_D0 DC_A4 DC_A2 J3 5V J4 DC_A21 DC_A19 DC_A17 DC_A15 DC_A13 DC_A11 DC_A9 DC_A7 DC_A5 DC_A3 DC_BE3# DC_BE1# DC_D31 DC_D29 DC_D27 DC_D25 DC_D23 DC_D21 DC_D19 DC_D17 DC_D15 DC_D13 DC_D11 DC_D9 DC_D7 DC_D5 DC_D3 DC_D1 DC_ARE# DC_AOE# DC_CE3# CONNECTOR 40 X 2 DGND R2 0 DGND DGND (9) (9) (9) (9) (9) 3.3V 3.3V External Memory Interface 12V 3.3V 5V
(7) DC_CLKS0 (7) DC_DX0 DC_DR0
(7)
(7) DC_CLKS2 (7) DC_DX2 DC_DR2
(7)
(4) DC_TINP0 (4) DC_EINT5 (4) DC_TINP1
(2) DC_CNTL0 (2) DC_STAT0 (4) DC_EINT7
(9) DC_ECLKOUT CONNECTOR 40 X 2 DGND
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79
DAUGHTERCARD I/F
Title
TMS320C6416T DSK
508032

Rev A
A-11
1 2
1 2
J6 12V R9 C6 71.5K 0.1uF C5 3300pF R7 10K 1% C3 0.047uF L1 2.7 uH

+
-12V R5 1.65K 1% C2 560pF R8 107 1% D16 C4 0.01uF C8 0.039uF U2 AGND 3.3 sq in AGND, min thermal pad
D15 MURS120T3
1 2
A-12
Connect at pin 1 Sets Voltage 0.025 OHMS FOR POWER MEASUREMENT R10 3.74K 1% R31 C65 71.5K 1% 0.1uF 3300pF C37 R38 10K TP SVS_RST# (2,17) 3.3V 0.047uF L3 NO-POP CT4
+
5V
OPTIONAL, POWER SUPPLY LOAD RESISTORS, 2512 BODY
R346 NU
R347 NU
DGND C66 0.039uF 107 1% R20 TP1 R21 C10 C127 DSPIO_3.3V 2.7 uH C11 D12 0 100uF 4V R66 CT15
+
DGND U7 C12 470pF 10K 1%
SYSTEM POWER MEASUREMENT POINTS. R IS 2512 BODY, 6 VIAS FROM PAD TO PLANE AGND 3.3 sq in AGND, min thermal pad 3.3V R11 2K 1% C36 8200pF
POWER INPUT
5V L4 R99 CT9
+
J5 16 15 14 VIN3 VIN2 VIN1 3.3V @1.5Amp Max MURS120T3 PGND3 PGND2 PGND1 1000pF TPS54310PWP D3 D13 GREEN MURS120T3 TP32 OPTIONAL CROSS COUPLE D14 MURS120T3 R6 28.0K 1% NO-POP DSP_CVDD 0 R4 MURS120T3 SENSE_DSP_CVDD CT1
+
21 20 19 18 17 POWERPAD RT SYNC SS/ENA VBIAS AGND VSENSE COMP PWRGD BOOT 1 2 3 4 5
CENTER SHUNT SLEEVE R52 180 10uF LESR 0.1uF 13 12 11

+
2.5 MM JACK RASM712
CT16 47uF
BLM41P750SPT C63 0.1uF C64 PH1 PH2 PH3 PH4 PH5 6 7 8 9 10
DSPIO_3.3V (4,12) TP31 TP 100 uF
JP4 NO-POP EMI SUPPRESION. LOCATE NEAR EACH REGULATOR. 6 VIAS FROM PAD TO PLANE OR DIRECT TIE. Connect at pin 1 1.4V -> 17.4K 1% 1.2V -> 28.0K 1% 1.1V -> 42.2K 1% JP2 JP1 NO-POP
0.025 OHMS FOR POWER MEASUREMENT DSP POWER MEASUREMENT POINTS. R IS 2512 BODY, 6 VIAS FROM PAD TO PLANE
1 DGND TestPoint
+5 GND -12 +12 TO BE POPULATED BY THE USER IF NEEDED.
4 3 2 1
DSP_CVDD (12) TP2 TP 100 uF 1.4V @1.5Amp Max
NU Molex 15-24-4041 L2
21 20 19 18 17 POWERPAD RT SYNC SS/ENA VBIAS AGND VSENSE COMP PWRGD BOOT 1 2 3 4 5
CT3
+
16 15 14 C7 0.1uF 13 12 11 PGND3 PGND2 PGND1 TPS54310PWP VIN3 VIN2 VIN1
BLM41P750SPT C9 0.1uF 10uF LESR PH1 PH2 PH3 PH4 PH5 6 7 8 9 10
WARNING: DO NOT SUPPLY POWER TO BOTH POWER CONNECTORS AT THE SAME TIME!
CT2 100uF 4V
C1 1000pF
POWER ESTIMATES BASED ON SPRU190 1.4V@600MHz 3.3V@600MHz 1.09 W 0.52 W 0.778A 0.157A ( no emif clk) MEASURED CURRENT ON C6416TEB, ~0.7A@5V
DAUGHTERCARD STANDOFF GROUNDING
EACH REGULATOR CAN SUPPLY UP TO 3A OF CURRENT. HOWEVER COMPONENT VALUES HAVE BEEN SELECTED FOR 1.5A OPERATION. VALUES CALCULATED WITH SWIFT DESIGN TOOL 2.0. KEEP TRACES A MINIMUM OF 0.070 INCHES FROM THESE HOLES. FOLLOW TPS54310 EVM LAYOUT
M1 125_PH
M2 125_PH
M3 125_PH
M4 125_PH
POWER
Title
DGND Size B Date:
TMS320C6416T DSK
Document Number
508032
Rev A
DSP_CVDD U10H U10I
U10G
DSP_CVDD
DSPIO_3.3V
DSPIO_3.3V
DSPIO_3.3V U10J DSP_CVDD F3 A3 G2 G14 H3 H7 J4 K6 RSV RSV RSV RSV RSV RSV RSV RSV DSPIO_3.3V TMS320C6416TGLZ RSV RSV RSV RSV RSV RSV RSV N3 N20 P3 P7 R6 W25 Y13
A2 A25 B1 B14 B26 E7 E8 E10 E17 E19 E20 F9 F12 F15 F18 G5 G22 H5 H22 J21 K5 K22 L5 M5 M6 M21 N2 DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD TMS320C6416TGLZ
A1 A26 B2 B25 C3 C24 D4 D23 E5 E22 F6 F7 F20 F21 G6 G7 G8 G10 G11 G13 G16 G17 G19 G20 G21 H20 K7 K20 L7 L20 N7 P20
CVDD CVDD CVDD CVDD CVDD CVDD CVDD CVDD CVDD CVDD CVDD CVDD CVDD CVDD CVDD CVDD CVDD CVDD CVDD CVDD CVDD CVDD CVDD CVDD CVDD CVDD CVDD CVDD CVDD CVDD CVDD CVDD
CVDD CVDD CVDD CVDD CVDD CVDD CVDD CVDD CVDD CVDD CVDD CVDD CVDD CVDD CVDD CVDD CVDD CVDD CVDD CVDD CVDD CVDD CVDD CVDD CVDD CVDD CVDD CVDD CVDD CVDD CVDD
T7 T20 U7 U20 W7 W20 Y6 Y7 Y8 Y10 Y11 Y14 Y16 Y17 Y19 Y20 Y21 AA6 AA7 AA20 AA21 AB5 AB22 AC4 AC23 AD3 AD24 AE2 AE25 AF1 AF26
P25 R5 R21 T5 U5 U22 V6 V21 W5 W22 Y5 Y22 AA9 AA12 AA15 AA18 AB7 AB8 AB10 AB17 AB19 AB20 AE1 AE13 AE26 AF2 AF25
TMS320C6416TGLZ All capacitors on this sheet are decoupling capacitors for the DSP. They should be placed as close as possible to the DSP. DSP_CVDD DSP_CVDD (11) C23 0.1 C25 0.1 C34 0.1 C58 0.1 C88 0.1 C112 0.1 C110 0.1 C104 0.1 C101 0.1 C52 0.1 C54 0.1 C56 0.1 C85 0.1 C83 0.1 C81 0.1 C27 0.1
A8 A19 B3 B13 B24 C2 C4 C23 C25 D3 D5 D22 D24 E4 E6 E9 E18 E21 E23 F5 F8 F10 F11 F13 F14 F16 F17 F19 F22 G9 G12 G15 G18 H1 H6 H21 H26 J5 J7 J20 J22 K21 L6 L21 M7 M20 N6 N21 N25 P2 C57 0.1 C87 0.1 C89 0.1 C91 0.1 C60 0.1 C49 0.1 C107 0.1 DGND VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS TMS320C6416TGLZ
P6 P21 R7 R20 T6 T21 U6 U21 V5 V7 V20 V22 W1 W6 W21 W26 Y9 Y12 Y15 Y18 AA5 AA8 AA10 AA11 AA13 AA14 AA16 AA17 AA19 AA22 AB4 AB6 AB9 AB18 AB21 AB23 AC3 AC5 AC22 AC24 AD2 AD4 AD23 AD25 AE3 AE14 AE24 AF8 AF19
CT14 10
+ +
CT11 10
CT7 10
C30 0.1
C32 0.1
C105 0.1
C108 0.1
C50 0.1
C46 0.1
C77 0.1
C79 0.1
C61 0.1
DGND
DGND
DSPIO_3.3V DSPIO_3.3V (4,11) C24 0.1 C29 0.1 C33 0.1 C62 0.1 C90 0.1 C109 0.1 C35 0.1 C100 0.1 C106 0.1 C103 0.1 C102 0.1 C78 0.1 C80 0.1 C47 0.1 C48 0.1 C59 0.1
CT6 10
+ +
CT8 10
CT12 10
C111 0.1
C76 0.1
C82 0.1
C84 0.1
C86 0.1
C55 0.1
C53 0.1
C51 0.1
C26 0.1
C31 0.1
DSP POWER & DECOUPLING

DGND Title
TMS320C6416T DSK
508032

Rev A
A-13
1.6K C123 D5 LM4040DCIM3-4.1 0.1 DGND
DGND GND 8 DGND C126 R95 100 1% 22pF DGND Title
3.3V U23 5 5 U22 1 4 2 SN74LVC1G32 3 3 4 2 SN74AHC1G14
1 15 S OE
R89
D4
SN74CBT3257PW
DGND
A-14
DSP JTAG HEADER
DSP_EMU0 (4) DSP_EMU1 (4) 3.3V J8 2 4 8 10 12 14 DGND LOCACTE R-PACK NEAR DSP J7 3.3V R94 30.1K HURRICANE_DETn C125 0.1 DGND R88 1K XDS_TVD 1 3 5 7 9 11 13 3.3V
ROUTE TRACES AS ONE GROUP. MATCH SIGNAL LENGTH.
42 42 42 42 42 42 42 42 42 42 42 42 42 42 DSP_EMU2 (4) DSP_EMU3 (4) DSP_EMU4 (4) DSP_EMU5 (4) DSP_EMU6 (4) DSP_EMU7 (4) DSP_EMU8 (4) DSP_EMU9 (4) DSP_EMU10 (4) DSP_EMU11 (4)
RN2C RN2D RN2A RN2B RN2E RN2F RN2G RN1C RN1A RN1B RN2H RN1F RN1E RN1D
HEADER 7x2, Emulation
JTAG MULTIPLEXERS
5V R93 XDS_4.1V XDS_4.1V HUR_EMU11 HUR_EMU10 HUR_EMU9 HUR_EMU8 HUR_EMU7 HUR_EMU6 HUR_EMU5 HUR_EMU4 HUR_EMU3 HUR_EMU2 HUR_EMU1 HUR_EMU0 (4,7)
GND GND GND GND GND GND GND TYPE0 GND GND GND GND GND GND GND
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15
3.3V U19 47K VCC 1A 2A 3A 4A DSP_TRST# (4) DSP_TMS DSP_TDI DGND DSP_TDO (4) 42 RN1G (4) 3.3V (4) DGND GND 8 12 9 3.3V R91 1K 7 4 16
DGND
R67
(17) T_TDO
(17) T_TDI
(17) T_TMS
XDS_TDO T_TDO XDS_TDI T_TDI XDS_TMS T_TMS XDS_TRST# T_TRSTn 2 3 5 6 11 10 14 13 1B1 1B2 2B1 2B2 3B1 3B2 4B1 4B2 S OE SN74CBT3257PW 1 15
(17) T_TRSTn
C2 B3 C4 C5 B5 C6 B6 C7 C9 B9 C10 B10 C11 B11 C12 C13 B13 C14 B14 C8 B12 B7 B4 B2 C3 C15 C1 B15 B1 B8 EMU18 EMU17 EMU16 EMU15 EMU14 EMU13 EMU12 EMU11 EMU10 EMU9 EMU8 EMU7 EMU6 EMU5 EMU4 EMU3 EMU2 EMU1 EMU0 TCKRTN TCLK TDO TDI TMS TRSTn ID3 ID2 ID1 ID0 TVD GND GND GND GND GND GND GND TYPE1 GND GND GND GND GND GND GND HEADER 4x15 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
3.3V
DGND
U18
SN74AHC1G14 U26 SN74LVC1G32 1 4 2 3.3V C124 .1uF VCC 1A 2A 3A 4A 12 9 7 4 16 DGND MUX_EMU0 MUX_EMU1 HUR_TCK HUR_TCKRTN 1 4 2 DGND U24 R92 33 SN74LVC1G32 R96 33 DSP_TCK (4)
HURRICANE_DETn 2
DGND U25 47K
3.3V
R90
(16,17) T_EMU0
(16,17) T_EMU1
(17) T_TCK
XDS_EMU0 T_EMU0 XDS_EMU1 T_EMU1 XDS_TCK T_TCK XDS_TCKRET T_TCK_RET 2 3 5 6 11 10 14 13 1B1 1B2 2B1 2B2 3B1 3B2 4B1 4B2
(17) T_TCK_RET
EMULATION
Size B Document Number
C122
150
.1uF
LTST-C150GKT USB IN USE
DGND DGND
508032
Date: Wednesday, November 10, 2004 Sheet 13 of 15
Rev A
3.3V C67
.1uFDGND U11 5 1 4 33 2 SN74LVC1G32 3 CLK_12MHZ
(2,15) CODEC_CLK
R32
DGND 3.3V AIC23 Audio CODEC_SYSCLK 3.3V AIC3.3V (2,11,17) SVS_RST# PONRSn 3.3V 5V USB/Emulation 5V
(7,15) BCLK (7,15) LRCIN (7,15) AIC23SDATAIN (7,15) AIC23SDATAOUT (7,15) LRCOUT DATA_BCLK DATA_SYNCIN DATA_DIN DATA_DOUT DATA_SYNCOUT (2,17) USB_DSP_RST# USB_DSP_RST# CLK_12MHZ CLK_24MHZ CTL_DATA CTL_CLK CTL_CS GND AIC23 Audio DGND USB/Emulation
T_TRSTn T_TCK T_TMS T_TDI T_TDO T_EMU0 T_EMU1
T_TRSTn T_TCK T_TMS T_TDI T_TDO T_EMU0 T_EMU1
(13,17) (13,17) (13,17) (13,17) (13,17) (13,16,17) (13,16,17)
(8,15) CTL_DX1 (8,15) CTL_CLKX1 (8,15) CTL_FSX1
T_TCK_RET GND
T_TCK_RET (13,17)
DGND
Hierarchical Blocks
Title
TMS320C6416T DSK
Size B Date:
4 3 2
Document Number
508032
Wednesday, November 10, 2004 Sheet
1
Rev A 14 of 15
A-15
10uF C324220uF C326 0.1uF C327 NO POP C331 U307

PW Package +
C325 L303 BLM21P221SN C328 NO POP R331 0
A-16
(14) CODEC_SYSCLK R325 2.2K 3.3VA C315 R326 4.7K C316 NO POP C319 C323220uF C322 0.1uF 3
+ +
L301 HZ0805E601R
J301
Microphone In C318 NO POP 1uF

+
4 2 1 10uF C321 47pF R328 NO POP L302 BLM21P221SN C317 NO POP J302
R327 0
C320 NO POP
4 2 1 Head Phone Out
C329 NO POP C330 NO POP R334 4.7K R332 47K R333 47K C333 470nF R335 4.7K C334 470nF R336 4.7K RHPOUT LHPOUT RLINE_OUT LLINE_OUT C337 470nF C338 470nF AIC3.3V R339 C341 C343 0.1uF 10uF L307 BLM21P221SN R341 47K R342 47K C344 NO POP C345 NO POP 0.1uF C342 + R340 100 100 C339 NO POP L306 BLM21P221SN 13 12 6 10 9 SPIMODE AIC23LRCIN DOUT 23 24 22 SDIN SCLK MODE RLINE_OUT LLINE_OUT R337 4.7K 17 18 20 19 MIC_BIAS MIC_IN LLINE_IN RLINE_IN XTI/MCLK XTO CLKOUT 25 26 2 C332 0.1uF 14 8 16 AVdd HPVdd VMID AGND HPGND 15 11 10uF
L304 BLM21P221SN
J303
Line In
4 2 1
R338 0
L305 BLM21P221SN
C335 C336 NO POP NO POP
AIC3.3V RN314 AIC23CS 21 CS TLV320AIC23 1 2 3 4 10K 8 7 6 5 BVdd DVdd DGND 1 27 28
4 5 7 3 DIN LRCIN LRCOUT BCLK
C340 NO POP 3 4 2 1 J304
Line Out
(8) CTL_DATA
(8)
CTL_CLK
(8) Control Port
CTL_CS
R343 0
AIC3.3V RN315 AIC3.3V L308 3.3VA BLM21P221SN R344 2.2 1 2 3 4 10K RN316
+ +
8 7 6 5
C346 10uF AIC3.3V
C347 10uF
(7) DATA_DIN (7) DATA_SYNCIN (7) DATA_BCLK (7) DATA_DOUT 33 R345 33
1 2 3 4
8 7 6 5
R312 0 AIC3.3V
(7) DATA_SYNCOUT
AUDIO
GND L309 BLM21P221SN Title

508032
Wednesday, November 10, 2004
3 2
Rev A Sheet
1
15
of
15

4
Appendix B Mechanical Information
This appendix contains the mechanical information about the TMS320C6416T DSK produced by Spectrum Digital.
B-1
B-2
THIS DRAWING IS NOT TO SCALE
Printed in U.S.A., November 2004 508035-0001 Rev. A

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TMS320C6416T DSK Technical Reference

DSP Development Systems

TMS320C6416T DSK Technical Reference

508035-0001 Rev. A November 2004

Copyright 2004 Spectrum Digital, Inc.

3-10 3-10 3-10 3-11 3-11 3-11 A-1 B-1

Table 1: Manual History Revision A Initial Release History

Chapter 1 Introduction to the TMS320C6416T DSK

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Memory Exp McBSPs EMIFA EMIFB

JTAG Voltage Reg

ENDIAN BOOTM 1 BOOTM 0 SPARE PLL_SEL1 PLL_SEL2 PLL_SEL3 PLL_SEL4

Embedded JTAG Ext. JTAG

Host Port Int

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Spectrum Digital, Inc

TMS320C6416T DSK Module Technical Reference

Spectrum Digital, Inc

Generic 6416 Address Space Internal Memory

6416 DSK Internal Memory Reserved or Peripheral CPLD Flash

Reserved Space or Peripheral Regs

EMIFB CE1 EMIFB CE2

EMIFA CE1 EMIFA CE2

Figure 1-2, Memory Map, C6416T DSK

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TMS320C6416T DSK Module Technical Reference

Spectrum Digital, Inc

Spectrum Digital, Inc

TMS320C6416T DSK Module Technical Reference

Chapter 2 Board Components

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TMS320C6416T DSK Module Technical Reference

Spectrum Digital, Inc

VERSION MISC McBSP2_EN R (MCBSP2 enabled)

CPLD_VER[3.0] R DSP_PLL_ Select4 R 1 DSP_PLL_ Select3 R 1 DSP_PLL_ Select2 R 1

Spectrum Digital, Inc

TMS320C6416T DSK Module Technical Reference

Spectrum Digital, Inc

Spectrum Digital, Inc

FSX1 CLKX1 TX1

Analog LINE OUT MIC IN LINE IN

DR2 FSX2 CLKR CLKX FSR2 DX2

DOUT LRCOUT BCLK LRCIN DIN

LINE OUT HP OUT HP OUT

Spectrum Digital, Inc

Spectrum Digital, Inc

TMS320C6416T DSK Module Technical Reference

Chapter 3 Physical Description

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Figure 3-1, TMS320C6416T DSK

TMS320C6416T DSK Module Technical Reference

Spectrum Digital, Inc

Spectrum Digital, Inc

TMS320C6416T DSK Module Technical Reference

Spectrum Digital, Inc

Spectrum Digital, Inc

TMS320C6416T DSK Module Technical Reference

Spectrum Digital, Inc

Spectrum Digital, Inc

Ground Right Headphone Left Headphone Figure 3-5, Headphone Jack

TMS320C6416T DSK Module Technical Reference

Spectrum Digital, Inc