Parasitic Inductance Effect on Switching Losses for

a High Frequency Dc-Dc Converter

Thomas Meade

, Dara OSullivan

, Raymond Foley

, Cristian Achimescu

, Michael Egan

and Paul McCloskey

Department of Electrical Engineering,

University College Cork,
Cork, Ireland

Tyndall National Institute,

Lee Maltings,
Cork, Ireland
Email: paul.mccloskey@tyndall.ie
AbstractThis work examines the impact of packaging para-
sitics on the efciency of a synchronous DC-DC buck converter.
An anaytical model of the losses in the converter is developed
and this is compared to practical results at switching frequencies
in the range of 1-2 MHz. The effect that the packaging parasitic
inductance has on efciency is highlighted by predicting the
expected losses from a converter with optimised packaging
parasitics.
I. INTRODUCTION
The steady decrease in IC system voltages along with the
sharp rise in power requirements result in signicant current
being delivered from the power supply [1]. This trend coupled
with the increase in switching speeds of power semiconductor
devices, due to the technology transfer from bipolar to MOS
based devices and the reduction in R
ds(on)
means that the
effect of packaging parasitics on power converter performance
is increasingly signicant. As switching speeds increase, the
limiting factor in power device performance is shifting from
the silicon characteristics to the path inductance. This paper
uses an analytical approach to model converter losses and
efciency. The effect of packaging inductance is included in
the model by incorporating inductance values extracted from
the packaging geometry using Ansoft Q3D. The analytical
model of a discrete component converter, in the frequency
range of 1-2 MHz, is veried with practical efciency results.
The model is then applied to predict the efciency of a 3 MHz,
1V, 20A converter using three different packaging techniques.
One technique is to use discrete devices on PCB, the next
technique is to use an integrated power-train incorporating
wire-bonds and the nal technique is to use an innovative
wire-bond-free power train.
II. PACKAGING INDUCTANCE
The self inductance of a wire with rectangular cross section
can be derived using electromagnetic eld theory and geom-
etry mean distance as in [2]. The equation for self inductance
is given in (1), where l is the length of the wires, w and t
are the width and thickness of the rectangular cross section,
respectively. The equation for mutual inductance between two
parallel wires is given in (2) for l > d, where d is the
separation distance and l is the length.
L
self
=

0
l
2
_
ln
2l
w +t
+ 0.5 + 0.22
_
w +t
l
__
(1)
L
mutual
=

0
l
2
_
ln
2l
d
1 +
d
l
_
(2)
It follows from (1), that to minimise the parasitic inductance
value, the length through which the current passes must be
minimised and the cross sectional area through which current
ows maximised.
Simulations were carried out in order to determine whether
a strategy of placing wire-bonds in parallel was more effective
at reducing the parasitic inductance value as opposed to using
a block of copper occupying the same total cross sectional area
of the wire-bonds. It was found that while placing wire-bonds
in parallel reduces the overall self inductance, the effect of
mutual inductance between the wires results in a higher overall
inductance. The formula for calculating the overall inductance
for two wire-bonds in parallel with current owing in the same
direction is
L
total
=
L
self
+L
mutual
2
. (3)
In summary, packaging inductance is minimised by min-
imising current path length, maximising current path cross-
sectional area, and, where possible using a solid path, as
opposed to parallel paths. Such considerations have led to
innovative packaging techniques in power MOSFET design,
such as the DirectFET from International Rectier [3].
III. MOSFET SWITCHING EQUATIONS
The circuit diagram of a synchronous buck converter with
the main power loop parasitics included is shown in Fig.1. It is
important to note that the loop includes the input decoupling
capacitor and its associated parasitic inductance. The parasitic
inductances shown are those which contribute to the switching
losses of the converter. In recent integrated converter power
trains [4], the inductances L
S1
and L
S2
have been effectively
978-1-4244-1874-9/08/$25.00 2008 IEEE 3
+
-
V
D
I
o
L
d1
C
in
Load
High Side
Driver
L
s1
L
d2
Low Side
Driver
L
d3
L
s2
C
out
L
d4
Fig. 1. Buck converter circuit with included parasitic inductance
V
GH
R
G
L
D
C
GS
+
-
V
D
C
GD
C
DS
L
S
Fig. 2. Equivalent circuit for the main transition period
eliminated from the gate drive loop by connecting the source
terminal of the MOSFET directly to the driver inside an
integrated driver-MOSFET package, thus reducing the switch-
ing losses. In the analytical model developed, this source
inductance is included in the analysis but can be given a zero
value in the drive loop equations as the application requires.
In order to examine the effect of the parasitic inductances on
the switching losses of the high side MOSFET, the parasitic
inductances are grouped into two lumped values, with
L
D
= L
d1
+L
d2
+L
d3
+L
d4
+L
s2
(4)
and
L
S
= L
S1
. (5)
Each switching sequence, either from the off to the on state
or vice versa is divided into a number of separate intervals,
for which different conditions and constraints apply [5] [6].
The non-linear characteristics of the internal MOSFET capac-
itances [7] are included in the analysis.
A. Upper MOSFET Turn On Waveforms
Fig. 3 shows current and voltage waveforms during the turn
on of the upper MOSFET. This has four distinct time intervals,
described below.
1) Time interval 1: In this time period the gate voltage
rises to its threshold value. No drain current ows as long as
the gate voltage is less than the threshold voltage V
th
. The
t
V
GH
V
DS
I
DS
V
GS
Current
&
Voltage
I
o
Time
Interval 1
Time
Interval 2
Time
Interval 3
Time
Interval 4
t
1
t
2
t
3
t
4
Fig. 3. Current and voltage waveforms during MOSFET turn-on
time interval ends when the gate to source voltage equals the
threshold voltage.
V
GS
(t) = V
GH

_
1 e
t
R
G
(C
GD
+C
GS
)
_
(6)
2) Time interval 2: In this time interval V
GS
(t) is greater
than V
th
. Drain current, I
DS
(t) now rises. The change in
switching loop current induces a voltage across the parasitic
inductance and causes the drain to source voltage, V
DS
(t)
(which in idealised switching waveforms [8] remains constant)
to fall. Writing equations around the switching loop as in [5]
yields:
V
GS
(t) = A

2
V
GS
(t)
dt
2
+B
dV
GS
(t)
dt
+V
GS
(t) (7)
where
A = R
G
g
fs
C
GD
(L
D
+L
S
) (8)
B = R
G
(C
GD
+C
GS
) +L
S
g
fs
. (9)
Solving (7) and piecing it together with the equation for
V
GS
(t) in time interval 1 [Eqn. (6)], yields:
V
GS
(t) = V
B1
V
B2
e
(tt
1
)
T
1

_
cos
1
(t t
1
) +
sin
1
(t t
1
)

1
T
1
_
if 4AB
2
0
(10)
and
V
GS
(t) = V
B1

V
B2
T
2
T
3

_
T
2
e
(tt
1
)
T
2
T
3
e
(tt
1
)
T
3
_
if 4AB
2
< 0 (11)
where

2
1
=
4AB
2
4A
2
, (12)
T
1
=
2A
B
, (13)
T
2
=
2A
B +

B
2
4A
, (14)
4
and
T
3
=
2A
B

B
2
4A
. (15)
V
GH
is the applied gate voltage and g
fs
is the forward
transconductance of the MOSFET. During turn-on
V
B1
= V
GH
(16)
and
V
B2
= V
GH
V
th
, (17)
while during the turn-off transient
V
B1
= 0 (18)
and
V
B2
=
I
o
g
fs
+V
th
(19)
where I
0
is the full load current. I
DS
(t) and V
DS
(t) of the
MOSFET for this time period can be calculated using (20) and
(21) based on V
GS
(t). This time interval comes to an end at
time t
2
when I
DS
(t) rises to I
0
or V
DS
(t) falls to I
0
R
DSon
,
whichever occurs rst.
I
DS
(t) = g
fs
(V
GS
(t) V
th
) (20)
V
DS
(t) = V
D
(L
D
+L
S
)
dI
DS
(t)
dt
(21)
3) Time interval 3: In this time interval either V
DS
(t)
completes its fall or I
DS
(t) completes its rise. Consider rst
the drain voltage completing its fall, I
DS
(t) having risen to
I
0
. Since the drain current is constant, V
GS
(t) must also be
constant:
V
GS
(t) = V
th
+
I
0
g
fs
. (22)
The drain to source voltage in this time period is given by:
V
DS
(t) = V
DS
(t
2
)
_
V
GH
(V
th
+
I0
g
fs
)
R
G
C
GD
_
(t t
2
) (23)
where V
DS
(t
2
) is the drain to source voltage at the start of
this time period, and t
2
is the time at which I
DS
rises to full
load current. The time period ends at time t
3
when V
DS
(t)
completes its fall to I
0
R
DSon
.
Consider now the situation where the current completes its rise
during the third time interval,V
DS
(t) having already completed
its fall. I
DS
(t) and V
GS
(t) are given by:
I
DS
(t) = I
DS
(t
2
) +
_
V
D
L
D
+L
S
_
(t t
2
) (24)
where V
D
is the applied dc input voltage and I
DS
(t
2
) is the
drain to source current at the start of this time period, and t
2
in this case is the time at which the drain voltage drops to
I
0
R
DSon
.
Current
&
Voltage
V
DS
I
DS
V
GS
V
peak
t
Time
Interval 2
Time
Interval 1
Time
Interval 3
Time
Interval 4
t
4
t
3
t
2
t
1
Fig. 4. Current and voltage waveforms during MOSFET turn-off
V
GS
(t) =
_
V
GH
V
GS
(t
2
)
L
s
L
D
+L
S
V
D
_

_
1 e
(tt
2
)
R
G
(C
GD
+C
GS
)
_
+V
GS
(t
2
)
(25)
4) Time interval 4: In this time interval the gate to source
voltage completes its charge to the level of applied drive
voltage V
GH
.
V
GS
(t) = (V
GH
V
GS
(t
3
))

_
1 e
(tt
3
)
R
G
(C
GD
+C
GS
)
_
+V
GS
(t
3
) (26)
B. Upper MOSFET Turn Off Waveforms
A similar analysis may be performed during the turn-off
transition of the upper MOSFET, using the waveforms shown
in Fig. 4.
1) Time interval 1: In time interval 1, the gate source
voltage, V
GS
(t) falls at a rate determined by the time constant
R
G
(C
GD
+ C
GS
). There is no change to the drain current
or drain to source voltage until the value of V
GS
(t) falls to
V
GS(th)
+ I
0
/g
fs
. This is the gate voltage needed to sustain
drain current I
0
. The gate to source voltage during this period
is given by:
V
GS
(t) = V
GH
e
t
R
G
(C
GS
+C
GD
)
. (27)
This interval ends at time t
1
when V
GS
(t) falls to a value of
V
GS(th)
+
I0
g
fs
.
2) Time Interval 2: In this time period the drain to source
voltage rises to V
D
, the applied dc input voltage. The drain
current remains constant at I
0
and the gate to source voltage
stays constant at V
GS(th)
+
I0
g
fs
. The drain to source voltage
during this time period rises according to the following equa-
tion:
V
DS
(t) =
_
g
fs
V
GS(th)
+I
0
(1 +g
fs
R
G
)C
GD
+C
DS
_
(t t
1
). (28)
5
This time period comes to an end at time t
2
when V
DS
(t)
rises to V
D
.
3) Time Interval 3: As with the second time interval during
turn-on, both the drain current and drain voltage change. A
change in the drain current produces a change in the voltage
across the parasitic inductances L
S
and L
D
. A current ow
through the capacitance C
GD
is produced. This current ow
restrains the rate of decrease of the gate voltage, which in
turn restrains the original rate of change of drain current. The
gate to source voltage during this period is given by (29) or
(30). During this time interval I
DS
(t) falls from I
0
to zero
according to (20) and V
DS
(t) changes in accordance with (21).
This time interval comes to an end at time t
3
when V
GS
(t)
falls to the threshold voltage V
GS(th)
.
V
GS
(t) = V
B1
V
B2
e
(tt
2
)
T
1

_
cos
1
(t t
2
) +
sin
1
(t t
2
)

1
T
1
_
if 4A B
2
0
(29)
V
GS
(t) = V
B1

V
B2
T
2
T
3

_
T
2
e
(tt
2
)
T
2
T
3
e
(tt
2
)
T
3
_
if 4AB
2
< 0 (30)
T
1
, T
2
, T
3
and
1
are as given previously for turn-on interval
2. Also
V
B1
= 0 (31)
and
V
B2
= (I
0
/g
fs
+V
GS(th)
). (32)
4) Time interval 4: At the end of time interval 3, the drain
current has fallen to zero, but the drain voltage V
DS
(t
3
) is
greater than the circuit voltage V
IN
. The drain capacitance
C
DS
rings with the stray circuit inductance. The stray circuit
resistance R
l
damps the oscillation. The drain voltage is given
by:
V
DS
(t) = V
IN
+ (V
DS
(t
3
) V
IN
)e
(tt
3
)
T
4
cos(
4
(t t
3
))
(33)
where
T
4
=
2L
D
R
l
(34)
and

4
=
_
4L
D
C
DS
C
2
DS
R
2
l
2L
D
C
DS
. (35)
The gate voltage decays to zero with time constant R
G
(C
GD
+
C
GS
). The gate to source voltage is given by:
V
GS
(t) = V
GS
(t
3
)e
(tt
3
)
R
G
(C
GD
+C
GS
)
. (36)
IV. SOURCES OF POWER LOSS
A. Crossover Switching Loss
The turn-on switching loss can be calculated using the turn-
on switching waveforms derived in Section III
P
on(loss)
= F
SW
_
t3
t1
V
DS
(t) I
DS
(t)dt (37)
where F
SW
is the switching frequency of the converter.
Similarly, the turn-off switching losses are calculated from
P
off(loss)
= F
SW
_
t3
t1
V
DS
(t) I
DS
(t)dt. (38)
B. Conduction Loss
The upper MOSFET conduction loss is given by:
P
condupper
=
_
I
2
0
+
I
2
0
12
_
DR
DS(onupper)
(39)
where I
0
is the ripple of the load current I
0
, D is the duty
cycle and R
DS(onupper)
is the is the on-state resistance of
the top switch.
The lower MOSFET conduction loss is given by:
P
condlower
=
_
I
2
0
+
I
2
0
12
_
(1 D)R
DS(onlower)
. (40)
C. Gate Drive Loss
Most of the switch losses associated with charging and
discharging the MOSFET gate are dissipated in the driver IC
since the source and sink resistances of the driver IC are much
greater than the MOSFETs internal gate resistance. The gate
drive loss of the upper MOSFET is given, as in [9], by:
P
Gupper
= Q
g
V
GH
Fsw. (41)
A similar equation holds for the gate drive of the lower
MOSFET.
D. Reverse Recovery and Ringing Turn On
The reverse recovery and ringing power loss is calculated
as in [7], via
P
RRR(on)
= F
SW
_
V
D
Q
RR(lower)
+
1
2
Q
oss(lower)
V
D
_
(42)
where Q
RR(lower)
is the reverse recovery charge for the lower
MOSFET, which is dependant on the loop inductance [7], and
Q
oss(lower)
is the charge stored in C
GD
+C
DS
of the lower
MOSFET.
6
I
IN(cap)RMS
=

_
_
(I
SW(pk)
I
IN(avg)
)
2
+
I
2
SW(pp)
12
_
D +I
2
IN(avg)
(1 D) (46)
E. Reverse Recovery and Ringing Energy Turn Off
The reverse recovery ringing power loss during MOSFET
turn-off is given by
P
RRR(off)
= F
SW
1
2
_
Q
oss(V peak)
V
peak
Q
oss(VD)
V
D
_
(43)
where Q
oss(V peak)
is the charge stored in C
GS
+ C
GD
of
the upper MOSFET when the voltage reaches its peak value,
V
peak
. Q
oss(VD)
is the charge stored in C
GS
+ C
GD
of the
upper MOSFET when the voltage reaches its steady state
value, V
D
.
F. Diode Conduction Loss
The average power loss in the synchronous diode is given
by:
P
diode
= V
fr
I
0v
T
d1
F
SW
+V
fr
I
0p
T
d2
F
SW
(44)
where V
fr
is the forward voltage drop, T
d1
and T
d2
are the
dead-times when the diode is conducting, I
0v
is the valley
value of the load current I
0
and I
0p
is the peak value of the
load current I
0
.
G. Other Losses
Losses in the input and output capacitors as well as the
power inductor must also be considered to accurately model
the overall converter loss. The input capacitor power loss can
be calculated from
P
IN(cap)
= I
2
IN(cap)RMS
R
esrIN(cap)
(45)
where the rms capacitor current, I
IN(cap)RMS
, is calculated
from (46) above and
I
IN(avg)
=
V
out
I
out
V
IN
. (47)
I
SW
and are the top-switch current and converter power-
train efciency respectively. The ac component of the load
current generates a power loss in the output capacitors. This
is given by
P
OUT(cap)
= I
2
0(RMS)
R
esrOUT(cap)
(48)
The power inductor losses comprise of hysteresis and eddy-
current losses in the core and winding resistive losses. Total
losses are calculated using a vendor-specied procedure [10]
for the inductor used in the design.
Fig. 5 shows the theoretical loss breakdown of the designed
converter operating at three different frequencies. The most
notable difference between the loss breakdowns as the fre-
quency is increased is the change in the switching loss of the
converter, and in particular, the upper MOSFET turn-off power
loss, P
off
.
U
p
p
e
r

M
O
S

C
o
n
d
u
c
t
i
o
n

L
o
s
s
L
o
w
e
r

M
O
S

C
o
n
d
u
c
t
i
o
n

L
o
s
s
R
e
v
e
r
s
e

R
e
c
o
v
e
r
y

a
n
d

R
i
n
g
i
n
g

T
u
r
n

O
n
R
i
n
g
i
n
g

T
u
r
n

O
f
f
B
o
d
y

D
i
o
d
e

C
o
n
d
u
c
t
i
o
n

L
o
s
s
G
a
t
e
-
D
r
i
v
e

U
p
p
e
r
G
a
t
e
-
D
r
i
v
e

L
o
w
e
r
I
n
p
u
t

C
a
p
a
c
i
t
o
r
I
u
t
p
u
t

C
a
p
a
c
i
t
o
r
P o
n
P o
f
f
I
n
d
u
c
t
o
r

L
o
s
s
W
i
r
e

L
o
s
s
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
P
o
w
e
r

L
o
s
s

(
W
)
534 kHz
1.5 MHz
1.9 MHz
Fig. 5. Theoretical breakdown of power-converter losses at three different
frequencies
V. PRACTICAL DC-DC CONVERTER
A practical DC-DC converter as shown in Fig. 8 was built in
order to verify the analytical power loss equations. The output
voltage is 1V, the input voltage is 12V and the inductor value
is 300 nH. The parasitic inductances were extracted from the
layout diagram, shown in Fig. 9, using the software package
Ansoft Q3D. The extracted inductances are L
D
=6.03 nH and
L
S
=1.65 nH. Oscilliscope plots of V
GS
and V
DS
during the
MOSFET turn-on and turn-off transitions with a 20 A output
current are shown in Figs. 6 and 7 respectively.
Graphs of the efciency versus load current for three
different switching frequencies are shown in Fig. 10. These
results show good correlation between the analytical model
that has been developed (theoretical values) and the measured
practical values.
A. Effect of Parasitic Inductance on a 3 MHz converter
Having validated the analytical model in a discrete-
component converter, it is possible to utilise the model for
predicting the converter efciency at higher switching frequen-
cies, and to examine the effect of using alternative packaging
technologies at these frequencies. A similar power converter
is modelled at a switching frequency of 3 MHz, with packag-
ing parasitic inductances corresponding to (a) discrete power
devices, (b) currently available wire-bonded power trains, and
(c) an innovative wire-bond-free packaging technique using
copper as the interconnect medium. A comparison between the
switching losses of the three converters is shown in Fig. 11. As
is evident from Fig. 11, a higher parasitic inductance slightly
reduces the turn-on switching losses (with L
S
= 0), but
7
Fig. 6. MOSFET turn on voltage waveforms
Fig. 7. MOSFET turn off voltage waveforms
signicantly increases the turn-off loss. The overall effect of
the changes in parasitic inductance on converter efciency can
be seen in Fig. 12. Clearly, currently available wire-bonded
co-packaged power trains offer a signicant advantagein
terms of efciency at a 3MHz switching frequencyover
designs using discrete components; however, the residual
parasitic inductance of even this approach limits the overall
converter efciency. The plot predicts that the most appropriate
packaging strategy for a power converter at this frequency is
one which uses a wire-bond-free approach.
VI. CONCLUSION
This paper has presented an analytical model for a buck
converter which has been veried experimentally. The effect of
Fig. 8. Buck converter as implemented
Fig. 9. Layout diagram for the power stage of the converter
parasitic inductance on the switching losses has been examined
in detail. A loss model for a high frequency converter is
proposed in order to outline the impact of parasitic inductance
on efciency and to highlight the deciencies of using discrete
devices and a layout which are not optimised for minimum
parasitic inductance. The guidelines needed to reduce the
critical parasitic inductance values are also presented.
8
0 2 4 6 8 10 12 14 16 18 20 22 24
0
40
45
50
55
60
65
70
75
80
85
E
f
f
i
c
i
e
n
c
y

(
%
)
I
o
(A)
Theoretical
Practical
(a) FSW=534 kHz
0 2 4 6 8 10 12 14 16 18 20 22 24
0
40
45
50
55
60
65
70
75
80
85
E
f
f
i
c
i
e
n
c
y

(
%
)
I
o
(A)
Theoretical
Practical
(b) FSW=1.5 MHz
0 2 4 6 8 10 12 14 16 18 20 22 24
0
40
45
50
55
60
65
70
75
80
85
E
f
f
i
c
i
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c
y

(
%
)
I
o
(A)
Theoretical
Practical
(c) FSW=1.9MHz
Fig. 10. Efciency vs. load current
REFERENCES
[1] D. Stafere and M. Mankikar, Power technology roadmap for IT power
supplies, in Proc. IEEE Appl. Power Electron. Conf., Mar. 2001, pp.
4953.
[2] X. Qi, G. Wang, Z. Yu, R. W. Dutton, T. Young, and N. Chang, On-
chip inductance modeling and RLC extraction of VLSI interconnects for
Discrete Power Devices
Wire-bonded Power Train
Wire-bond-free Packaging
0
2
4
6
8
10
P
on
P
off
P
o
w
e
r

L
o
s
s

(
W
)
Fig. 11. The effect of parasitic inductance on switching losses at 3MHz with
Io = 20 A
10 12 14 16 18 20 22 24 26 28 30
0
40
45
50
55
60
65
70
75
80
E
f
f
i
c
i
e
n
c
y

(
%
)
I
o
(A)
Discrete Power Devices
Wire-bonded Power Train
Wire-bond-free Packaging
Fig. 12. Efciency comparison at 3 MHz for three packaging techniques
circuit simulation, in Proc. Custom Int. Circuits Conf., May 2000, pp.
487490.
[3] A. Sawle, M. Standing, T. Sammon, and A. Woodworth. Directfet -
a proprietary new source mounted power package for board mounted
power. International Rectier. Surrey, England. [Online]. Available:
http://www.irf.com/technical-info/whitepaper/directfet.pdf
[4] Philips PIP212-12M datasheet. [Online]. Available: http://www.nxp.
com/acrobat/datasheets/PIP212-12M 4.pdf
[5] Y. Xiao, H. Shah, T. Chow, and R. Gutmann, Analytical modeling
and experimental evaluation of interconnect parasitic inductance on
MOSFET switching characteristics, 2004, pp. 516521.
[6] Hexfet power MOSFET designers manual, International Rectier, ch.
11.
[7] Y. Rena, M. Xu, J. Zhou, and F. C. Lee, Analytical loss model of power
MOSFET, IEEE Trans. Power Electron., vol. 21, no. 2, pp. 310319,
Mar. 2006.
[8] N. Mohan, T. M. Undeland, and W. P. Robbins, Power Electronics
Converters, Applications and Design. John Wiley and Sons, ch. 22.
[9] L. Balogh, A design and application guide for high speed power
MOSFET gate drive circuits, 2001, Unitrode Power Supply Design
Seminar.
[10] IHLP-5050 application note, Vishay Dale, 2006, unpublished.
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