Documenti di Didattica
Documenti di Professioni
Documenti di Cultura
Reference Guide
Contents
Preface ....................................................................................................................................... 5 1 Introduction ........................................................................................................................ 7 2 Operational Description of HRPWM ....................................................................................... 9
................................................................................ 10 .............................................................................................. 11 2.3 Principle of Operation ................................................................................................. 12 2.4 Scale Factor Optimizing Software (SFO) ........................................................................... 18 2.5 HRPWM Examples Using Optimized Assembly Code ............................................................ 23 3 HRPWM Register Descriptions ............................................................................................ 29 3.1 Register Summary ..................................................................................................... 29 3.2 Registers and Field Descriptions .................................................................................... 30 Appendix A SFO Library Software - SFO_TI_Build_V5.lib ............................................................... 33 A.1 SFO Library Version Comparison .................................................................................. 33 A.2 Software Usage ....................................................................................................... 36 Appendix B Revision History ...................................................................................................... 41
2.1 2.2 Controlling the HRPWM Capabilities Configuring the HRPWM
Table of Contents
www.ti.com
List of Figures
1 2 3 4 5 6 7 8 9 10 11 12 13 14 Resolution Calculations for Conventionally Generated PWM ......................................................... 7 Operating Logic Using MEP ............................................................................................... 9 HRPWM Extension Registers and Memory Configuration ........................................................... 10 HRPWM System Interface
...............................................................................................
11 16 18 24 24 26 26 30 30 30
................................ ................................ Simple Buck Controlled Converter Using a Single PWM ............................................................ PWM Waveform Generated for Simple Buck Controlled Converter ................................................ Simple Reconstruction Filter for a PWM Based DAC ................................................................ PWM Waveform Generated for the PWM DAC Function ............................................................ HRPWM Configuration Register (HRCNFG) ........................................................................... Counter Compare A High Resolution Register (CMPAHR) .......................................................... TB Phase High Resolution Register (TBPHSHR) .....................................................................
Low % Duty Cycle Range Limitation Example When PWM Frequency = 1 MHz High % Duty Cycle Range Limitation Example when PWM Frequency = 1 MHz
List of Tables
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resolution for PWM and HRPWM ........................................................................................ 7 HRPWM Registers ........................................................................................................ 10 Relationship Between MEP Steps, PWM Frequency and Resolution .............................................. 12 CMPA vs Duty (left), and [CMPA:CMPAHR] vs Duty (right) ......................................................... 14 Duty Cycle Range Limitation for 3 and 6 SYSCLK/TBCLK Cycles ................................................. 17 SFO Library Routines ..................................................................................................... 18 Factor Values .............................................................................................................. 21 Register Descriptions ..................................................................................................... 29 HRPWM Configuration Register (HRCNFG) Field Descriptions .................................................... 30
................................... .............................................. SFO Library Version Comparison ....................................................................................... SFO V5 Library Routines ................................................................................................. Software Functions ........................................................................................................ Technical Changes in the Current Revision ...........................................................................
Counter Compare A High Resolution Register (CMPAHR) Field Descriptions TB Phase High Resolution Register (TBPHSHR) Field Descriptions
30 31 33 34 36 41
List of Figures
Preface
SPRU924F April 2005 Revised October 2011
Notational Conventions
This document uses the following conventions. Hexadecimal numbers are shown with the suffix h. For example, the following number is 40 hexadecimal (decimal 64): 40h. Registers in this document are shown in figures and described in tables. Each register figure shows a rectangle divided into fields that represent the fields of the register. Each field is labeled with its bit name, its beginning and ending bit numbers above, and its read/write properties below. A legend explains the notation used for the properties. Reserved bits in a register figure designate a bit that is used for future device expansion.
www.ti.com
SPRU566 TMS320x28xx, 28xxx DSP Peripheral Reference Guide describes the peripheral reference guides of the 28x digital signal processors (DSPs). SPRU716 TMS320x280x, 2801x, 2804x DSP Analog-to-Digital Converter (ADC) Reference Guide describes how to configure and use the on-chip ADC module, which is a 12-bit pipelined ADC. SPRU791 TMS320x280x, 2801x, 2804x Enhanced Pulse Width Modulator (ePWM) Module Reference Guide describes the main areas of the enhanced pulse width modulator that include digital motor control, switch mode power supply control, UPS (uninterruptible power supplies), and other forms of power conversion SPRU790 TMS320x280x, 2801x, 2804x Enhanced Quadrature Encoder Pulse (eQEP) Module Reference Guide describes the eQEP module, which is used for interfacing with a linear or rotary incremental encoder to get position, direction, and speed information from a rotating machine in high performance motion and position control systems. It includes the module description and registers SPRU807 TMS320x280x, 2801x, 2804x Enhanced Capture (eCAP) Module Reference Guide describes the enhanced capture module. It includes the module description and registers. SPRU924 TMS320x280x, 2801x, 2804x High-Resolution Pulse Width Modulator Reference Guide describes the operation of the high-resolution extension to the pulse width modulator (HRPWM). SPRUEU0 TMS320x280x/2801x Enhanced Controller Area Network (eCAN) Reference Guide describes the enhanced controller area network (eCAN) on the x280x and x2801x devices. SPRUFK7 TMS320x280x, 2801x, 2804x Serial Communication Interface (SCI) Reference Guide describes the features and operation of the serial communication interface (SCI) module that is available on the TMS320x280x, 2801x, 2804x devices. SPRUG72 TMS320x280x, 2801x, 2804x Serial Peripheral Interface Reference Guide describes how the serial peripheral interface works. SPRU721 TMS320x28xx, 28xxx Inter-Integrated Circuit (I2C) Module Reference Guide describes the features and operation of the inter-integrated circuit (I2C) module. SPRU722 TMS320x280x, 2801x, 2804x Boot ROM Reference Guide describes the purpose and features of the bootloader (factory-programmed boot-loading software). It also describes other contents of the device on-chip boot ROM and identifies where all of the information is located within that memory. Tools Guides SPRU513 TMS320C28x Assembly Language Tools v5.0.0 User's Guide describes the assembly language tools (assembler and other tools used to develop assembly language code), assembler directives, macros, common object file format, and symbolic debugging directives for the TMS320C28x device. SPRU514 TMS320C28x Optimizing C/C++ Compiler v5.0.0 User's Guide describes the TMS320C28x C/C++ compiler. This compiler accepts ANSI standard C/C++ source code and produces TMS320 DSP assembly language source code for the TMS320C28x device. SPRU608 TMS320C28x Instruction Set Simulator Technical Overview describes the simulator, available within the Code Composer Studio for TMS320C2000 IDE, that simulates the instruction set of the C28x core. SPRU625 TMS320C28x DSP/BIOS 5.32 Application Programming Interface (API) Reference Guide describes development using DSP/BIOS.
C2000, TMS320C28x, C28x are trademarks of Texas Instruments. 6 Read This First SPRU924F April 2005 Revised October 2011 Submit Documentation Feedback
Reference Guide
SPRU924F April 2005 Revised October 2011
This document is used in conjunction with the device-specific Enhanced Pulse Width Modulator (ePWM) Module Reference Guide. The HRPWM module extends the time resolution capabilities of the conventionally derived digital pulse width modulator (PWM). HRPWM is typically used when PWM resolution falls below ~ 9-10 bits. This occurs at PWM frequencies greater than ~200 kHz when using a CPU/system clock of 100 MHz. The key features of HRPWM are: Extended time resolution capability Used in both duty cycle and phase-shift control methods Finer time granularity control or edge positioning using extensions to the Compare A and Phase registers Implemented using the A signal path of PWM, i.e., on the EPWMxA output. EPWMxB output has conventional PWM capabilities Self-check diagnostics software mode to check if the micro edge positioner (MEP) logic is running optimally
Introduction
The ePWM peripheral is used to perform a function that is mathematically equivalent to a digital-to-analog converter (DAC). As shown in Figure 1, where TSYSCLKOUT = 10 ns (i.e. 100 MHz clock), the effective resolution for conventionally generated PWM is a function of PWM frequency (or period) and system clock frequency. Figure 1. Resolution Calculations for Conventionally Generated PWM
TPWM PWM t TSYSCLK PWM resolution (%) = FPWM/FSYSCLKOUT x 100% PWM resolution (bits) = Log2 (TPWM/TSYSCLKOUT)
If the required PWM operating frequency does not offer sufficient resolution in PWM mode, you may want to consider HRPWM. As an example of improved performance offered by HRPWM, Table 1 shows resolution in bits for various PWM frequencies. These values assume a 100 MHz SYSCLK frequency and a MEP step size of 180 ps. See the device-specific datasheet for typical and maximum performance specifications for the MEP. Table 1. Resolution for PWM and HRPWM
PWM Freq (kHz) 20 50 100 Regular Resolution (PWM) Bits 12.3 11.0 10.0 % 0.0 0.0 0.1 High Resolution (HRPWM) Bits 18.1 16.8 15.8 % 0.000 0.001 0.002 7
Introduction
www.ti.com
Although each application may differ, typical low frequency PWM operation (below 250 kHz) may not require HRPWM. HRPWM capability is most useful for high frequency PWM requirements of power conversion topologies such as: Single-phase buck, boost, and flyback Multi-phase buck, boost, and flyback Phase-shifted full bridge Direct modulation of D-Class power amplifiers
www.ti.com
+1.5 ]
To generate an HRPWM waveform, configure the TBM, CCM, and AQM registers as you would to generate a conventional PWM of a given frequency and polarity. The HRPWM works together with the TBM, CCM, and AQM registers to extend edge resolution, and should be configured accordingly. Although many programming combinations are possible, only a few are needed and practical. These methods are described in Section 2.5. Registers discussed but not found in this document can be seen in the device-specific Enhanced Pulse Width Modulator (ePWM) Module Reference Guide. The HRPWM operation is controlled and monitored using the following registers:
www.ti.com
Shadowed No Yes No
Description Extension Register for HRPWM Phase (8 bits) Extension Register for HRPWM Duty (8 bits) HRPWM Configuration Register
2.1
0x0008
CMPAHR (8)
Reserved (8)
CMPAHR (8)
Reserved (8)
HRPWM capabilities are controlled using the Channel A PWM signal path. Figure 4 shows how the HRPWM interfaces with the 8-bit extension registers.
10
www.ti.com
EPWMxSYNCO
TBCTL[SYNCOSEL]
CMPA shadow (24) CTR=CMPB 16 EPWMB CMPB active (16) CMPB shadow (16) CTR = ZERO Dead band (DB) PWM chopper (PC) Trip zone (TZ) EPWMxBO EPWMxTZINT TZ1 to TZ6
2.2
11
www.ti.com
2.3
Principle of Operation
The MEP logic is capable of placing an edge in one of 255 (8 bits) discrete time steps (see device-specific data sheet for typical MEP step size). The MEP works with the TBM and CCM registers to be certain that time steps are optimally applied and that edge placement accuracy is maintained over a wide range of PWM frequencies, system clock frequencies and other operating conditions. Table 3 shows the typical range of operating frequencies supported by the HRPWM. Table 3. Relationship Between MEP Steps, PWM Frequency and Resolution
System (MHz) 50.0 60.0 70.0 80.0 90.0 100.0
(1) (2)
(3)
PWM MIN (Hz) (4) 763 916 1068 1221 1373 1526
Res. @ MAX (Bits) (5) 11.1 10.9 10.6 10.4 10.3 10.1
System frequency = SYSCLKOUT, i.e., CPU clock. TBCLK =SYSCLKOUT. Table data based on a MEP time resolution of 180 ps (this is an example value, see the device-specific data sheet for MEP limits. MEP steps applied = TSYSCLKOUT/180 ps in this example. PWM minimum frequency is based on a maximum period value, i.e., TBPRD = 65535. PWM mode is asymmetrical up-count. Resolution in bits is given for the maximum PWM frequency stated.
12
www.ti.com
2.3.1
Edge Positioning In a typical power control loop (e.g., switch modes, digital motor control [DMC], uninterruptible power supply [UPS]), a digital controller (PID, 2pole/2zero, lag/lead, etc.) issues a duty command, usually expressed in a per unit or percentage terms. Assume that for a particular operating point, the demanded duty cycle is 0.405 or 40.5% on time and the required converter PWM frequency is 1.25 MHz. In conventional PWM generation with a system clock of 100 MHz, the duty cycle choices are in the vicinity of 40.5%. In Figure 5, a compare value of 32 counts (i.e., duty = 40% ) is the closest to 40.5% that you can attain. This is equivalent to an edge position of 320 ns instead of the desired 324 ns. This data is shown in Table 4. By utilizing the MEP, you can achieve an edge position much closer to the desired point of 324 ns. Table 4 shows that in addition to the CMPA value, 22 steps of the MEP (CMPAHR register) will position the edge at 323.96 ns, resulting in almost zero error. In this example, it is assumed that the MEP has a step resolution of 180 ps. Figure 5. Required PWM Waveform for a Requested Duty = 40.5%
Tpwm = 800 ns 324 ns Demanded duty (40.5%) 10 ns steps 0 EPWM1A 30 31 32 33 34 79
37.5%
40.0%
42.5%
38.8%
41.3%
13
www.ti.com
High Time (ns) 280 290 300 310 320 330 340
CMPA (count) 32 32 32 32 32 32 32 32 32
CMPAHR (count) 18 19 20 21 22 23 24 25 26 27
Duty (%) 40.405 40.428 40.450 40.473 40.495 40.518 40.540 40.563 40.585 40.608
High Time (ns) 323.24 323.42 323.60 323.78 323.96 324.14 324.32 324.50 324.68 324.86
28 29 30 31 32 33 34 Required 32.40
(1) (2) (3)
40.5
324
32
System clock, SYSCLKOUT and TBCLK = 100 MHz, 10 ns For a PWM Period register value of 80 counts, PWM Period = 80 x 10 ns = 800 ns, PWM frequency = 1/800 ns = 1.25 MHz Assumed MEP step size for the above example = 180 ps See the device-specific data manual for typical and maximum MEP values.
2.3.2
Scaling Considerations The mechanics of how to position an edge precisely in time has been demonstrated using the resources of the standard CMPA and MEP (CMPAHR) registers. In a practical application, however, it is necessary to seamlessly provide the CPU a mapping function from a per-unit (fractional) duty cycle to a final integer (non-fractional) representation that is written to the [CMPA:CMPAHR] register combination. To do this, first examine the scaling or mapping steps involved. It is common in control software to express duty cycle in a per-unit or percentage basis. This has the advantage of performing all needed math calculations without concern for the final absolute duty cycle, expressed in clock counts or high time in ns. Furthermore, it makes the code more transportable across multiple converter types running different PWM frequencies. To implement the mapping scheme, a two-step scaling procedure is required.
14
www.ti.com
Assumptions for this example: System clock , SYSCLKOUT PWM frequency Required PWM duty cycle, PWMDuty PWM period in terms of coarse steps, PWMperiod (800 ns/10 ns) Number of MEP steps per coarse step at 180 ps (10 ns /180 ps ), MEP_ScaleFactor Value to keep CMPAHR within the range of 1-255 and fractional rounding constant (default value) = = = = 10 ns (100 MHz) 1.25 MHz (1/800 ns) 0.405 (40.5%) 80
= 55
Step 1: Percentage Integer Duty value conversion for CMPA register CMPA register value = = = = int(PWMDuty*PWMperiod); int means integer part int(0.405*80 ) int(32.4 ) 32 (20h)
Step 2: Fractional value conversion for CMPAHR register CMPAHR register value = (frac(PWMDuty*PWMperiod)*MEP_ScaleFactor +1.5) << 8); frac means fractional part = (frac(32.4) *55 + 1.5) <<8 Shift is to move the value as CMPAHR high byte = (0.4 * 55 + 1.5) <<8 = (22 + 1.5) <<8 = 23.5 * 256; Shifting left by 8 is the same as multiplying by 256. = 6016 = 1780h CMPAHR value = 1700h , lower 8 bits will be ignored by hardware.
CMPAHR value
15
www.ti.com
NOTE: The MEP scale factor (MEP_ScaleFactor) varies with the system clock and DSP operating conditions. TI provides an MEP scale factor optimizing (SFO) software C function, which uses the built in diagnostics in each HRPWM and returns the best scale factor for a given operating point. The scale factor varies slowly over a limited range so the optimizing C function can be run very slowly in a background loop. The CMPA and CMPAHR registers are configured in memory so that the 32-bit data capability of the 28x CPU can write this as a single concatenated value, i.e., [CMPA:CMPAHR]. The mapping scheme has been implemented in both C and assembly, as shown in Section 2.5. The actual implementation takes advantage of the 32-bit CPU architecture of the 28xx, and is somewhat different from the steps shown in Section 2.3.2. For time critical control loops where every cycle counts, the assembly version is recommended. This is a cycle optimized function (11 SYSCLKOUT cycles ) that takes a Q15 duty value as input and writes a single [CMPA:CMPAHR] value.
2.3.3
Duty Cycle Range Limitation In high resolution mode, the MEP is not active for 100% of the PWM period. It becomes operational: 3 SYSCLK cycles after the period starts when diagnostics are disabled 6 SYSCLK cycles after the period starts when SFO diagnostics are running Duty cycle range limitations are illustrated in Figure 6 . This limitation imposes a lower duty cycle limit on the MEP. For example, precision edge control is not available all the way down to 0% duty cycle. Although for the first 3 or 6 cycles, the HRPWM capabilities are not available, regular PWM duty control is still fully operational down to 0% duty. In most applications this should not be an issue as the controller regulation point is usually not designed to be close to 0% duty cycle. To better understand the useable duty cycle range, see Table 5 . Figure 6. Low % Duty Cycle Range Limitation Example When PWM Frequency = 1 MHz
60 ns 30 ns TPWM = 1000 ns (FPWM = 1 MHz) SYSCLKOUT = TBCLK = 100 MHz
0 EPWM1A
100
16
www.ti.com
3 Cycles Minimum Duty 0.6% 1.2% 1.8% 2.4% 3.0% 3.6% 4.2% 4.8% 5.4% 6.0%
6 Cycles SYSCLKOUT Minimum Duty 1.2% 2.4% 3.6% 4.8% 6.0% 7.2% 8.4% 9.6% 10.8% 12.0%
If the application demands HRPWM operation in the low percent duty cycle region, then the HRPWM can be configured to operate in count-down mode with the rising edge position (REP) controlled by the MEP. This is illustrated in Figure 7. In this case, low percent duty limitation is no longer an issue. However, there will be a maximum duty limitation with same percent numbers as given in Table 5 .
17
www.ti.com
Figure 7. High % Duty Cycle Range Limitation Example when PWM Frequency = 1 MHz
60 ns 30 ns Tpwm = 1000 ns (Fpwm = 1 MHz)
100
EPWM1A
2.4
n is the ePWM module number on which the SFO function operates. e.g., n = 1, 2, 3, or 4 for the F2808. Check your device data manual for device configurations. SPRU924F April 2005 Revised October 2011 Submit Documentation Feedback
18
www.ti.com
Constraints when using this function: SFO_MepDis(n) can be used with SYSCLKOUT from 50 MHz to maximum SYSCLK frequency. MEP diagnostics logic uses SYSCLKOUT not TBCLK and hence SYSCLKOUT restriction is an important constraint. SFO_MepDis(n) function does not require a starting Scale Factor value. Additionally, TBCLK must equal SYSCLKOUT. When to use If one of the ePWM modules is not used in HRPWM mode, then it can be dedicated to run the SFO diagnostics for the modules that are running HRPWM mode. Here the single MEP_ScaleFactor value obtained can be applied to other ePWM modules. This assumes that all HRPWM modules MEP steps are similar but may not be identical. The ePWM module that is not active in HRPWM mode is still fully operational in conventional PWM mode and can be used to drive PWM pins. The SFO function only makes use of the MEP diagnostics logic. The other ePWM modules operating in HRPWM mode incur only a 3-cycle minimum duty limitation. SFO_MepEn(n) Scale Factor Optimizer with MEP Enabled This routine runs slower as the calibration logic is used concurrently while HRPWM capabilities are being used by the ePWM module. If SYSCLKOUT = TBCLK = 100 MHz and assuming MEP steps size is 150 ps Typical value at 100 MHz = 66 MEP steps per unit TBCLK (10 ns) The function returns a value in the variable array: MEP_ScaleFactor[n] (2) = Number of MEP steps/SYSCLKOUT = Number of MEP steps/TBCLK Constraints when using this function: SFO_MepEn(n) function is restricted to be used with SYSCLKOUT of 60 MHz maximum SYSCLK frequency. MEP diagnostics logic uses SYSCLKOUT not TBCLK and hence SYSCLKOUT restriction is an important constraint. SFO_MepEn(n) function does require a starting Scale Factor value.MEP_ScaleFactor[0] needs to be initialized to a typical MEP step size value. Additionally, TBCLK must equal SYSCLKOUT.
NOTE:
SFO_MepEn(n)_V5B.lib includes an SFO_MepEn(n)_V5(n) function which does not have this limitation.
When to use If the application requires all ePWM modules to have HRPWM capability (i.e., MEP is operational), then the SFO_MepEn(n) function can run for each of the active ePWM modules with HRPWM capability. In the above case, a 6-cycle MEP inactivity zone exists at the start of the PWM period. See Section 2.3.3 on duty cycle range limitation. It is also possible to run the SFO_MepEn(n) function for only one ePWM module and to use the SFO return value for the other modules. In this case only one ePWM module incurs the 6-cycle limitation, and remaining modules incur only a 3-cycle minimum duty limitation. See Duty cycle limitation section. This assumes that all HRPWM modules MEP steps are similar but may not be identical.
(2)
n is the ePWM module number on which the SFO function operates. e.g., n = 1, 2, 3, or 4 for the F2808. Check your device data manual for device configurations.
Both routines can be run as background tasks in a slow loop requiring negligible CPU cycles. In most applications only one of these routines will be needed. However, if the application has free HRPWM resources then both the routines could be used. The repetition rate at which an SFO function needs to be executed depends on the applications operating environment. As with all digital CMOS devices temperature and supply voltage variations have an effect on MEP operation. However, in most applications these parameters vary slowly and therefore it is often sufficient to execute the SFO function once every 5 to 10 seconds or so. If more rapid variations are expected, then execution may have to be performed more frequently to match the application. Note, there is no high limit restriction on the SFO function repetition rate, hence it can execute as quickly as the background loop is capable.
19
www.ti.com
While using HRPWM feature with no SFO diagnostics, HRPWM logic will not be active for the first 3 TBCLK cycles of the PWM period. While running the application in this configuration, if CMPA register value is less than 3 cycles, then its CMPAHR register must be cleared to zero. This would avoid any unexpected transitions on PWM signal. However, if SFO diagnostic function SFO_MepEn is used in the background, then HRPWM logic will not be active for the first 6 TBCLK cycles of PWM period. While using SFO_MepEn function if CMPA register value is less than 6 cycles, then its CMPAHR register must be cleared to zero. This would avoid any unexpected transitions on PWM signal. Also note that the SFO_MepDis function cannot be used concurrently with PWM signals with HRPWM enabled (see the previous section for details). 2.4.1 Software Usage Software library functions SFO_MepEn(int n) and SFO_MepDis(int n) calculate the MEP scale factor for ePWMn modules, where n = 1, 2, 3, or 4. The scale factor is an integer value in the range 1 255, and represents the number of micro step edge positions available for a system clock period. The scale factor value is returned in an array of integer variables of length 5 called MEP_ScaleFactor[5]. For example, see Table 7.
20
www.ti.com
Functional description
(1)
Returns the scale factor value to array index 1 Returns the scale factor value to array index 2 Returns the scale factor value to array index 3 Returns the scale factor value to array index 4
Returns the scale factor value to array index 1 Returns the scale factor value to array index 2 Returns the scale factor value to array index 3 Returns the scale factor value to array index 4
MEP_ScaleFactor[0] variable is a starting value and used by the SFO software functions internally
To use the HRPWM feature of the ePWMs it is recommended that the SFO functions be used as described here. Step 1. Add Include Files The SFO.h file needs to be included as follows. This include file is mandatory while using the SFO library function. For theTMS320F280x devices, the C280x C/C++ Header Files and Peripheral Examples (literature number SPRC191). DSP280x_Device.h and DSP280x_PWM_defines.h are necessary as they are used with all TI software examples. These include files are optional if customized header files are used in the end applications. Example 1. A Sample of How to Add Include Files
#include "DSP280x_Device.h" // DSP280x Headerfile #include "DSP280x_EPWM_defines.h" // init defines #include "SFO.h" // SFO lib functions (needed for HRPWM)
Step 2. Element Declaration Declare a 5-element array of integer variables as follows: Example 2. Declaring an Element
int MEP_ScaleFactor[5] = {0,0,0,0,0}; // Scale factor values for ePWM1-4 int MEP_ScaleFactor1, MEP_ScaleFactor2, MEP_ScaleFactor3, MEP_ScaleFactor4 // Not required by library volatile struct EPWM_REGS *ePWM[] = {0, &EPwm1Regs, &EPwm2Regs, &EPwm3Regs, &EPwm4Regs};
Step 3. MEP_ScaleFactor Initialization After power up, the SFO_MepEn(n) function needs a starting Scale Factor value. This value can be conveniently determined by using one of the ePWM modules to run the SFO_MepDis(n) function prior to configuring its PWM outputs for the application. SFO_MepDis(n) function does not require a starting Scale Factor value. As part of the one-time initialization code, include the following: Example 3. Initializing With a Scale Factor Value
// MEP_ScaleFactor variables initialized using function SFO_MepDis while (MEP_ScaleFactor[1] == 0) SFO_MepDis(1); //SFO for HRPWM1 while (MEP_ScaleFactor[2] == 0) SFO_MepDis(2); //SFO for HRPWM2
21
www.ti.com
Step 4. Application Code While the application is running, fluctuations in both device temperature and supply voltage may be expected. To be sure that optimal Scale Factors are used for each ePWM module, the SFO function should be re-run periodically as part of a slower back-ground loop. Some examples of this are shown here.
NOTE: See the HRPWM_SFO example in the C280x C/C++ Header Files and Peripheral Examples (SPRC191) available from the TI website.
22
www.ti.com
main() { // //
User code Case1: ePWM1,2,3,4 are running in HRPWM mode SFO_MepEn(1); // Each of these of function enables SFO_MepEn(2); // the respective MEP diagnostic logic SFO_MepEn(3); // and returns MEP Scale factor value SFO_MepEn(4); MEP_ScaleFactor1 MEP_ScaleFactor2 MEP_ScaleFactor3 MEP_ScaleFactor4 = = = = MEP_ScaleFactor[1]; MEP_ScaleFactor[2]; MEP_ScaleFactor[3]; MEP_ScaleFactor[4]; // // // // used used used used for for for for ePWM1 ePWM2 ePWM3 ePWM4
//
// // // // //
Case2:ePWM1,2,3 only are running in HRPWM mode. One of the ePWM channel(as an example ePWM4) is used as for Scale factor calibration Here minimum duty cycle limitation is 3 clock cycles. HRPWM 4 MEP diagnostics circuit is used to estimate the MEP steps with the assumption that all HRPWM channels behave similarly though may not be identical. SFO_MepDis(4); // MEP steps using ePWM4 MEP_ScaleFactor1 = MEP_ScaleFactor[4]; // MEP_ScaleFactor2 = MEP_ScaleFactor1 // MEP_ScaleFactor3 = MEP_ScaleFactor1 // MEP_ScaleFactor4 = MEP_ScaleFactor1 //
2.5
23
www.ti.com
2.5.1 In
Implementing a Simple Buck Converter this example, the PWM requirements are: PWM frequency = 1 MHz (i.e., TBPRD = 100 ) PWM mode = asymmetrical, up-count Resolution = 12.7 bits (with a MEP step size of 150 ps)
Figure 8 and Figure 9 show the required PWM waveform. As explained previously, configuration for the ePWM1 module is almost identical to the normal case except that the appropriate MEP options need to be enabled/selected. Figure 8. Simple Buck Controlled Converter Using a Single PWM
Vin1 Buck EPWM1A Vout1
CA
CA
EPWM1A
24
www.ti.com
The example code shown consists of two main parts: Initialization code (executed once) Run time code (typically executed within an ISR) Example 6 shows the Initialization code. The first part is configured for conventional PWM. The second part sets up the HRPWM resources. This example assumes MEP step size of 150 ps and does not use the SFO library. Example 6. HRPWM Buck Converter Initialization Code
void HrBuckDrvCnf(void) { // Config for conventional PWM first EPwm1Regs.TBCTL.bit.PRDLD = TB_IMMEDIATE; // set Immediate load EPwm1Regs.TBPRD = 100; // Period set for 1000 kHz PWM hrbuck_period = 200; // Used for Q15 to Q0 scaling EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // EPWM1 is the Master EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_DISABLE; EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1; // Note: ChB is initialized here only for comparison purposes, it is not required EPwm1Regs.CMPCTL.bit.LOADAMODE EPwm1Regs.CMPCTL.bit.SHDWAMODE EPwm1Regs.CMPCTL.bit.LOADBMODE EPwm1Regs.CMPCTL.bit.SHDWBMODE = = = = CC_CTR_ZERO; CC_SHADOW; CC_CTR_ZERO; CC_SHADOW;
// optional // optional
//
EPwm1Regs.AQCTLA.bit.ZRO = AQ_SET; EPwm1Regs.AQCTLA.bit.CAU = AQ_CLEAR; EPwm1Regs.AQCTLB.bit.ZRO = AQ_SET; EPwm1Regs.AQCTLB.bit.CBU = AQ_CLEAR; Now configure the HRPWM resources EALLOW; EPwm1Regs.HRCNFG.all = 0x0; EPwm1Regs.HRCNFG.bit.EDGMODE = HR_FEP; EPwm1Regs.HRCNFG.bit.CTLMODE = HR_CMP; EPwm1Regs.HRCNFG.bit.HRLOAD = HR_CTR_ZERO; EDIS; MEP_ScaleFactor = 66*256;
// // // // // // // // // // // //
optional optional Note these registers are protected and act only on ChA clear all bits first Control Falling Edge Position CMPAHR controls the MEP Shadow load on CTR=Zero Start with typical Scale Factor value for 100 MHz Note: Use SFO functions to update MEP_ScaleFactor dynamically
Example 7 shows an assembly example of run-time code for the HRPWM buck converter. Example 7. HRPWM Buck Converter Run-Time Code
EPWM1_BASE .set 0x6800 CMPAHR1 .set EPWM1_BASE+0x8 ;=============================================== HRBUCK_DRV; (can execute within an ISR or loop) ;=============================================== MOVW DP, #_HRBUCK_In MOVL XAR2,@_HRBUCK_In MOVL XAR3,#CMPAHR1 ; Output for EPWM1A (HRPWM) MOV T,*XAR2
; Pointer to Input Q15 Duty (XAR2) ; Pointer to HRPWM CMPA reg (XAR3) ; T <= Duty 25
www.ti.com
2.5.2 In
Implementing a DAC function Using an R+C Reconstruction Filter this example, the PWM requirements are: PWM frequency = 400 kHz (i.e., TBPRD = 250) PWM mode = Asymmetrical, Up-count Resolution = 14 bits ( MEP step size = 150 ps)
Figure 10 and Figure 11 show the DAC function and the required PWM waveform. As explained previously, configuration for the ePWM1 module is almost identical to the normal case except that the appropriate MEP options need to be enabled/selected. Figure 10. Simple Reconstruction Filter for a PWM Based DAC
EPWM1A LPF VOUT1
Figure 11. PWM Waveform Generated for the PWM DAC Function
TPWM = 2.5 s
CA
CA
EPWM1A
The example code shown consists of two main parts: Initialization code (executed once) Run time code (typically executed within an ISR) This example assumes a typical MEP_ScaleFactor and does not use the SFO library. Example 8 shows the Initialization code. The first part is configured for conventional PWM. The second part sets up the HRPWM resources.
26
www.ti.com
// Set Immediate load // Period set for 400 kHz PWM // Used for Q15 to Q0 scaling
// optional // optional
// Now configure the HRPWM resources EALLOW; // // // // // // // // // // Note these registers are protected and act only on ChA. Clear all bits first Control falling edge position CMPAHR controls the MEP. Shadow load on CTR=Zero. Start with typical Scale Factor value for 100 MHz. Use SFO functions to update MEP_ScaleFactor dynamically
EPwm1Regs.HRCNFG.all = 0x0; EPwm1Regs.HRCNFG.bit.EDGMODE = HR_FEP; EPwm1Regs.HRCNFG.bit.CTLMODE = HR_CMP; EPwm1Regs.HRCNFG.bit.HRLOAD = HR_CTR_ZERO; EDIS; MEP_ScaleFactor = 66*256;
Example 9 shows an assembly example of run-time code that can execute in a high-speed ISR loop.
27
www.ti.com
; ; ; ; ; ; ; ;
T <= duty Q15 to Q0 scaling based on period Offset for bipolar operation MEP scale factor (from optimizer s/w) P <= T * AL, optimizer scaling AL <= P, move result back to ACC MEP range and rounding adjustment CMPA:CMPAHR(31:8) <= ACC
; Output for EPWM1B (Regular Res) Optional - for comparison purpose only MOV *+XAR3[2],AH ; Store ACCH to regular CMPB
28
www.ti.com
3.1
Register Summary
A summary of the registers required for the HRPWM is shown in the table below. Table 8. Register Descriptions
Name Time Base Registers TBCTL TBSTS TBPHSHR TBPHS TBCNT TBPRD TBPRDHR Compare Registers CMPCTL CMPAHR CMPA CMPB EPWM Registers ePWM HRCNFG Reserved 0x0000 to 0x001F 0x0020 0x0030 0x003F 32 1 16 Other ePWM registers including the ones given above. HRPWM Configuration Register 0x0007 0x0008 0x0009 0x000A 1/0 1/1 1/1 1/1 Counter Compare Control Register Counter Compare A High Resolution Register Set Counter Compare A Register Set Counter Compare B Register Set [4] 0x0000 0x0001 TBPHSHR 0x0003 0x0004 0x0005 0x0006 1/0 1/0 1/0 1/0 1/0 1/1 1/0 Time Base Control Register Time Base Status Register Time Base Phase High Resolution Register Time Base Phase Register Time Base Counter Register Time Base Period Register Set [3] Time Base Period High Resolution Register Set Offset Size (x16) Description
29
www.ti.com
3.2
Load on CTR = Zero: Time-base counter equal to zero (TBCTR = 0x0000) Load on CTR = PRD: Time-base counter equal to period (TBCTR = TBPRD) Load on either CTR = Zero or CTR = PRD (should not be used with HRPWM) Freeze (no loads possible should not be used with HRPWM)
Control Mode Bits: Selects the register (CMP or TBPHS) that controls the MEP: CMPAHR(8) Register controls the edge position ( i.e., this is duty control mode). (default on reset) TBPHSHR(8) Register controls the edge position ( i.e., this is phase control mode). Edge Mode Bits: Selects the edge of the PWM that is controlled by the micro-edge position (MEP) logic: HRPWM capability is disabled (default on reset) MEP control of rising edge MEP control of falling edge MEP control of both edges
Table 10. Counter Compare A High Resolution Register (CMPAHR) Field Descriptions
Bit 15-8 7-0 Field CMPAHR Reserved Value Description Compare A High Resolution register bits for MEP step control. A minimum value of 0x0001 is needed to enable HRPWM capabilities. Valid MEP range of operation 1-255h. Any writes to these bit(s) must always have a value of 0.
www.ti.com
31
32
www.ti.com
Appendix A
A.1
In SFO_TI_Build_V5.lib/SFO_TI_Build_V5B.lib, the diagnostic software has been optimized to use less memory, to minimize the calibration time, and to support up to 16 HRPWM channels. Table 13 provides functional description of the two SFO library routines in SFO_TI_Build_V5.lib/SFO_TI_Build_V5B.lib.
33
www.ti.com
34
www.ti.com
NOTE: Unlike the original SFO_MepEn(n) routine, this routine cannot run on multiple channels concurrently. Do not call SFO_MepEn_V5(n) for another channel until the function returns a 1 for the current channel. Otherwise, the MEP_ScaleFactor for both channels will become corrupted.
An upgraded version of SFO_MepEn_V5(n) in SFO_TI_Build_V5B.lib supports all available HRPWM configurations. When using this version, the HRCNFG register must be initialized with the appropriate configuration after calling SFO_MepDis_V5(n) to seed the MEP_ScaleFactor[n] and prior to calling SFO_MepEn_V5(n).
The SFO_MepEn_V5(n) function requires a SYSCLKOUT between 60 MHz and maximum SYSCLK frequency only. MEP diagnostics logic uses SYSCLKOUT and not TBCLK. Hence the SYSCLKOUT restriction is an important constraint. It is highly recommended that TBCLK=SYSCLKOUT. Usage: After calling SFO_MepDis(n) to seed MEP_ScaleFactor[n], and prior to using the SFO_MepEn(n) function in SPO_TI_Build_V5B.lib, the HRCNFG register must be initialized with the desired HRPWM configuration. Otherwise, calibration will not be initiated, and calls to SFO_MepEn_V5(n) will continuously return 0. The SFO_MepEn_V5(n) function requires a starting scale factor value, MEP_ScaleFactor[0]. MEP_ScaleFactor[0] needs to be initialized to a typical MEP step size value. To do this, SFO_MepDis_V5(n) can be run on an ePWM channel while the HRPWM is disabled, and the resulting MEP_ScaleFactor[n] value can be copied into MEP_ScaleFactor[0]. If there are drastic environmental changes to your system (i.e., temperature/voltage), it is generally a good idea to re-seed MEP_ScaleFactor[0] with a new typical MEP step size value for the changed conditions. Because SFO_MepEn_V5(n) can be run on only one channel at a time, it is only recommended for systems where there are no spare HRPWM channels available, so SFO calibration must be performed on all channels with HRPWM capabilities enabled. In this case, a 6-cycle MEP inactivity zone exists at the start of each PWM period on all HRPWM channels. See Section 2.3.3 on duty cycle range limitations. The function returns: A one when it has finished SFO calibration for the current channel A zero when SFO diagnostics are still running for the channel A two as an error indicator after calibration has completed if the resulting MEP_ScaleFactor for the channel differs from the original MEP_ScaleFactor[0] seed value by more than +/- 15
The function must be called repetitively before it will return a 1. This function takes a longer time to complete than the SFO_MepDis_V5(n) calibration.
(1)
If SFO calibration must be run on multiple channels at a time while HRPWM capabilities are enabled, the previous version of the SFO library, SFO_TI_Build.lib, which uses more memory resources, can be used instead, and SFO_MepEn(n) can run concurrently for up to 4 ePWM channels with HRPWM enabled. SFO Library Software - SFO_TI_Build_V5.lib 35
Software Usage
www.ti.com
A.2
Software Usage
Software library functions int SFO_MepEn_V5(int n) and int SFO_MepDis_V5(int n) calculate the MEP scale factor for ePWMn Modules, where n= the ePWM channel number. The scale factor value, which represents the number of micro-steps available in a system clock period, is returned in a global array of integer values called MEP_ScaleFactor[x], where x is he maximum numver of HRPWM channels for a device plus one. For example, if the maximum number of HRPWM channels for a device is 16, the scale factor array would be MEP_ScaleFactor[17]. Both SFO_MepEn_V5 and SFO_MepDis_V5 themselves also return a 1 when calibration has completed, indicating the MEP_ScaleFactor has been successfully updated for the channel, and a 0 when calibration is still on-going. A return of 2 represents an out-of-range error. Table 14. Software Functions
Software functional calls int SFO_MepDis_V5(int n)
(1)
Functional Description The scale factor in MEP_ScaleFactor[1] updated when status = 1. The scale factor in MEP_ScaleFactor[2] updated when status = 1. ... The scale factor in MEP_ScaleFactor[16] updated when status = 1 or 2. The scale factor in MEP_ScaleFactor[1] updated when status = 1 or 2. The scale factor in MEP_ScaleFactor[2] updated when status = 1 or 2. ... The scale factor in MEP_ScaleFactor[16] updated when status = 1 or 2.
MEP_ScaleFactor[0] is a starting seed value used by the SFO software functions internally.
To use the HRPWM feature of the ePWMs, it is recommended that the SFO functions in TI_Build_V5.lib be used as described here. The examples below are specific to the TMS320F28044 device, which includes a maximum of 16 HRPWM channels. For different devices which may have fewer HRPWM channels, modifications will be required in Step 1 and Step 2 below.
36
www.ti.com
Software Usage
Step 1. Add "Include" Files The SFO_V5.h file needs to be included as follows. This include file is mandatory when using the SFO V5 library functions. For the TMS320F28044 device, the C2804x C/C++ Header Files and Peripheral Examples (literature number SPRC324) DSP2804x_Device.h and DSP2804x_PWM_defines.h files are necessary as will, as they are used by all TI software examples for the device. These file names will change in accordance with your specific device. These include files are optional if customized header files are used in the end application. See example below. Example 1. A Sample of How to Add "Include" Files
//DSP2804x Headerfile //init defines //SFO V5 lib functions (needed for HRPWM)
Step 2. Define Number of HRPWM Channels Used In the SFO_V5.h file, the maximum number of HRPWM's used for a peticular device must be defines. PWM_CH must equal the number of HRPWM channels plus one. For instance, for the TMS320F28044 where there are 16 possible HRPWM channels, PWM_CH can be set to 17. For the TMS320F2809, where there are 6 possible HRPWM channnels, PWM_CH can be set to 7. See example below. To save static variable memory, fewer than the maximum number of HRPWM channels may be defined with some caution. To do this, PWM_CH can be set to the largest ePWM channel number plus one. For instance, if only ePWM1A and ePWM2A channels are required as HRPWM channels, PWM_CH can be set to 3. However, if only ePWM15A and ePWM16A channels are required as HRPWM channels, PWM_CH must still be set to 17. Example 2. Defining Number of HRPWM Channels Used (Plus One)
//SFO_V5.H //NOTE: THIS IS A VERY IMPORTANT STEP> PWM_CH MUST BE DEFINED FIRST BEFORE //BUILDING CODE #define PWM_CH //F28044 has a //For a device //For a device //For a device 17 maximum of 16 HRPWM channels (17=16+1) with maximum of 6 HRPWM channels, PWM_CH = 7 with maximum of 4 HRPWM channels, PWM_CH = 5 with maximum of 3 HRPWM channels, PWM_CH = 4
Step 3. Element Declaration Declare an array of integer variables with a length equal to PWM_CH, and an array of pointers to EPWM register structures. The array of pointers will include pointers for up to 16 EPWM register structures plus one dummy pointer in location EPWM[0] for a device with 16 EPWM channels. Likewise, it will include pointers for up to 3 EPWM register structures plus one for a device with three EPWM registers. Example 3. Declaring Elements Required by SFO_TI_Build_V5.lib
int MEP_ScaleFactor[PWM_CH] = {0,0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0}; //Scale factor values for ePWM 1-16 //and MEP_ScaleFactor[0] //For Fewer HRPWM channels, these //will be fewer zeros initialized
//Declare a volatile array of pointers to EPWM register structures. //Only point to registers that exist. If a device has only 6 EPWMs (PWM_CH is 7), //the array will include pointers for up to 6 EPWM register structures plus one //dummy pointer in the ePWM[0] location. volatile struct EPWM_REGS *ePWM[PWM_CH] {0, &EPwm1Regs, &EPwm2Regs, &EPwm3Regs, &EPwm4Regs, &EPwm5Regs, &EPwm6Regs, &EPwm7Regs, SPRU924F April 2005 Revised October 2011 Submit Documentation Feedback SFO Library Software - SFO_TI_Build_V5.lib 37
Software Usage
&EPwm8Regs, &EPwm9Regs, &EPwm10Regs, &EPwm11Regs, &EPwm12Regs, & EPwm13Regs, &EPwm14Regs, &EPwm15Regs, &EPwm16Regs};
www.ti.com
38
www.ti.com
Software Usage
Step 4. MEP_ScaleFactor After power up, the SFO_MepEn_V5(n) function needs a typical scale factor starting seed value in MEP_ScaleFacter[0]. This value can be conveniently determined using one of the ePWM modules to run the SFO_MepDis_V5(n) function prior to initializing the PWM settings for the application. The SFO_MepDis_V5(n) function does not require a starting scale factor value. As part of the one-time initialization code prior to using MEP_ScaleFactor, include the following: Example 4. Initializing With a Scale Factor Value
//MEP_ScaleFactor varaibles initialized using function SFO_MepDis_V5 Uint16 i; for(i=1; i<PWM_CH; i++) // for channels 1-16 { while (SFO_MepDis_V5(i) == 0); // Calls MepDis unitl MEP_ScaleFactor updated } // initialize MEP_ScaleFactor[0] with a typical // MEP seed value // required for SFO_MepEn_V5 MEP_ScaleFactor[0] = MEP_ScaleFactor[1]; }
Step 5. Application Code While the application is running, fluctuations in both device temperature and supply voltage may be expected. To be sure that optimal scalee factors are used for each ePWM modules, the SFO function should be re-run periodically as part of a slower background loop. Some examples of this are shown here in the below example. Example 5. SFO Function Calls
main() { Uint16 current_ch = 1; Uint16 status; // // // user code Case 1: all ePWMs are running in HRPWM mode here, the minimum duty cycle limitation is 6 clock cycles status = SFO_MepEn_V5(current_ch); if(status == 1) { current_ch++; } else if( status == 2) { error(); } if(current_ch == PWM_CH) { current_ch=1; } // // // // // // // // MepEn called here // if MEP_ScaleFactor has been updated // move on to the next channel // if MEP_ScaleFactor differs from // MEP_ScaleFactor[0] seed by more than // +/-15, flag an error // if last channel has been reached // go back to channel 1
Case 2: All ePWMs except one are running in HRPWM mode. One of the ePWM channels (ePWM16 in this example is used for SFO_MepDis_V5 scale factor calibration. Here, the minimum duty cycle limitation is 3 clock cycles. HRPWM diagnostics circuitry is used to estimate the MEP steps with the assumption that all HRPWM channels behave similarly though they may not be identical while( SFO_MepDis_V5(16) == 0); //wait until MEP_ScaleFactor[16] updates SFO Library Software - SFO_TI_Build_V5.lib 39
Software Usage
for(i=1; i<(PWM_CH-1); i++) //update scale factors for ePWM 1-15 { MEP_ScaleFactor[i] = MEP_ScaleFactor[16]; }
www.ti.com
NOTE: See the hrpwm_sfo_v5 example in your device-specific Header Files and Peripheral Examples software package available on the TI website.
40
www.ti.com
Revision History
41
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TIs terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TIs standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional restrictions. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonably be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in such safety-critical applications. TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use. TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated products in automotive applications, TI will not be responsible for any failure to meet such requirements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Audio Amplifiers Data Converters DLP Products DSP Clocks and Timers Interface Logic Power Mgmt Microcontrollers RFID OMAP Mobile Processors Wireless Connctivity www.ti.com/audio amplifier.ti.com dataconverter.ti.com www.dlp.com dsp.ti.com www.ti.com/clocks interface.ti.com logic.ti.com power.ti.com microcontroller.ti.com www.ti-rfid.com www.ti.com/omap www.ti.com/wirelessconnectivity TI E2E Community Home Page e2e.ti.com Applications Communications and Telecom www.ti.com/communications Computers and Peripherals Consumer Electronics Energy and Lighting Industrial Medical Security Space, Avionics and Defense Video and Imaging www.ti.com/computers www.ti.com/consumer-apps www.ti.com/energy www.ti.com/industrial www.ti.com/medical www.ti.com/security www.ti.com/space-avionics-defense www.ti.com/video
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright 2011, Texas Instruments Incorporated