EXPERIMENT #2 & #3 HIERARCHICAL DESCRIPTION OF COMBINATIONAL LOGIC (ADDERS, DECODERS, ENCODERS, MULTIPLEXERS) WITH MULTIBIT SIGNALS

2.1 OBJECTIVE This laboratory exercise will build on the design entry knowledge acquired in the first lab to design more advanced combinational circuits. 1-bit full adder will be designed in the first part of the experiment using behavioral description in contrast to the design entry method in Lab 1 using logic functions. This will then be extended to a 4-bit adder through hierarchical (structural) VHDL design. In the second part of the experiment, a decoder will be designed to display some letters at the 7-Segment LEDs on DE0 Demo Board. A priority encoder will be implemented next to encode the number of 8 active inputs into a 3-bit binary number using behavioral constructs. Finally, all of the VHDL design modules from the three parts will be integrated into a more complex combinational design with the assumption that output resources (7-Segment LEDs) are limited, and are therefore shared between the adder, HEX decoder, and encoder through multiplexing logic. 2.2 PRELIMINARY WORK 2.2.1 2.2.2 Read through Section 2.3 and 2.4 to learn about some of the VHDL behavioral modeling constructs, and hierarchical schematics with multibit signals. 4-bit Ripple Carry Adder: Use the symbol in Figure 2.2.1(a) for 1-bit full adder, and indicate how you would interconnect four of such adders in order to build a 4-bit ripple carry adder for which a symbol is provided in Figure 2.2.1(b). a b x(3:0) y(3:0)

cout

cin

cout

cin

a)

sum

b)

s(3:0)

Figure 2.2.1 (a) 1-bit full adder symbol, (b) 4-bit ripple carry adder symbol 2.2.3 Use your answer to 2.2.2 above to fill in the missing portions of the code provided for the 4-bit ripple carry adder in 2.3.4. The missing portions are annotated as (fill in prelab). HEX Decoder: Use combinational logic design principles to design a 7-Segment Display decoding logic such that when a number is entered between 0 and 15, the number will show up in hex representation on the display HEX0. For example, when the user enters 1, two of the vertically aligned 7-Segment Display LEDs should light up. Similarly number 2 should light up five of the LEDs. Please optimize your logic as much as possible to yield the lowest cost i.e. lowest number of input switches, gates, literals, and gate inputs. Input-to-Output delay is not a concern in this application.

2.2.4

METU Northern Cyprus Campus

EEE 248/CNG 232

Spring 2012

Hint: Remember the 7-Segment Display on DE0 board is characterized by 8 independent active low outputs (including the dot in the lower right) that need to be all defined to determine the displayed character, as depicted in Table 2.2.1. Table 2.2.1. Mapping of DE0 HEX0 7-Segment Display to HEX Decoder HEX Value 0 1 2 3 F 2.2.5 2.2.6 A on off on B C D E on on on on on on off off on off on on on off off off on F on off off G off off on DP off off off

on on off

Write a VHDL code to implement the decoder module designed in Section 2.2.4. Priority Encoder: Use combinational logic design principles to design a 8-to-3 priority encoder with an additional valid (V) bit. For example, when the highest priority input is turned ON (1), the three output LEDs should encode 7 in binary, regardless of the values of the other inputs. The valid bit should turn on as long as at least one input is ON. Output should display 0 in binary and V=1, when the lowest priority input is turned ON and no other input is ON. Please optimize your logic as much as possible to yield the lowest cost i.e. lowest number of input switches, gates, literals, and gate inputs. Input-to-Output delay is not a concern in this application. Write a VHDL code to implement the encoder module designed in Section 2.2.6. Mode Multiplexer: Design multiplexing logic such that the outputs from the ripple carry adder of 2.2.3, HEX decoder of 2.2.5 and priority encoder of 2.2.7 can share the 7-Segment Display. Introduce a Mode input (2 bits) in order to switch back and forth between the four sets of outputs as indicated in Table 2.2.2. The fifth (cout) bit of the addition result should map to the DP LED at the bottom right of the display. Table 2.2.2. Operation of 4 display modes Mode[1..0] 0 1 2 3 7-Segment Display (no LED should be on) Ripple Carry Adder Output HEX Decoder Output Priority Encoder Output

2.2.7 2.2.8

It is sufficient to show the multiplexer symbol in the answer, and label all the inputs and outputs. 2.2.9 Write a VHDL code module to implement the multiplexer designed in Section 2.2.8.

2.2.10 Complete Design: Draw the schematic of the combined logic including the four modules: 4-bit ripple carry adder, HEX decoder, Priority Encoder and the Multiplexer. Each module should be represented using a symbol (box) without showing its internals. However, input and output pins for all four modules as well as interconnections between modules should clearly be shown. 2.2.11 Make a copy of all of your VHDL codes and schematics from Preliminary Work. Your Prelim will not be made available to you after you submit it at the beginning of the lab. 2

2.3 Behavioral VHDL Code 2.3.1 Multibit Signals

A number greater than one is represented in a logic circuit using binary signals on multiple wires. Similarly, a number is represented as a multibit SIGNAL data object in VHDL. For example, a 3bit signal declaration can be done in different ways: SIGNAL A : STD_LOGIC_VECTOR (1 TO 3); SIGNAL D: STD_LOGIC_VECTOR (2 DOWNTO 0); The STD_LOGIC_VECTOR data type represents a linear array of STD_LOGIC data objects. The multibit STD_LOGIC_VECTOR declaration can be used in the same way as the single bit counterpart STD_LOGIC when defining signals within an architecture, or ports within an entity. 2.3.2 VHDL Libraries

VHDL libraries contain commonly used packages of code to make high level hardware description easier. For example std_logic_1164 library, specified during the first few lines of the VHDL code using USE command, defines std_logic data types and a few functions. It is typically included in every VHDL code. std_logic_arith is another library that allows signals to be used in integer arithmetic operations. An extension to this is std_logic_signed library to handle STD_LOGIC_VECTOR values as signed integers. e.g. S <= X+Y; Note, + in this case is used for arithmetic addition, not logic OR operation. S, X, and Y may be multibit signals previously declared using STD_LOGIC_VECTOR. There are few other libraries useful for behavioral modeling, which will not be described for now. 2.3.3 Behavioral Modeling

One of the main reasons VHDL or similar languages are popular for hardware description is the capability of behavioral modeling. Behavioral modeling allows a designer to describe hardware using high level abstractions by focusing on the desired behavior instead of details of the logic to get to that behavior. It is important to recognize that a good digital designer still needs to be very familiar with the logic derivation in order to check if the final hardware solution delivered is optimal. Below is an example of a 1-bit full adder, which takes advantage of the arithmetic libraries to describe an adder at a higher abstraction level than what was done in Lab 1 using logic functions. -- It is important to include below libraries to get behavioral -- modeling capability for arithmetic operations: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_SIGNED.ALL; -- Entity declaration with ports entity add1bit is Port ( cin : in STD_LOGIC; a : in STD_LOGIC; b : in STD_LOGIC; cout : out STD_LOGIC; sum : out STD_LOGIC); end add1bit; 3

-- Architecture name is picked to indicate this is a behavioral model: architecture Behavior of add1bit is -- This is an internal signal, which does not go to any port: signal int_sum: STD_LOGIC_VECTOR(1 DOWNTO 0); begin int_sum <= ('0' & a) + b + cin; sum <= int_sum(0); cout <= int_sum(1); end Behavior; In the above example ('0' & a) is concatenation of bit 0 with signal a in order to extend the signal from 1 bit to 2 bits before doing the addition. VHDL requires that at least one of the operands of an arithmetic expression has the same number of bits as the result. ('0' & a) has 2 bits as does the result int_sum. There are many other operations associated with the std_logic_signed library, in addition to +, which can be used in a similar manner: arithmetic: (+, -, *), comparison: (<, <=, >, >=, =, /=) shift: (shl, shr) 2.3.4 Structural (Modular) Coding

Structural or modular coding refers to first creating modules of logic blocks that are functionally independent of each other, and then stitching up these blocks into a circuit with a more complex overall function. One method of doing such hierarchical design in VHDL is shown in the below example where 1-bit full adders are used to build a 4-bit ripple carry adder: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity add4bit is Port ( cin : in STD_LOGIC; x : in STD_LOGIC_VECTOR (3 downto 0); y : in STD_LOGIC_VECTOR (3 downto 0); s : out STD_LOGIC_VECTOR (3 downto 0); cout : out STD_LOGIC); end add4bit; architecture Structure of add4bit is -- declare internal signals used to interconnect 1-bit adders: signal c1, c2, c3 : STD_LOGIC; -- declare the component to be used in this architecture: component add1bit Port ( cin : in STD_LOGIC; a : in STD_LOGIC; b : in STD_LOGIC; cout : out STD_LOGIC; sum : out STD_LOGIC); end component;

begin -- Instantiate 1-bit adder four times and interconnect: stage0: add1bit port map(cin,x(0),y(0),c1,s(0)); stage1: (fill in prelab) stage2: (fill in prelab) stage3: (fill in prelab) end Structure; The signals declared above preceding the BEGIN keyword in the architecture (c1, c2, c3) are used as carry-out signals from the first three stages of the adder. The next statement is called a component declaration statement, and uses syntax similar to that in an entity declaration. This statement allows the add1bit entity to be used as a component (subcircuit) in the architecture body. The 4-bit adder is described using four instantiations of the 1-bit adder. Each instantiation statement starts with an instance name (stage0, stage1, etc.), which can be any legal VHDL name followed by the colon character. The names must be unique. The colon is followed by the name of the component, add1bit, and then the keyword port map. The signal names in the add4bit entity that are to be connected to each input and output port on the add1bit component are then listed. The signals are listed in the same order as in the add1bit component declaration statement. Alternatively the signals can be listed in other orders by explicitly specifying which signal is to be connected to which port of the component. For example, the first instantiation in the code could be written as: stage0: add1bit port map(b=>y(0),sum=>s(0), cin=>cin,a=>x(0),cout=>c1); 2.3.5 Behavioral Constructs for a Multiplexer

2.3.5.1 Selected Signal Assignment A selected signal assignment allows a signal to be assigned one of several values, based on a selection criterion. The description of a 2-to-1 multiplexer has been provided as an example: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity mux2to1 is Port ( w0,w1,s f end mux2to1; : in STD_LOGIC; : out STD_LOGIC);

architecture Behavior of mux2to1 is begin WITH s SELECT f <= w0 WHEN 0, w1 WHEN OTHERS; end Behavior; VHDL syntax requires that a WHEN clause must be included for every possible value of the selection signal s. Since this signal has the STD_LOGIC type, possible values include 0, 1, Z, -, and others. The keyword OTHERS provides a convenient way of accounting for all logic values that are not explicitly listed in a WHEN clause. The selected signal assignment also facilitates the implementation of any type of decoder. A sample decoder truth table is provided below in Table 2.3.1, followed by the VHDL implementation.

Table 2.3.1. 2-to-4 decoder example S(1:0) 00 01 1X library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity mydecoder is Port ( S : in STD_LOGIC_VECTOR (1 downto 0); A : out STD_LOGIC; B : out STD_LOGIC; C : out STD_LOGIC; D : out STD_LOGIC); end mydecoder; architecture Behavior of mydecoder is begin WITH S SELECT (A,B,C,D) <= std_logic_vector(0001) WHEN 00, std_logic_vector(0010) WHEN 01, std_logic_vector(1000) WHEN OTHERS; end Behavior; 2.3.5.2 Conditional Signal Assignment A conditional signal assignment allows a signal to be set to one of several values, similar to the selected signal assignment. Below is an alternative architecture to describe the 2-to-1 multiplexer in the previous section: architecture Behavior of mux2to1 is begin f <= w0 WHEN s=0 ELSE w1, end Behavior; 2.4 Hierarchical Schematic Entry with Multibit Signals Modular design entry in VHDL has been described in Section 2.3.4. Similarly, multiple schematic or VHDL design modules can be pulled together in the schematic capture tool using their symbols. 2.4.1 Symbol Creation A 0 0 1 B 0 0 0 C 0 1 0 D 1 0 0

Once a design has been fully completed, choose File from Top Menu, and roll the mouse over to Create/Update selection. A side menu appears, from this menu select Create Symbol Files for Current File in order to create a symbol (.bsf file) for your design. The procedure is the same for both Schematic and VHDL design modules. 2.4.2 Module Instantiation in Schematic Capture Tool

If the design module of interest has been created as part of another project, pull it into the current project using File Open , browse and choose the relevant schematic or VHDL design file, 6

making sure that Add file to current project check box is selected. This can be repeated for all the modules that need to be pulled into the current project. The symbols created by the user can be used for the current project in same fashion as other symbols such as AND gate, OR gate, etc in schematic design. 2.4.3 Multi-bit Signal Entry in Schematic Tool

Multi-bit signals are entered using Orthogonal Bus Tool. A signal is interpreted as multi-bit only after it is labeled. Some examples of valid multi-bit signals names are: X[3..0] : A 4-bit signal named using vector notation A,B,C,D : Four 1-bit signals grouped together to form a 4-bit signal Y[4..2] : A 3-bit signal; the name implies it may be a sub-branch of the Y signal with more bits 1-bit or multi-bit signals (or I/O ports) are sometimes combined into a multi-bit signal. Quartus II schematic tool requires that a multi-bit signal and each net connected to it through a bus are all clearly labeled. One clean way to do this is to right click on the segment you need to name and select Properties. Below is an example of multi-bit signal connectivity. As observed in the figure, different bits making up the signal LED[3..0] are sourced from different single -bit signals. In the figure below (used as an example to explain multi-bit entry not part of the actual lab work but necessary to understand in order to perform the lab work) you would notice that the outputs of the register_unit are eight bits wide, whereas the input to the HexDrivers are only four bits wide. We need to rip four-bit slices from the eight-bit signals so that they can be connected to the HexDrivers. In order to do so, we first use the Orthogonal Bus Tool to draw a bus from A[7..0] output of the register_unit to the inputs of both the upper HexDrivers. Similarly, we connect B[7..0] output to the other two HexDrivers. Notice that these wires are thicker than the ones you drew before; this indicates that they are multi-bit buses. In order to rip the slices we want, we need to give these buses recognizable names. We can do so by Right-clicking on the wire segment attached to the A output and select Properties and entering A[7..0] in the Name field, then clicking OK. In order to choose the slice that will be our input to the top HexDriver, we right-click on the segment that leads to the HexDriver and select Properties. Here, entering the name A[7..4] would mean the four bits 7 downto 4 are the input for this HexDriver. Notice how Reset, LoadA, LoadB and Execute signals are merged into the LED[3..0] output. In order to do this task we first draw a bus out from the LED[3..0] output to the left, under the control unit and just under the input pins. Then we drew a wire from each of the four signals individually and labeled them. Execute segment was labeled LED[3], LoadA was labeled LED[2], LoadB was labeled LED[1] and Reset was Labeled LED[0]. This merges 1-bit signals to multi-bit signals. Similar approach can be used to merge 1-bit signals with multi-bit signals to get a larger multi-bit signal.

Figure 2.4.1 Multi-bit signal connectivity and naming example

2.5 EXPERIMENTAL WORK 2.5.1 Experimental Setup

Verify to make sure your workbench has all of the following items: - A Personal Computer (PC) with Altera Quartus II ISE 9.0 Project Navigator - DEO Demo Board with Cyclone III EP3C16F484C6 FPGA installed on a card with 10 input toggle switches, three push buttons, and four 7-Segment LED displays among other components. - A USB cable connected between the demo board and the PC using USB interface 2.5.2 4-bit Ripple Carry Adder Design, Functional and Timing Simulation

2.5.2.1 Use the full design implementation flow from Lab 1 to create a project named <your_name>_add4, enter the design using VHDL, and simulate. Remember to enter the 1bit full adder behavioral VHDL model first in the same project area, and then use instantiations of it. i) When defining the test bench waveform for functional simulation, make sure test is long enough to fit more than 10 test cycles. Use the pattern wizard to generate pseudorandom vectors for inputs x and y by right-clicking on the vector, choosing set value option, entering Pattern Wizard, and using the random bus pattern type. Pick different 8

random seeds for the inputs x and y to avoid always adding the same number (e.g. 0 for one, 3 for the other). ii) After package pin assignment, place and route steps, change test vectors as follows for the timing (post-routing) simulations (may want to also create a new test bench waveform i.e. .tbw file for this step): Assign 0000 to input x, 1111 to input y, 1 to input Cin. Then toggle each bit of the y input to 0 and back to 1, one at a time. Do the same with the Cin input. Measure the time delay between input and Cout for each case and note somewhere. iii) Once you are convinced, based on the functional and timing simulations, that your design module is correct, create a symbol for it as explained in Section 2.4.1. 2.5.2.2 Demonstrate the functional and timing simulation results from above to your lab instructor, after completing all of the steps up to 2.5.2.1(iii). Which input pin has the maximum input-to-output delay based on your experiment in (ii)? Why do you think this is the case? Be ready to comment on this to your lab instructor when you do your demonstration. 2.5.3 HEX Decoder Design, and Simulation

2.5.3.1 Create a project named <your_name>_decode, enter the decoder design using VHDL, and simulate functionality using the input combinations in Table 2.2.1. i) You do not need to do package pin assignments, place and route, or hardware programming for this design. ii) After you check the functionality of the design module, remember to create a symbol for it. 2.5.3.2 Demonstrate the functional simulation results from above to your lab instructor, after completing all of the steps up to 2.5.3.1(ii). 2.5.4 Priority Encoder Design, and Simulation

2.5.4.1 Create a project named <your_name>_encode, enter the priority encoder design using VHDL, and simulate functionality. Ensure you verify all input scenarios with a unique output. i) You do not need to do package pin assignments, place and route, or hardware programming for this design. ii) After you check the functionality of the design module, remember to create a symbol for it. 2.5.4.2 Demonstrate the functional simulation results from above to your lab instructor, after completing all of the steps up to 2.5.4.1(ii). 2.5.5 Multiplexer Design, and Simulation

2.5.5.1 Create a project named <your_name>_mux, enter the multiplexer design using VHDL, and simulate functionality using all four modes in Table 2.2.2. i) Generate the input vectors for the functional simulation using the random vector assignment described in Section 2.5.2.1. ii) You do not need to do package pin assignments, place and route, or hardware programming for this design. iii) After you check the functionality of the design module, remember to create a symbol. 2.5.5.2 Demonstrate the functional simulation results from above to your lab instructor, after completing all of the steps up to 2.5.5.1(iii). 9

2.5.6

Complete Combinational Design, Simulation, and Implementation

2.5.6.1 Create a project named <your_name>_combo, enter the complete combinational design using Schematic Capture, simulate, program to FPGA, and test. i) Use the description of Section 2.4.2 to pull in all the previous design modules into the current project. ii) Instantiate the symbols for the design modules, interconnect, and assign I/O ports. Pay attention to multi-bit vs. single-bit wires and naming conventions as described in 2.4.3. iii) Replicate input vectors used in previous module simulations to fully check the functionality of the complete design in all of the four different operation modes. iv) Ensure in functional and timing simulations that your design works correctly before programming to the FPGA. Then program, and test the same vectors as in (iii) above to make sure you get the same results as your functional simulations. If you do not have sufficient number of switches to implement your inputs, remember you can also take advantage of push buttons on DE0 board as inputs. 2.5.6.2 Demonstrate the functional simulation and hardware test results from above to your lab instructor, after completing all of the steps up to 2.5.6.1(iv). REFERENCES: Fundamentals of Digital Logic with VHDL Design, 2nd Edition, Stephen Brown & Zvonko Vranesic, McGraw-Hill, 2005

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