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School of Engineering Analogue and Mixed Signal CMOS Design

Literature survey

Flash ADC

Flash ADC
Introduction Analog to digital conversion is an important step in most kinds of electronic systems, including signal processing, communication and storage. There are many kinds of analog to digital conversion systems for example, Sigma delta ADC, Successive approximation ADC And Flash ADC [1]. This literature survey will focus on Flash ADC, its definition, architecture, advantages and disadvantages , and recent research about it. Flash ADC is also known as parallel ADCs and a direct conversion ADC [1]. It is the fastest kind of all Analog to digital converters and the simplest one because it uses the parallelism and sampling method [2]. The circuit of this kind is formed of reference ladder resistors, comparators and an encoder see figure (1). In essence, every N bit flash ADC consist of 2N of ladder resistors of the same value and 2N -1 comparators [2]. For instance, figure (1) shows a 3-bit flash ADC circuit which has 23=8 resistors , 23-1=7 comparators and an encoder. This means the number of bits (N) equal to the numbers of output bits.

Figure 1

Considering what the Flash ADC consists of, let us look at how this circuit works. Firstly, considering a 3-bit flash ADC as an example, which according to the above figure means there will be 7 comparators that compare the input voltage with the reference-voltage at each node as a result of potential dividers formed by 8 resistors (see figure 1). Moreover, the reference voltage for each comparator represents a single least significant bit (LSB) higher than the reference-voltage for the comparator directly below it [3]. The output of each comparator shows only two values depending on its inputs, when the input voltage is higher than the reference-voltage, the comparator then saturates to high. In addition, when the input voltage is less than the reference voltage then the comparator output saturates to low. This method applies to all comparators in the circuit. Secondly, the outputs of the comparators go into the encoder that translates their values to binary digits which are 0 or 1[1,2,3]. Figure 2 gives a good example to clarify the work principle of the circuit. It shows the reference voltage for each node which are V1 from the bottom to V7 at the top. Suppose applying an analog voltage (Vin) with its value higher than the voltage reference V5 and less than V6, then the positive inputs of the comparators 1 to 5 will be higher than the negative inputs so the comparators1 to 5 outputs saturate at high and the rest of the comparators 6 and 7 will output low because the reference voltage at their negative inputs is higher than Vin at the positive inputs. Finally, the encoder transfers comparator outputs to binary digits 101(5 in decimal) at its output.

Advantages and disadvantages. The flash ADC provides a fast conversion time because of the parallel process so it is the fastest system of all ADC systems [3]. Similarly, as seen above, it is not complicated to build, because it needs only an encoder for the last conversion to binary. Moving to drawbacks of flash ADC, it involves a high number of comparators ,for example, 3-bit of output requires 8 comparators and 8 bits would require 2N-1=28-1=255 comparators that means

it will need a huge silicon die and consume a lot of power [2]. This increase in comparators numbers leads to a large capacitance in the input.

Recent Research work According to Sreehari et al, with programmable resolution based upon the analogue input peak voltage, a low powered flash ADC design will operate with high speed [4]. This flash ADC has the ability to operate with a higher speed, lower resolution while consuming minimum power. There is a big advantage of the proposed ADC as it has a built in peak detector which will detect the peak input signal level. It provides comprehensively a programmable feature of true variable-power and variable-resolution. They proposed that in case of receiving strong signals the resolution of the ADC can be reduced and can be increased upon receiving low signals [4].

He Tang, Hui Zhao et al, describe their research about flash ADC which they took from a different angle of quantitative design methodology for capacitive interpolated flash ADC that it draws a design matrix which links it with architecture, block circuit, devices and process parameters [5]. They believe that this technique provides a comprehensive analysis of bottom-up flash ADC design while addressing the general ADC performance specs including dynamic power analysis. They elaborate in their conclusion that though this type of quantitative flash ADC design methodology does not exist yet but it is reported that discussions are widely taken place to accomplish such goals.

Damir Ferenci, Simon Mauch and their fellow researchers consider that a 3bit 36 GS/s Flash ADC with a large analog input has given a high sampling rate as employed with a fourfold parallelisation [6]. According to these researchers, the power consumption of the ADC core is 2.6 W and its basic intention is cost effective integration as it has an equaliser circuit on a single CMOS chip. They believe that it is not faster than the 8 bit 56 GS/s CMOS ADC but it has the most smallest chip area ever recorded. This ADC is hundred times smaller than the currently fastest one. They presented in this paper a detail discussion with linearity and SNDR measurement results up to 36GS/s.

Mohammed O. Shaker, Sumik Gosh and his peers proposed a new design of Flash ADC with a low power quality [7]. They presented a design and simulation results of a low voltage ADC i.e. 6-bit CMOS. Its speed is 1 GHz and it is implemented in an analog supply voltage of 1.2 V. The proposed Flash ADC's consumption is about 72 mW in a commercial 90 nm CMOS process. If compared with the traditional flash ADC, it offers lower number of comparators and consumes lower power. They believe that this architecture can be extended to high resolution applications because of the simplicity of the circuit.

A research taken by Denis C. Daly and Anantha P. ChandraKasan in which they carried out an implementation of a 6-bit highly digital ADC in a 0.18 m CMOS process [8]. The flash ADC not only employs comparator redundancy and reconfiguration to improve linearity but it operates in a subthreshold regime down to 200 mV. In this research they presented a highly digital flash ADC which can operate from supply voltages of 200 mV to 900 mV. They are of the view that this architecture due to its redundancy and reconfigurability of the comparator array it can tolerate large comparator and voltage offsets.

Conclusion Flash ADC is the fastest kind of analog-to-digital conversion and many applications include this kind of ADC for example in communications etc. This ADCs system structure has three main parts which are ladder resisters, comparators and an encoder. Moreover, the number of comparators and resistors depend on the number of output bits. Although Flash ADC has advantages, such as its speed, it has also disadvantages such as the huge number of comparators when apply more output bits. Finally, there is a lot of research conducted about this system, which aims to develop it in order to get simpler and faster, less cost and low power consumption circuits than what is available now.

[1] R.V. Plassche, 2003. CMOS Integrated Analog-to-Digital and Digital-to-Analog Converters, 2nd Edition. Dordrecht: Kluwer Academic Publishers. [2] B. Razavi, 1995. Principles of Data Conversion System Design. New York: WILLY-IEEE Press. [3] wikipedia [4] S. Veeramachanaen, A.M. Kumar, V. Tummala, M.B. Srinivas, 2009, Design of a Low Power, Variable-Resoluation Flash ADC, Center for VLSI and Embedded System Technology, San Jose State University, 1063-9667/09 2009 IEEE. [5] H. Tang, H. Zhao, X. Wang, L. Lin, Q. Fang, J. Liu and A. Wang, 2010, Capacitive Interpolated Flash ADC Design Technique, Dept. of EE, University of California, 978-1-4244-8631-1/10 2010 IEEE. [6] Damir Ferenci, Simon Mauch, Markus Grozing, Fleix Lang, Manfred Berroth, 2011, A 3 bit 36GS/s Flash ADC in the 65 nm Low Power CMOS Technology, Institute of Electrical and Optical Communications Engeering, University of Stuttgart , 97 8-612854-865-5 2011IEEE [7] M.O. Shaker, S. Gosh, and M.A. Bayoumi, 2009, A 1-GS/s 6-bit Flash ADC in 90 nm CMOS, The Center For Advanced Computer Studies, University of Louisiana, 978-1-4244-4480-9/09 2009 IEEE. [8] D.C. Daly, and A.P Chandrakasan, 2009, A 6-bit, 0.2 V to 0.9 V Highly Digital Flash ADC With Comparator Redundancy, IEEE Journal of 44.11(2009): 3030-3038. 2009 IEEE.