TEA5170

SWITCH MODE POWER SUPPLY SECONDARY CIRCUIT

. . . . . . . . . . .

INTERNAL PWM SIGNAL GENERATOR POWER SUPPLY WIDE RANGE 4.5V 14.5V SOFT START REFERENCE VOLTAGE 2V 5% WIDE FREQUENCY RANGE 250kHz MINIMUM OUTPUT PULSE WIDTH 500nS MAXIMUM PRESET DUTY CYCLE SYNCHRONIZATION WINDOW OUTPUT SWITCH UNDERVOLTAGE LOCKOUT FREQUENCY RANGE WITH SYNCHRONIZATION 64kHz

DIP8 (Plastic Package) ORDER CODE : TEA5170

DESCRIPTION The TEA5170 is designed to work in the secondary part of an off-line SMPS, sending pulses to the slaved TEA2260/61 which are located on the primary side of the main transformer. An accurate regulated voltage is obtained by duty cycle control. The TEA5170 can be externally synchronized by higher or lower frequency signal, then it could be used in applications like TV set ones. For more details, refer to application note AN408/0591. PIN CONNECTIONS

SOFT-START CAPACITOR SUPPLY VOLTAGE POWER OUTPUT

CSF V CC P OUT

1 2 3 4

8 7 6 5

RT CT

OSCILLATOR RESISTOR OSCILLATOR CAPACITOR

GROUND GND

E OUT VOLTAGE ERROR AMPLIFIER OUTPUT VOLTAGE ERROR AMPLIFIER E INVERTING INPUT
5170-01.EPS

September 1993

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TEA5170
BLOCK DIAGRAM
Rt 8 Comparator Ct 7
OSCILLATOR LOGIC (SYNCHRO) POWER OUTPUT STAGE

2.7V

Csf 1

SOFT START AND DUTY CYCLE LIMITING

PWM

LOGIC

Error Amplifier E- 5
x -1 PWM

2V

V CC Monitor
6 Eout 4 GND 2 V CC 3 P out
5170-02.EPS

ABSOLUTE MAXIMUM RATINGS

Symbol VCC Tj Tstg Supply Voltage Operating Junction Temperature Storage Temperature Range Parameter Value 15 150 40, + 150 Unit V C C
5170-01.TBL 5170-03.TBL 5170-02.TBL

THERMAL DATA
Symbol Rth (j-a) Parameter Junction-ambient Thermal Resistance Value 90 Unit C/W

RECOMMANDED OPERATING CONDITIONS

Symbol VCC RT CT Fosc Fsy Tamb VRT VCT ISOURCE Power Supply Voltage Timing Resistor Timing Capacitor Oscillator Frequency Synchro Frequency Operating Ambient Temperature Voltage on Pin RT (8) Current on Pin CT (1) Output Current 30 Parameter Min. 5 47 0.12 12 12 20 Typ. Max. 14 180 1.8 250 64 70 7 100 60 Unit V k nF kHz kHz C Volt A mA

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TEA5170
ELECTRICAL CHARACTERISTICS (TA = 25oC, VCC = 12V, unless otherwise specified)
Symbol OSCILLATOR TA TB FOSC (T) Frequency drift due to ambient o o temperature variation from 0 C to 70 C FOSC (70oC) FOSC (0oC) 70 C x FOSC (25 C) Frequency drift due to VCC variation from 5V to 12V FOSC (12V) FOSC (5V) 7V x FOSC (12V) Input Bias Current Voltage Gain Gain Bandwidth Slew Rate Voltage Reference VREF (12V) VREF (5V)
o
o

Parameter Free Period

Test Conditions RT = 100k 0% CT = 1.2nF 0%, Vcc = 12V RT = 100k 0% CT = 560pF 0%, Vcc = 12V RT = 100k 0% CT = 1.2nF 0%, Vcc = 12V

Min.

Typ.

Max.

Unit S S %/C

60.40 65.60 70.80 29.18 31.70 34.22 0.01

FOSC (VCC)

RT = 100k 0% CT = 1.2nF 0%

0.07

%/V

ERROR VOLTAGE AMPLIFIER (VCC = 12V) Ibias Gvol GB Ein = 2V 0 0.2 80 2 2 2 0.4 0.2 1 A dB MHz V/s V mV/V mV/

INTERNAL VOLTAGE REFERENCE VREF Using the voltage error amplifier as a follower 1.9 3 2.1 3

VREF (VCC) Line Regulation VREF (T)

7V

VCC = 5V to 12V TA = 0C to 70C

VREF drift with temperature VREF (70oC) VREF (0oC) 70oC

TON MIN TONMIN A TONMIN B Minimum Duty Cycle Minimum Duty Cycle Ct = 1.2nF 0% Rt = 100k 0% Ct = 560pf 0% Rt = 100k 0% Iload = 1mA Iload = 1mA VPOUT = 3V VPOUT = 3V 1.77 1.04 2.53 1.49 3.29 1.94 s s

POWER OUTPUT STAGE VPOUTH VPOUTL ISINK ISOURCE Ftrig Max Vtrig Ttrigp Wtrig + Wtrig SOFT START
5170-04.TBL

Output High Level Output Low Level Sink Current Source Current Maximum Synchro Frequency Synchro Triggering Threshold Synchro Triggering Pulse Width Ttrig+ TO Positive Triggering Window

6.3 0.5 30 30 64

6.9 0.8 60 110

7.5 1.1 190 190

V V mA mA kHz V nS % %

SYNCHRONISATION 2.7 at VRT = 2.7Volt (fig 5) CT = 1.2nF 0% RT = 100k 0% CT = 1.2nF 0% RT = 100k 0% Vcsf = 1V Vcs > 2.5V, VCC = 12V CT = 1.2nf 0% RT = 100k 0% 800 25 9 35 29 40 42 3

TO

Negative Triggering Window

TO Ttrig

TO

Icsf Donmax

*Csf Load Current Maximum Duty Cycle

2.5 60

3.7 78

6 95

A %

*Csf is a high impedance capacitor

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TEA5170
ELECTRICAL CHARACTERISTICS (TA = 25oC, VCC = 12V, unless otherwise specified) (continued)
Symbol VCC MONITOR VSTART VHYST VSTOP ICC Turn-on Threshold Hysteresis Voltage Turn-off Threshold Supply Current RT = 100k 0%, CT = 1.2nf 0% No Load on Pin 3, VCC = 12V 3.60 100 3.50 7 4 4.40 V mV V mA
5170-05.TBL 5170-04.EPS

Parameter

Test Conditions

Min.

Typ.

Max.

Unit

TOTAL DEVICE 12 25

GENERAL DESCRIPTION The TEA5170 takes place in the secondary part of an isolated off-line SMPS. During normal mode operation, it sends pulses to the slave circuit located in the primary side (TEA2164, TEA2260/61) through a pulse transformer to achieve a very precisely regulated voltage by duty cycle control. The main blocs of the circuit are : - an error voltage amplifier - an RC oscillator - an output stage - a VCC monitor - a voltage reference bloc - a pulse width modulator - two logic blocs - a soft start and Duty cycle limiting bloc PRINCIPLE OF OPERATION The TEA5170 sends pulses continuously to the slave circuit in order to insure a proper behaviour of the primary side. - According to this, the output duty cycle is varying between DON (min.) (0.05) and DON (max.) (0.75) : then even in case of open load, pulses are still sent to the slave circuit. Figure 1 : Basic Concept
MASTER-SLAVE ARCHITECTURE

ASYNCHRONIZED MODE (Figure 2) The regulated voltage image is compared to 2V vol-tage reference. The error voltage amplifier output and the RC oscillator voltage ramp are applied to the internal Pulse Width Modulator Inputs. The PWM logic Output is connected to a logic bloc which behaves like a RS latch, sets by the PWM output and resets when Ct downloading occurs. Finally, the push-pull output bloc delivers square wave signal whom output leading edge occurs during Ct uploading time, and output trailing edge at Ct downloading time end. The duty cycle is limited to 75% of oscillator period as maximum value and to Ct downloading time/oscillator period as minimum value (Figure 2). Figure 2
V2 Vt V1
max.

OSCILLATOR RAMP

POWER OUTPUT

T1 Ton max.

T2 = Ton min.

MASTER CIRCUIT SLAVE CIRCUIT

SYNCHRONIZED MODE (see Figure 3) The TEA5170 will enter the Synchronized Mode when it receives one pulse through Rt during Ct discharge. At that time Ct charging current will be multiplied by 0.75 and period will increase up to To x 1.26. A pulse occuring during the synchro window, commands the Ct downloading. If none, the TEA5170 will return to normal mode at the end of the period.

PWM

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5170-03.EPS

TEA5170
Figure 3
UNSYNCHRONIZED MODE

SYNCHRONIZED MODE

UNSYNCHRONIZED MODE

Vct Vtsy

Vrt
5170-05.EPS

Wtrig-

Wtrig+

Remark : In case of an application between TEA5170 and TEA2164, to optimize the synchronization windows of these circuits, the following relations have to TSYNC Tm be used : Tm = Te = 1.06 1.223 with Te : Free period of the TEA2164 oscillator, and Tm : Free period of the TEA5170 oscillator. BLOCK DESCRIPTION The error voltage amplifier inverting-input and output are accessible to use different feed-back network and allowing parasitic filtering network. The non-inverting input is internaly connected to 2V reference voltage. The RC oscillator is designed to work at high frequency (up to 250kHz). RT sets the capacitor charging current Io = 2/RT. The capacitor CT is loaded from V1 1V to V2 = 2V CT RT and then down loaded through during T1 = 1.985 an integrated resistor R2 1k during T2 = 1300 CT The ramp is used to limit the duty cycle. Then the maximum duty cycle is 1 DONMAX = (0.73 T1 + T2) T1 + T2 The output level is VCC independant when VCC is over 8V. The VCC monitoring switches the circuit on when VCC is over 4V and switches it off when under 3.8V. This function insures a proper starting procedure (made by the primary side circuit). SYNCHRONIZATION (see Figures 4 and 5)

Figure 4 : Triggering Schematic

VCC

7 Ct 1k from logic

2.7V 8 Network Rt 2.7V + 5170-06.EPS

towards logic

Figure 5 : Typical Waveforms

Vct

1V T trigP Vrt 2V
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5170-07.EPS

2.7V

TEA5170
STARTING When VCC is under 4V, output pulses are not allowed and the slave circuit keeps its own mode. When VCC is going over 4V, output pulses are sent via the pulse transformer (or an optical device) to the slave circuit which is synchronizing and entering the slaved mode. Output pulses can be shut down only if VCC goes below 3.8 Volt. Figure 6 : Soft-Start Sequence
VCC (V) 12

SOFT START Using Csf, it is possible to make a soft start sequence. When VCC grows from 0V to 4V, voltage on Csf equals 0V. When VCC is higher than 4V, Csf is loaded by a 3.7A current, then TonMAX (Vcsf) will vary linearly from Tonmin to Tonmax according to Csfst bias. When VCC will go low (3.8 Volt threshold), Csf will be downloaded by an internal transistor.

4 t VCSF (V) 3.2 2

t Duty cycle D on max. maximum

D on min.

POWER OUTPUT STAGE Figure 7 : Electrical Schematic

VCC 1mA 1mA

3 Pout

from logic
5170-09.EPS

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5170-08.EPS

minimum

Figure 8

G4466-01 4 x BY254 3 100F (250V) P1 47k 15V 470F (25V) 2.2k 10V BY218-100 6.8 (3W) 7 BC547C 22 20V BY318-100 21 470F (40V) 3.3 nF 75k 16 17 220F 25V 1000F (25V) 10k Stand-by Control 120k 20 6 4.7 (3W) 9 14 BA157 19 BA157 13 BY218-600 135V

110 V AC 44k (2W)

20%

220F (250V)

1nF

68k

P2 22k

100nF

10

12

13

15

TEA2164
18 2 2.2F BUV56A 47F 14 10F 16V 2 4 6 5 BZX85C-3V0

11

110k 1% 1N4148 100 220 (8W) BA159

4.7F

1.2 nF 2%

16V 3

TEA5170
7 8 1 47nF

1k

1nF 0.18 (1W) 4.7nF 1kV

330

1.2 nF 2% 270

1N4148

150pF

Sync. Input 100k 1% 6.8k

100

P OUT : 90W

f : 16kHz Pulse Transformer

TEA5170

7/9

5170-10.EPS

22k

220nF

1M

220nF

56k

150k

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TEA5170
Figure 9

G4576-02 4 x 1N4007 3 100F (250V) P1 47k 12V 0.5A 120k

20 39 13

170 V AC

BY218-600

270 V AC 150F (385V) 18k (3W) PLR811 1N4148 6 2.2 (0.5W) BA157 9
BY218-100 1000F (25V) BC547C 22 10k 14 19 470F (25V)

135V 0.8A

4.7k

P2

3.3nF

1k

1nF

2.2F (16V)

7.5V 1A

2.2k

1k 6.8 (1W) 7 25V

BY218-100 1000F (40V) 17

330F 25V

Stand-by Control 1.2 nF

7 22k
21

12

13

16

15

75k

TEA2164
3 18 2.2F SGSF344 BY299 330
0.135 (1W)

11 14 BZX85C-3V0 47F 220 (16W)

10

8 1

10F 16V

1nF

TEA5170
3

7 560 pF

1
47nF

BC547C 2.7nF 1kV 1k

100

P OUT : 140W
100 pF

270

1N4148

150pF

f : 32kHz

Sync. Input 100k 6.8k

5170-11.EPS

TEA5170
PACKAGE MECHANICAL DATA 8 PINS - PLASTIC DIP
e4
A a1

b1

b Z

B B1 e e3 D Z

Dimensions A a1 B b b1 D E e e3 e4 F i L Z

Min. 0.51 1.15 0.356 0.204 7.95

Millimeters Typ. 3.32

Max.

Min. 0.020 0.045 0.014 0.008 0.313

Inches Typ. 0.131

Max.

1.65 0.55 0.304 10.92 9.75 2.54 7.62 7.62 6.6 5.08 3.81 1.52

0.065 0.022 0.012 0.430 0.384 0.100 0.300 0.300 0260 0.200 0.150 0.060

3.18

0.125

Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No licence is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. 1994 SGS-THOMSON Microelectronics - All Rights Reserved Purchase of I2C Components of SGS-THOMSON Microelectronics, conveys a license under the Philips I2C Patent. Rights to use these components in a I2C system, is granted provided that the system conforms to the I2C Standard Specifications as defined by Philips. SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - China - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.

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DIP8.TBL

PM-DIP8.EPS

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