DEPARTMENT OF ELECTRONICS & COMMUNICATION

8EC4.2: VHDL
UNIT-1 TUTORIAL SHEET NO.: 01(A)

Q1. Explain any five VHDL statements using example for each. Q2. Explain package and entity declaration.

(RU 2009) (RU 2009)

Q3. Explain dataflow style and structural style of modeling with suitable example. (RU 2011) Q4. Explain entity declaration in VHDL. Q5. Describe and write the syntax for the packages in connection with VHDL. Q6. Explain the lexical elements? Q7. Explain signals and variables in VHDL. Mention out the differences between them with suitable example. Q8. Explain different type of operators available in VHDL. Q9. Write short note on modeling with Hardware Description Language. (RTU 2011)

DEPARTMENT OF ELECTRONICS & COMMUNICATION 8EC4.2: VHDL Unit 1 TUTORIAL SHEET NO.: 1(B) Q1. Explain architecture declaration in VHDL. (RTU 2011)

Q2. Explain different modeling styles used in VHDL. A synthesis output will be in which kind of modeling style? Q3. What are FPGA ? Q4. What data types are available in VHDL? Explain in brief. Q5. What types of port modes are available in VHDL? Explain briefly. Q6. In which case will you prefer a buffer port opposed to an inout port and why?

DEPARTMENT OF ELECTRONICS & COMMUNICATION 8EC4.2: VHDL UNIT 1 TUTORIAL SHEET NO.: 01(C) Q1. Write short note on concurrent assignment statements. (RU 2008)

Q2. Define synthesis, simulation and testbench in VHDL and also differentiate them with example (at least five points) (RU 2008 back) (RU 2006)

Q3. Draw the schematic of ASIC design flow and explain every step in brief. (RTU 2011) Q4. Explain the history of various hardware description languages. Q5. Differentiate between floor planning and placement. Q6. Differentiate between FPGA and CPLD. Q7. Explain Gajskis Chart. (RTU 2011)

DEPARTMENT OF ELECTRONICS & COMMUNICATION 8EC4.2: VHDL Unit 2 TUTORIAL SHEET NO.: 01(A)

Q1. Write VHDL code for 16:1 mux using 4 x 1 MUX with package style. Draw the circuit in the block diagram form. (RU 2006) Q2. Implement F(A,B,C)= using a multiplexer. (RU 2009) (RU 2009)

Q3. Write VHDL code for the multiplexer in the above code. Q4. Apply Shannons expansion theorm to implement the function:

Using 4 to 1 mux. (RU 2008) Q5. Write VHDL code for implementation of f(A,B,C)= using MUX. (RU 2006)

Q6. Explain multiplexer synthesis using Shannons expansion and prove Shannons expansion theorm. (RTU 2011) Q7. Write VHDL code for 2 to 1 multiplexer specified using if then else statement. (RTU 2011) Q8. Draw the digital logic diagram for a VHDL code for architecture given as follows: ARCHITECTURE logic OF fa IS BEGIN s <= x XOR y XOR cin; c <= (x AND y) OR (y AND cin) OR (x AND cin); END logic; [RU-2005]

Q9. Write VHDL code for a 4 x 1 mux using selected signal assignment statement. Q10. Write the VHDL code for 8 x 1 multiplexer using case statements.

DEPARTMENT OF ELECTRONICS & COMMUNICATION 8EC4.2: VHDL Unit 2 TUTORIAL SHEET NO.: 01(B)

Q1. Implement a 4 to 16 binary decoder using 2 to 4 decoder, write its VHDL using GENERATE statement. (RU 2006) Q2. Show that the function

Can be implemented using a 3 to 8 binary decoder and an OR gate. Q3. Write VHDL code for the circuit derived in question above. Q4. Write VHDL code for the BCD to 7-segment decoder.

(RU 2008 back) (RU 2008) (RU 2009)

Q5. Implement a 3 to 8 binary decoder using 2 to 4 decoder, write its VHDL code. Q6. Write the VHDL code for 4 x 2 priority encoder. Q7. Write VHDL code for Binary to gray converter. Q8. Write VHDL code for Gray to binary converter. [ RU-2007 ]

DEPARTMENT OF ELECTRONICS & COMMUNICATION 8EC4.2: VHDL Unit 2 TUTORIAL SHEET NO.: 01(C)

Q1. Write short note on Code converter.

(RU 2009)

Q2. Write VHDL code for BCD to 7-segment decoder using CASE statement. (RU 2008) Q3. Write a package declaration fulladd-package which provides component declaration for fulladd entity. Then write VHDL code for a four bit ripple carry adder using the component fulladd defined in the above package. (RU 2008) Q4. Draw the structural diagram of a serial adder and explain each block of it with waveform. (RU 2008 back) Q5. Using conditional signal assignment statement write VHDL code for 8 to 3 encoder. (RU 2007) Q6. How will you implement a serial adder in VHDL? Q7. Write VHDL code for Binary to BCD encoder. Q8. Write VHDL code for: (RU 2007) (RU 2006) (RU 2006)

O/P

Clk Data

DEPARTMENT OF ELECTRONICS & COMMUNICATION 8EC4.2: VHDL Unit 3 TUTORIAL SHEET NO.: 01(A)

Q1. Write VHDL code for a positive edge triggered D flip flop.

(RU 2007)

Q2. Write VHDL code for T flip flop with an asynchronous clear input using behavioral style. (RU 2007) Q3. Design S-R latch using NAND gate. Also derive its truth table, VHDL code and show its timing diagram. (RU 2008 back) Q4. Write VHDL code for D flip-flop using wait until statement.(RU 2009)(RTU 2011) Q5. Write VHDL code for J-K flip-flop. (RU 2009)

Q6. Write and explain difference between level sensitive and edge triggered memory elements. Explain with timing diagram for a DFF having preset and clear provision, write its VHDL code also. (RU 2006)(RTU 2011) Q7. Write VHDL code for an n-bit NAND gate using variable assignment and FOR-LOOP. (RU 2008)

DEPARTMENT OF ELECTRONICS & COMMUNICATION 8EC4.2: VHDL UNIT 3 SEQUENCIAL CIRCUITS TUTORIAL SHEET NO.: 01(B)

Q1. Give VHDL code for 8-bit shift register. How will you include shift left and shift right operations in the circuit shift register? (RU 2007) Q2. Design 8-bit serial-in-serial-out (SISO) shift register using flip flop. (RU 2008 back) Q3. Draw the four bit parallel access shift register and write its VHDL code using GENERIC parameter. (RU 2008)(RTU 2011) Q4. Write a VHDL code for 4-bit right to left shift register with enable input. (RU 2009) Q5. Draw the block diagram of 8-bit structural barrel shifter and explain its working through waveform. Also write its VHDL code. (RU 2008 back) Q6. Write VHDL code for following ckt : (RU 2006)

Q7. Write VHDL code for n- bit register using generic statement. Q8. Write VHDL code for 4-bit register with asynchronous reset. [RU-2009]

DEPARTMENT OF ELECTRONICS & COMMUNICATION 8EC4.2: VHDL UNIT 3 SEQUENCIAL CIRCUITS TUTORIAL SHEET NO.: 01(C)

Q1. Design 4-bit up-down counter using behavior modeling. (RU 2008 back)(RTU 2011) Q2. Write the VHDL code for a 4-bit Johnson counter and also draw its timing diagram. (RU 2008 back) Q3. Draw the block diagram of a two digit BCD counter and write its VHDL code. (RU 2008) Q4. Design a 3-bit counter that counts in the sequence 0, 4, 2, 6, 1, 5, 3, 7, 0, 4 and so on. The counter counts on the pulses on the input W. (RU 2008) Q5. Design a 4-bit up counter. Show its data diagram and write VHDL code for it. (RU 2009) Q6. Write short note on Modulo-4 counter. (RU 2009)

Q7. Write VHDL code for a 3-bit up down counter using T flip flops. It should have a control input called up/dpwn. If up/down = 0, then the circuit should behave as an up counter and if up/down = 1 then the circuit should act as a down counter. (RU 2007) Q8. Write VHDL code for modulo II counter. Q9. Implement with VHDL code for timing diagram given below: (RU 2006)

Count seg. is 0 1 2 3 4 5 0 1 2 3.

(RU 2006)

DEPARTMENT OF ELECTRONICS & COMMUNICATION 8EC4.2: VHDL UNIT 4 SYNCHRONOUS/ ASYNCHRONOUS SEQUENCIAL CIRCUITS TUTORIAL SHEET NO.: 01(A)

Q1. What do you mean by FSM? Classify them. (RU 2008 back) Q2. Write difference between mealy and moore machine. Q3. Write short note on Moore type FSM. Q4. Write VHDL code for the following state diagram: (RU 2009)(RTU 2011) (RU 2009) (RU 2007) (RU 2008 back)

Q5. For the given state diagram, design the FSM and write VHDL code.

(RU 2008)

Q6. Derive a minimal state table for a Moore type FSM that produces an output of 1 if in the input sequence it detects 110 or 101 patterns. Also write the VHDL code for it. Q7. Repeat the same as given in Q.6 for Mealy type FSM.

DEPARTMENT OF ELECTRONICS & COMMUNICATION

8EC4.2: VHDL UNIT 4 SYNCHRONOUS/ ASYNCHRONOUS SEQUENCIAL CIRCUITS TUTORIAL SHEET NO.: 01(B)

Q1. Design the Mealy type FSM for a serial adder and write its VHDL code. (RU 2008) Q2. Design a sequential circuit for given table: Present State Y2 Y1 00 01 10 11 Next State W=0 Y2Y1 10 01 11 10 W=1 Y2Y1 11 00 00 01 (RU 2009) Output

0 0 0 1 (RU 2009)

Q3. Write VHDL code for mealy machine of following fig.

Q4. Write VHDL code for sequence generator. Q5. Write VHDL code for the following state diagram

(RU 2006) (RU 2006)

Q6. What do you mean by ASM charts? Q7. Derive a minimal state table for a Mealy type FSM that produces an output of 1 if in the input sequence it detects 110 or 101 patterns. Also write the VHDL code for it.

DEPARTMENT OF ELECTRONICS & COMMUNICATION

8EC4.2: VHDL UNIT 4 SYNCHRONOUS/ ASYNCHRONOUS SEQUENCIAL CIRCUITS TUTORIAL SHEET NO.: 01(C)

Q1. Write short note on Vending Machine.

(RU 2009) (RU 2006)

Q2. Design an synchronous sequential vending machine controller and make its state diagram and explain it.(No need for VHDL coding) (RU 2008 back) Q3. A coin operated vending machine dispenses candy under the following conditions: -- It accepts nickels (= 5 cents) and dimes (= 10 cents). -- It takes 15 cents to release a candy. -- if 20 cents is deposited, the machine will credit 5 cents and wait for a second purchase. Draw the state diagram for above FSM and minimize it using partitioning procedure. (RU 2008) Q4. Draw the state diagram for an FSM with input x and o/p y such that y is high if previous four values are 1001 or 1111, let i/p is X: 0 1 0 1 1 1 1 0 0 1 1 0 0 1 1 1 1 Write its VHDL code. (RU 2006) Q5. Design above machine using J K F/F. Q6. With the help of an example explain state diagram. Q7. Design an state diagram for sequence detector (11010). (RU 2006)

DEPARTMENT OF ELECTRONICS & COMMUNICATION 8EC4.2: VHDL UNIT 5 DIGITAL SYSTEM DESIGN TUTORIAL SHEET NO.: 01(A)

Q1. Explain setup time and hold time.

(RU 2009)

Q2. How does the problem of clock-skew occur in sequential circuits? (RU 2008 back) Q3. What is the utility of clock synchronization? Q4. What do you mean by hazards? Explain briefly. (RU 2008 back)(RTU 2011) (RU 2008 back)

Q5. What is switch debouncing? How does it affect the performance of a circuit? Q6. What are the common errors in VHDL. [RU-2005]

Q7. Differentiate between cache memory and virtual memory.

DEPARTMENT OF ELECTRONICS & COMMUNICATION 8EC4.2: VHDL UNIT 5 DIGITAL SYSTEM DESIGN TUTORIAL SHEET NO.: 02(B)

Q1. Draw the block diagram of memory organization. Also differentiate SRAM and DRAM with their diagrams. (RU 2008 back) (RU 2009) Q2. Explain SRAM. (RU 2009)

Q3. What is memory organization? Give diagram of single SRAM cell and write the code in VHDL. (RU 2007) Q4. Explain in brief the organization of CPU. Q5. Write short note on ALU in VHDL. Q6. Explain the schematic diagram of a 2mxn SRAM block and explain it. Q7. Explain building blocks of shift registers with enable inputs. Q8. Explain ASM chart, data path circuit and control circuit. (RU 2007) (RU 2006) (RTU 2011)

DEPARTMENT OF ELECTRONICS & COMMUNICATION 8EC4.2: VHDL UNIT 5 DIGITAL SYSTEM DESIGN TUTORIAL SHEET NO.: 01(C)

Q1. Design the Mealy type FSM for a serial adder and write its VHDL code. (RTU 2011) Q2. Draw the ASM chart for state diagram of above question. (RU 2008)

Q3. Draw ASM charts for data path and control circuits for the shift-add multiplier and write its VHDL code. (RU 2008) Q4. Write short note on Flip flop timing parameters. Q5. Write short note on sort operation. Q6. Write short note on Parity generator ckt. (RU 2008) (RU 2008) (RU 2006)

Q7. Draw the schematic diagram for data path circuit for the sort operation. (RTU 2011) Q8. Design ASM chart, data path circuit and ASM chart for the control circuit of divider. Also write its VHDL code.