Conclusion: Andrews: In this lab, we created a state diagram that would be implemented on the board as a logic analyzer.

It would detect the sequence 011001 and when BTN0 is pressed, then it would display 011101. This can be real world application because they may be used in traffic light detectors. This also helps us understand chapter 17 and sequence detectors as well, and allowed us more practice with drawing state diagrams.

Questions: Questions: 1) Sequence detectors could be used in finding an error in previous written code for an application or they could be used in traffic light detection. It could also be used in search, where the bits represent characters and you are looking for a particular string. 2) See pictures

Figure 3: Mealy 0

Figure 4: Mealy 1 3) The SEQ_DVR module take an 8-bit vector and splits it up into single bits passed out as time progresses. The switches in this module were used as the input sequence being detected. The LED indicates the bit currently being read into the system. The 7-segment display showed if the sequence was found or not. Code: -- Company: Cal Poly SLO -- Engineer: Kyle Woody and Tim Grijalava and Sal Navarro and Andrew Vu --- Create Date: 12:31:19 11/16/2011

-- Design Name: FSM Sequence Detector -- Module Name: lab21 - Behavioral -- Project Name: lab 21 -- Target Devices: -- Tool versions: -- Description: detects sequences --- Dependencies: --- Revision: -- Revision 0.01 - File Created -- Additional Comments: ---------------------------------------------------------------------------------library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity lab21 is Port ( CLK : in STD_LOGIC; switches : in STD_LOGIC_VECTOR (7 downto 0); btn : in STD_LOGIC; sseg : out STD_LOGIC_VECTOR (7 downto 0); seg_enable : out STD_LOGIC_VECTOR (3 downto 0); lights : out STD_LOGIC_VECTOR (7 downto 0)); end lab21; architecture Behavioral of lab21 is --Declare Components component clk_div_fs is Port ( CLK : in STD_LOGIC; FCLK, SCLK : out STD_LOGIC); end component; component SEQ_DVR is Port ( SWITCHES : in STD_LOGIC_VECTOR; CLK : in STD_LOGIC;

X : out STD_LOGIC; LEDS : out STD_LOGIC_VECTOR); end component; component FSM is Port ( CLK, btn : in STD_LOGIC; X : in STD_LOGIC; Z : out STD_LOGIC); end component; component BC_DEC is Port ( CLK, Z : STD_LOGIC; SEGMENTS : out STD_LOGIC_VECTOR; DISP_EN : out STD_LOGIC_VECTOR); end component; --intermediate signals signal t1: STD_LOGIC; signal t2: STD_LOGIC; signal t3: STD_LOGIC; begin cdfs: clk_div_fs port map (CLK => CLK, SCLK => t1); seq: SEQ_DVR port map ( SWITCHES => switches, CLK => t1, LEDS => lights, X => t2); CLK => t1, X => t2, btn => btn, Z => t3); bcd: bc_dec port map ( CLK => CLK, Z => t3, SEGMENTS => sseg, DISP_EN => seg_enable); end Behavioral; ---------------------------------------------------------------------------------- Company: Cal Poly SLO -- Engineer: Kyle Woody and Tim Grijalava and Sal Navarro and

fsm1: fsm port map (

Andrew Vu --- Create Date: 13:20:49 11/16/2011 -- Design Name: FSM sequence Detector -- Module Name: fsm - Behavioral -- Project Name: lab 21 -- Target Devices: -- Tool versions: -- Description: Present state to next state --- Dependencies: --- Revision: -- Revision 0.01 - File Created -- Additional Comments: ---------------------------------------------------------------------------------library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity fsm is Port ( CLK X : btn Z : end fsm; : in STD_LOGIC; in STD_LOGIC; : in STD_LOGIC; out STD_LOGIC);

architecture Behavioral of fsm is type state_type is (ST0,ST1,ST2,ST3,ST4,ST5,ST6); signal PS,NS : state_type; begin sync_proc: process(CLK,NS) begin if (rising_edge(CLK)) then

PS <= NS; end if; end process sync_proc; comb_proc: process(PS,X) begin if (btn = '1') then case PS is when ST0 => if X = '0' NS <= else NS <= end if; when ST1 => if X = '0' NS <= else NS <= end if; when ST2 => if X = '0' NS <= else NS <= end if; when ST3 => if X = '0' NS <= else NS <= end if; when ST4 => if X = '0' NS <= else NS <= end if; when ST5 => if X = '0' NS <= else NS <= end if; when ST6 => if X = '0'

then ST1; ST0; then ST1; ST2; then ST1; ST3; then ST1; ST4; then ST5; ST0; then ST1; ST6; then

NS <= ST1; else NS <= ST0; end if; when others => -- the catch all condition NS <= ST0; end case; else case PS is when ST0 => if X = '0' NS <= else NS <= end if; when ST1 => if X = '0' NS <= else NS <= end if; when ST2 => if X = '0' NS <= else NS <= end if; when ST3 => if X = '0' NS <= else NS <= end if; when ST4 => if X = '0' NS <= else NS <= end if; when ST5 => if X = '0' NS <= else NS <= end if;

then ST1; ST0; then ST1; ST2; then ST1; ST3; then ST4; ST0; then ST5; ST2; then ST1; ST6;

when ST6 => if X = '0' then NS <= ST1; else NS <= ST0; end if; when others => -- the catch all condition NS <= ST0; end case; end if; end process comb_proc; with PS select Z <= '1' when ST6, '0' when others; end Behavioral;