Digital Integrated Circuits

A Design Perspective

Designing Sequential Logic Circuits

Bassam Jamil & Saed Abed
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Sequential Logic
Inputs COMBINATIONAL LOGIC Current State Registers
Q D

Outputs

Next state

CLK

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Naming Conventions
In

our text:

a latch is level sensitive a register is edge-triggered For instance, many books call edgetriggered elements flip-flops

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Static vs Dynamic Storage

Static storage
preserve state as long as the power is on have positive feedback (regeneration) with an internal connection between the output and the input useful when updates are infrequent (clock gating)

Dynamic storage
store state on parasitic capacitors only hold state for short periods of time (milliseconds) require periodic refresh usually simpler, so higher speed and lower power
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Latches vs Flipflops

Latches
level sensitive circuit that passes inputs to Q when the clock is high (or low) - transparent mode input sampled on the falling edge of the clock is held stable when clock is low (or high) - hold mode

Flipflops (edge-triggered)
edge sensitive circuits that sample the inputs on a clock transition
positive edge-triggered: 0 1 negative edge-triggered: 1 0

built using latches (e.g., master-slave flipflops)

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Latch versus Register

Latch stores data when clock is low

D Q Clk
Clk D Q

Register stores data when clock rises

D Q Clk

Clk D Q
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Latches

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Latch-Based Design
N latch is transparent when f = 0
f

P latch is transparent when f = 1

N Latch

Logic

P Latch

Logic
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Timing Metrics/Definitions

Setup time (tsu) Hold time (thold) Propagation delay (tc-q) T tsetup + tclk-Q + tp_logic

Also: tcdreg + tcdlogic > thold tcd: contamination delay = minimum delay

CLK t
Register

tsu
D

thold

Q
CLK

DATA STABLE

t
q

tc 2 Q

DATA STABLE

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Review: The Regenerative Property

Vi1 Vo1 Vi2 Vo2

cascaded inverters
A

C
B

If the gain in the transient region is larger than 1, only A and B are stable operation points. C is a metastable operation point.

Vi1 = Vo2
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Bistable Circuits
Vi1 The cross-coupling of two inverters results in a Vi2 bistable circuit (a circuit with two stable states) Have to be able to change the stored value by making A (or B) temporarily unstable by increasing the loop gain to a value larger than 1

done by applying a trigger pulse at Vi1 or Vi2 the width of the trigger pulse need be only a little larger than the total propagation delay around the loop circuit (twice the delay of an inverter)

Two approaches used

cutting the feedback loop (mux based latch) overpowering the feedback loop (as used in SRAMs)
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Writing into a Static Latch

Use the clock as a decoupling signal, that distinguishes between the transparent and opaque states
CLK

CLK
Q CLK

D CLK

CLK

Converting into a MUX

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Forcing the state (can implement as NMOS-only)

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MUX Based Latches

Change the stored value by cutting the feedback loop

feedback feedback

1 Q

0 Q

0
clk Negative Latch

1
clk Positive Latch

Q = clk & Q | !clk & D transparent when the clock is low

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Q = !clk & Q | clk & D transparent when the clock is high

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TG MUX Based Latch Implementation

clk Q !clk D clk clk D Q !clk input sampled (transparent mode)

clk
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feedback (hold mode)

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PT MUX Based Latch Implementation

clk D !Q Q

input sampled (transparent mode) !clk

Reduced clock load, but threshold drop at output of pass transistors so reduced noise margins and performance
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clk !clk

feedback (hold mode)

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Master Slave Based ET Flipflop

D 0 1 D 0 clk Master clk = 0 transparent clk = 01 hold Q clock 1 clk Slave clk D QM Q
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QM

hold
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transparent

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MS ET Implementation
Master Slave I2 T2 I3 QM D clk master transparent slave hold clk !clk
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I5

T4

I6

I1

T1

I4

T3

master hold slave transparent

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MS ET Timing Properties

Assume propagation delays are tpd_inv and tpd_tx, that the contamination delay is 0, and that the inverter delay to derive !clk is 0 Set-up time - time before rising edge of clk that D must be valid
3 * tpd_inv + tpd_tx

Propagation delay - time for QM to reach Q

Hold time - time D must be stable after rising edge of clk

zero
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tpd_inv + tpd_tx

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Set-up Time Simulation

3 2.5 2

3 2.5

QM D clk I2 out
0 0.2 0.4 0.6 0.8 1

2 1.5 1 0.5 0 -0.5 0 0.2 0.4 0.6 0.8 1

1.5
1 0.5

0
-0.5

tsetup = 0.21 ns

tsetup = 0.20 ns
Fails

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Propagation Delay Simulation

3 2.5 2 1.5

tc-q(LH) = 160 psec

Volts

1 0.5 0 -0.5 0

tc-q(LH)

tc-q(HL)

tc-q(HL) = 180 psec

0.5

1.5

2.5
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Time (ns)
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Reduced Load MS ET FF

Clock load per register is important since it directly impacts the power dissipation of the clock network. Can reduce the clock load (at the cost of robustness) by making the circuit ratioed
clk
I1 D T
1

!clk
I3 QM T
2

I2
!clk clk

I4
reverse conduction

to switch the state of the master, T1 must be sized to overpower I2 to avoid reverse conduction, I4 must be weaker than I1
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Non-Ideal Clocks
clk !clk clk !clk

Ideal clocks

Non-ideal clocks clock skew 1-1 overlap

0-0 overlap
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Example of Clock Skew Problems

clk X !clk Q

P1

I1
P2 !clk

I2
B

P3

I3
P4 clk

I4

!Q

Race condition direct path from D to Q during the short time when both clk and !clk are high (1-1 overlap) Undefined state both B and D are driving A when clk and !clk are both high Dynamic storage when clk and !clk are both low (0-0 24 overlap) 2nd

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Pseudostatic Two-Phase ET FF
clk1 D P1 X clk2 P3 B I3 P4 clk1 dynamic storage I4 Q

I1

I2

!Q

P2
clk2

master transparent slave hold

clk1

tnon_overlap
clk2
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master hold slave transparent

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Non-Ideal Clocks
clk !clk clk !clk

Ideal clocks

Non-ideal clocks clock skew 1-1 overlap

0-0 overlap
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Example of Clock Skew Problems

clk X !clk Q

P1

I1
P2 !clk

I2
B

P3

I3
P4 clk

I4

!Q

Race condition direct path from D to Q during the short time when both clk and !clk are high (1-1 overlap) Undefined state both B and D are driving A when clk and !clk are both high Dynamic storage when clk and !clk are both low (0-0 27 overlap) 2nd

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Pseudostatic Two-Phase ET FF
clk1 D P1 X clk2 P3 B I3 P4 clk1 dynamic storage I4 Q

I1

I2

!Q

P2
clk2

master transparent slave hold

clk1

tnon_overlap
clk2
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master hold slave transparent

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Dynamic ET Flipflop
master !clk T
1

slave clk

I1 C

QM

T
2

I2 C

clk

!clk

master transparent slave hold

tsu = tpd_tx thold = zero tc-q = 2 tpd_inv + tpd_tx

clk

!clk

master hold slave transparent

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Dynamic ET FF Race Conditions

!clk T
1

clk I1 C

QM

T
2

I2 C

clk

!clk

clk !clk

0-0 overlap race condition toverlap0-0 < tT1 +tI1 + tT2

1-1 overlap race condition toverlap1-1 < thold

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Dynamic Two-Phase ET FF
clk1 T
1

clk2 I1 C QM T
2

I2 C

!clk1
master transparent slave hold

!clk2

clk1 tnon_overlap clk2

master hold slave transparent

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Pseudostatic Dynamic Latch

Robustness considerations limit the use of dynamic FFs

coupling between signal nets and internal storage nodes can inject significant noise and destroy the FF state leakage currents cause state to leak away with time internal dynamic nodes dont track fluctuations in VDD that reduces noise margins

A simple fix is to make the circuit pseudostatic

!clk

clk

Add above logic added to all dynamic latches

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