VALPARAISO UNIVERSITY ELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT ECE 222 Design Project #3 - 4-Bit Adder/Subtractor Spring 2001

Objective: The objective of this project is to introduce you to the VHDL environment in the Mentor Graphics software. In this project you will create a 1-bit full adder using dataflow VHDL and then create a 2s complement 4-bit adder/subtractor using a structural VHDL model. SECTION I. VHDL IMPLEMENTATION IN MENTOR GRAPHICS

ModelSim is the software tool in the Mentor Graphics tool suite that works with VHDL. To minimize problems, you should create a separate directory for the VHDL source code and you should be logged into that directory while you perform the project. For the remaining portion of the project we will call this directory myVHDL. 1. ModelSim requires that there be a specially initialized directory called work just below the directory with the source files. Perform the command

vlib work
in myVHDL. ModelSim builds the directory work and initializes its contents properly (do not just use mkdir to create this directory!). 2. Copy the template.vhd file from the directory /home/ejohnson/Public/ece222/VHDL into myVHDL. This template contains the interface and architecture structure that you can use when creating your VHDL code. SECTION II. DATAFLOW VHDL

1. Using a text editor develop a dataflow representation (concurrent statements) of the full adder (call it fulladd.vhd). Use the full adder schematic implementation shown on page 151 of Dewey as a guide. 2. To compile the adder, from the directory myVHDL, execute the command

vcom fulladd.vhd
in a command window. The source files must be in the current directory, and the results are placed in the directory work. If you encounter any errors, check your VHDL file, fix the errors and re-compile. 3. You are now ready to verify the full adder design using simulation. Use the command

vsim &
to start ModelSims simulator. Two windows will appear, the Main window and a Load window. (The first time you start up ModelSim you will have another window appear. You can simply close that window). The Main window is shown below. All commands and other windows are opened from this window.

The Load window is shown below. In the Load window you can select which model you want to verify. Click on the model name (full_adder or something similar) and then hit the Load button.

4. Under the View menu select Signals. A new window which shows all of the signals in your design appears. In the Signals window, select View->Wave->Signals in region. You should now see a window in which waveforms can be displayed. 5. Now we need to apply stimulus to the inputs. There are different ways to do this in ModelSim. You can enter the forces from the Force option under the Edit menu in the Signals window, you can type in the forces in the main window or you can create a force file (like with QuickSimII). For this experiment, we will use the third option. Place the following commands in a file (call it fulladd.do). force force force force force force -freeze -freeze -freeze -freeze -freeze -freeze /a 0 /a 1 /b 0 /b 1 /cin /cin -repeat 200 100 -repeat 200 -repeat 100 50 -repeat 100 0 -repeat 50 1 25 -repeat 50

This creates three clock-like waveforms for the three input signals, a, b, and cin. 6. In the Waveform window then select the Load Wave Format button (some of the buttons and their function are shown below. When the file browser pops up, select the fulladd.do file and hit Execute. This will load your input forces.

Print Load Wave Format 2

Zoom Full Restart

Run

7. Run the simulation for 200 ns by clicking on the Run button in the Waveform window. Each click of the button will advance your simulation 100 ns. In the Waveform window, check to make sure your full adder is working properly (use the Zoom Full command if necessary). If you find any errors you will need to fix them, re-compile the code and then reload the design using the Load New Design under the Design menu. If you want to restart the simulation, you can simply click on the Restart button in the waveform window. This resets your simulation time back to 0 ns. In both cases you will need re-execute the macro file again to add the proper forces to your inputs. 8. To print out the waveforms, click on the Print button. When the Print window appears, change the print command to just lp and then hit OK. 9. You can exit out of the simulator by selecting Quit under the File menu in the Main window. SECTION III. ADDER/SUBTRACTOR STRUCTURAL REPRESENTATION

In this section, you will create and verify a structural representation of a 2s complement 4-bit adder/ subtractor using your full adder model you designed in the previous section. You will be given additional information as needed to complete the representation. 1. Before you create the model, sketch your design out on paper. This will help you visualize what the design looks like and will help you see the internal signals you will need to define. 2. Two of the components you will need have already been created for you, a 4-bit 2:1 multiplexer and a 4-bit inverter. You can copy those models along with a package containing those two components from the following directory: ~ejohnson/Public/ece222/VHDL/dp3 You will want to compile each of these files into your work library before you use the models in your adder/subtractor. You will also want to look at the ordering of the PORTS in the inverter and multiplier entities in these files since you will be using them in your structural design. 3. Create a structural representation of a 4-bit adder/subtractor using your 1-bit full adder dataflow representation and the two given components. 3a. Create the interface for your adder. For the two data inputs and sum output use the BIT_VECTOR type instead of BIT. The BIT_VECTOR format can be found on page 403 in Dewey. You will also need a MODE input that will determine if you perform an add or subtract. 3b. Create the structural description of the adder/subtractor. At the beginning of your architecture you need to declare and bind the components that you will be using. Since a package has already been compiled for two of the three components, make sure you include the USE command to utilize the package. Create the model using the in-class project (4-bit ripple adder) as a guide. 4. Compile your structural model. If you find any mistakes, fix them and recompile. 5. Simulate the model to verify it is working correctly. When the Load window appears make sure you select your four-bit design. 5a. Use the Simulation option under the Options menu in the Main window to set the Default Radix to Hexadecimal instead of Binary. 5b. Instead of a force file, create the forces using the pull down menus in the Signals window. Select the signal you want to apply the force to (one of your two inputs) and then select the Force command under the Edit menu. Change the value to another hex number and hit OK. Do the same to your other input and then run the simulation to make sure it is working correctly. Run at least three different 3

additions and subtractions to ensure the design is working correctly. Also make sure you show both overflow and underflow conditions. 5c. Once you have the design working correctly print out your waveforms. Above each test case write the equivalent decimal addition or subtraction. SECTION IV. WHAT TO TURN IN?

1. A hard copy of your dataflow representation of the full adder along with a copy of the waveforms. 2. A hard copy of your structural representation of the 2s complement 4-bit ripple adder/subtractor and a copy of the waveform output.

ECE 222 Advanced Logic Design Design Project #3: 4-Bit Adder/Subtractor
February 19, 2001
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