Introduction To CMOS Design: Dr. Paul D. Franzon

ECE 520 Class Notes
Introduction to CMOS Design

Dr. Paul D. Franzon
Outline 1. CMOS Transistors 2. CMOS cell design 3. Transistor Sizing 4. Low Power Design References l Smith and Franzon, Chapter 11 l Weste and Eshraghian, Principles of CMOS VLSI Design, A Systems Perspective
2000, Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html 1
ECE 520 Class Notes
CMOS Transistors
1. nMOS Transistor
Drain Source n p substrate Gate L Gate n W Gate Polysilicon Conductor Silicon Oxide Gate
Drain substrate
Source
Drain
Source
2000, Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html
ECE 520 Class Notes
Transistors
2. pMOS transistor: Drain Source p n substrate Gate L Gate p W Gate Silicon Oxide Gate
Drain substrate
Source
Drain
Source
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MOS Transistor Theory

Transistor States: 1. Cutoff Region Ids = 0 when Vgs < Vt Vt = Threshold Voltage (typically 1 V for nMOS, - 1V for pMOS) 2. Linear Region Ids = ((Vgs - Vt)Vds - Vds2/2) when 0 < Vds < Vgs - Vt =(/tox)(W/L) W = channel width L = channel length = electron (n) / hole (p) mobility = permittivity of gate insulator tox = gate insulator (oxide) thickness
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... nMOS Transistor Theory

.... Transistor States 3. Saturatation Region Ids = (Vgs - Vt)2 when 0 < Vgs - Vt < Vds Q: Draw a large signal equivalent model for transistor in Linear and Saturation States:
Transistor Characteristics:
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Transistor Characteristics
V-I Characteristics: |Ids| |Vgs|
|Vds|
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CMOS Inverter
Static CMOS Inverter: Vin 5V Vout 0V What are the transistor states when: Vin = 0 V Vin = 2 V Vin = 3 V Vin = 5 V given |Vt| = 1 V
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Transistor Speed is determined by SIZE

CMOS circuit speeds can be modeled to a first approximation as RC delays: 1. What does the input of a CMOS gate `look like? C in = 2. What does the òutput of a CMOS gate `look like during switching? Rn = Rp = 3. Usually hole mobility is half of electron mobility. So what must you do to make the pull up and pull down delays about the same? 4. If a gate is heavilly loaded what must you do to speed up the delay?
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Other Gate Designs

Refer to data sheets in CMOSX library: l NAND gate l NOR gate l D Flip Flop Analyse the circuits to determine `how these gates work. Exercise in transistor sizing:
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Power Consumption
Why is power consumption important? l Battery powered devices
l Minimize cost of wall-powered systems
l Maximize battery life
l Plastic packaging is 10x cheaper than ceramic packaging but can only dissipate 1 - 2
W u What happens if the chip gets too hot?
l `Green systems
l Need a fan to cool somewhere above 10 W l Difficult to air cool at all somewhere above 50 W l Cost of power supply l Minimize pollution by reducing demand from power stations
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Power Consumption in Digital Electronics

Bipolar Circuits:
l Always draw DC current l Average current per gate high l Gate layout area larger than CMOS
CMOS Circuits:
l Static CMOS draws current only when it changes state

When input = Vcc, nMOS transistor off When input = GND, pMOS transistor off Gate load = capacitor, no current load Reverse current through backbiased pn junction to substrate is small unless Vcc is very small u `through current small during switching Derive power consumption for CMOS:
u u u u
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Minimizing Power Consumption

Power consumption in a CMOS module: Power = Nswitch f Vcc2 Cload
l l l l
Sum over all nodes in circuit f = clock frequency Nswitch = average % of clock periods in which node switches Cload = capacitance of node
Approaches to minimizing power consumption
l Reduce Supply Voltage l Reduce clock frequency

u Only useful when performance can be satisfied with slower clock u Can induce `sleep mode by turning off clock, or ìdle mode by slowing clock down a lot l Reduce Nswitch through clever design
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Reducing Power Consumption

Reduce the power consumption in this circuit: Specification lCalculates memory address by adding busA and busB lOnly 15% of bus transactions contain memory address always@(posedge clock) address <= busA + busB; Calculate Power Consumption if address bus load = 100 inverters and adder equivalent to 30 inverters switching Solution1: Use a Mux
Solution 2: Use an Enable
Solution 3: Gate the clock
Disadvantages of gating clock:
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ECE 520 Class Notes
Summary Complementary MOS transistors gives dense circuits and lower power than other circuit families l Standard Cell designs use Static CMOS l Transistor speed approximated using òn resistance l Ron proportional to electron/hole mobility and W/L
u Hole mobility = half electron mobility Inverter Wp = 2 Wn to make trise = tfall u To drive larger loads, increase transistor width proportionally
Power consumption important in many designs Power = Nswitch f Vcc2 Cload l Lower ing voltage by one-half, quarters the power but halves the speed l Turn clock frequency down when performance not needed l Reduce Nswitch through good design (enable circuits)
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ECE 520 Class Notes