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Ivan Grech
Design of various digital signal processing and communication blocks which form an integral part of a typical L1-band C/A-code GPS receiver
Using synthesisable VHDL code
Design of a GPS satellite signal modulation model Noise performance analysis of the designed baseband processor
GPS uses spread-spectrum communication (CDMA) for communication between space and user segments Satellites transmit on the same frequency
two separate RF carriers are used (L1 and L2)
Each satellites navigation message is modulated by the satellites PRN code and the resulting digital signal BPSK modulates the carrier wave
The baseband processor is responsible for demodulation of navigation data coming from different satellites
Demodulation involves acquisition and tracking
Acquisition:
Generate local replica of incoming signal:
carrier replica + C/A-code replica
Down convert the incoming signal to baseband and cross-correlate the result with the local C/A-codes
Baseband Processing
8
Assumptions:
Perfect carrier phase recovery GPS signals are not affected by Doppler Effect
The baseband processor hardware modules are designed using synthesisable VHDL code
The GPS satellite signal modulation model is designed using MATLAB Simulink
System Design
9
Carrier Generator:
Front-end chip used is the GP2015 which down converts the L1 frequency to 4.309 MHz IF IF bandwidth = 2.046 MHz; fS = 5.102 MHz Aliasing occurs and the IF frequency is further down converted to 793 kHz Local carrier = 2.4 sin (2(793k)t)
Carrier Quantisation
10
Carrier Samples:
11
Baseband Mixer:
Mixes incoming 2-bit digitised IF signal with local carrier Each baseband sample requires 3-bit to be represented
C/A-Code Generator:
Generates the C/A-codes of all 24 satellites in parallel at a rate of 1.023 MHz
13
Baseband Signal
S0
S1
S2
S3
S1022
14
Comparator:
Selects four satellites for data demodulation and determines their correct code phase delays Controls which four satellites are processed simultaneously by the correlator Accumulation interval = 2 ms
15
16
The correct functionality of each module was verified through various simulations
VHDL modules were tested using ModelSim Satellite signal modulation model was tested using MATLAB Simulink Simulation tool
Evaluation setup:
Bottom-up approach Tests for one satellite transmission Tests for multiple satellite transmissions Analyse noise performance of baseband processor
17
18
4000
3000
Correlation Value
2000
1000
0 38 75
-1000
1000
630
112
149
186
223
260
297
334
371
408
445
482
519
556
593
667
704
741
778
815
852
889
926
963
19
Correlation
Value
325
649
109
145
181
217
253
289
361
397
433
469
505
541
577
613
685
721
757
793
829
865
901
937
973
20
21
Noise Performance:
22
Noise Performance:
23
X3S500E
24
Minimum SNR value that processor can tolerate is -10 dB when gain control is adopted The front-end AGC is crucial in the performance of the baseband processor
If no gain control is adopted, minimum SNR that the receiver can tolerate is greater than -10 dB
25
Carrier Synchronisation
27