7b.

Passtransistor and Transmission Gate Logic

Institute of Microelectronic Systems

Passtransistor Logic: Basic Principle

Idea:
control

0=open 1=closed

Vin

Vout

Vin 1 1 0

control 0 1 0 1

Vout x 1 x 0

Implementation:

Vin

Vout

control

7b: Transmission Gate Logic

Institute of Microelectronic Systems

Passtransistor Logic: NEXOR Realisation

B
A
OUT

B 0 1 0 1

OUT 1 0 0 1

0 0 1 1

A B

7b: Transmission Gate Logic

Institute of Microelectronic Systems

Passtransistor: Charging Characteristics

NMOS
Vctrl (t )
Vctrl (t < 0) = 0 Vctrl (t >= 0) = VDD

VGS

Vin = VDD
Cout

Vout ( t )
Vout ( t = 0) = 0

Transistor is in Saturation during Charging Process

Vout (t )
VDD VT ( VSB )

t
Institute of Microelectronic Systems

7b: Transmission Gate Logic

Passtransistor Cascades
VDD VDD VDD VDD

Vin = VDD
Vmax Vmax Vmax

Vmax = VDD VT ( Vmax )

Cout
Vmax

VDD

Vin = VDD
Vmax,1

Vmax,1 = VDD VT ( Vmax,1 )

Vin = VDD
Cout

Vmax, 2 = Vmax,1 VT ( Vmax, 2 )

Vmax, 2

VDD 2VT

7b: Transmission Gate Logic

Institute of Microelectronic Systems

Passtransistor: Discharging Characteristics

NMOS
VGS Vctrl (t )
Vctrl (t < 0) = 0 Vctrl (t >= 0) = VDD

Vin = 0

Vout ( t )

Transistor is always in Nonsaturation during Discharging Process

Cout Vout (t = 0) = VDD VT ( VSB )

Vout (t )
VDD VT ( VSB )

t
Institute of Microelectronic Systems

NMOS Passtransistor: Discharging faster than Charging, since Device Impedance is lower in NSat than in Sat
6

7b: Transmission Gate Logic

Passtransistor: Charging Characteristics

PMOS Charging Process:
Vctrl (t )
Vctrl (t < 0) = VDD Vctrl (t >= 0) = 0

VGS

Vin = VDD
VDD

Vout ( t )
Cout
Vout ( t = 0) = 0

The output is charged to VDD (Transistor is initially saturated and goes in nonsaturated mode)

PMOS Discharging Process:

Vctrl (t ) VGS
Vctrl (t < 0) = VDD Vctrl (t >= 0) = 0

Vin = 0
VDD

Vout ( t )
Cout
Vout ( t = 0) = VDD

The output is discharged to VT (Transistor is saturated and finally goes in cut-off mode)

7b: Transmission Gate Logic

Institute of Microelectronic Systems

From Passtransistors to Transmission Gates

Logic Level Logic 0 Logic 1
VDD

NMOS 0
VDD VTN

PMOS
VTP

CMOS 0
VDD

Vctrl

VDD

Vin

Vout
Cout

Vctrl

Vin
Vctrl
CMOS Transmission Gate

Vout
Vctrl

I DN + I DP

dV = Cout * out dt

Symbol: CMOS Transmission Gate

Bidirectional resistive connection between the input and output terminals Useful in both analog (e.g. for relay contacts) and in digital design (e.g. for multiplexers)
Institute of Microelectronic Systems

7b: Transmission Gate Logic

Transmission Gate: Operation States

Operation states of the Transistors which are passed over during charging the output from 0 to VDD:
Mn cut-off

Final Voltage : VDD

VTP
Initial Voltage : 0

Mn saturated

7b: Transmission Gate Logic

Institute of Microelectronic Systems

Mp sat.

Mp nonsaturated

VDD VTN

CMOS Transmission Gate: On-Resistance

R EQ =

R onP R onN R onP + R onN

On-resistance of a transmission gate, including body effect

VTON = 0.75V , VTOP = 0.75V

= 0.5V 0.5 , 2 F = 0.6V ,

K p = 20 A / V 2 , K n = 50 A / V 2

7b: Transmission Gate Logic

Institute of Microelectronic Systems

10

CMOS Transmission Gate (III)

Charge sharing problem

VF =

C BIGVBIG + C SMALLVSMALL C BIG + C SMALL

Example: CSMALL = 0.02 pF, VSMALL = 5 V, VBIG = 0 V CBIG = 0.2 pF (about 10 standard loads in a 0.5 CMOS process)
VF = 0.45 V The big capacitor has forced node A to a voltage close to a 0

Node A has to be insulated from node Z by including a buffer (e.g. Inverter) between the 2 nodes, if node A is not strong enough to overcome the big capacitor
7b: Transmission Gate Logic Institute of Microelectronic Systems 11

Transmission Gate Logic

Multiplexer: Equivalence (NEXOR):

F = AS + BS
S B

F = AB + A B = AB

Alternate equivalence logic circuit:

A
S

A
S

B
B

7b: Transmission Gate Logic

Institute of Microelectronic Systems

12

Function Implementation with Passtransistor Logic

F = bd + abd + abd + bcd
Karnaugh Map of F:

F
1 0 b 1 a 1 c 0 1 d
Institute of Microelectronic Systems

0 0

0 1 1 1

1 0 1 1

Step 1:

find minimum decomposition in such a way, that each selected field is depending on one variable or constant 0 or constant 1 only (in our case: decompose with combinations of the literals b and d

7b: Transmission Gate Logic

13

Function Implementation with Passtransistor Logic

Step 2: Step 3: Attach decomposition variables to selection lines Determine the line input signals (implement inverted function to compensate output inverter

VDD
Sustainer transistor

a
F

b
7b: Transmission Gate Logic

d
Institute of Microelectronic Systems 14