SCMITT TRIGGER BY USING IC-741

EXP NO :
DATE :
AIM : To Study the operation of Schmitt trigger using op-amp using IC-741.
APPARATUS REQUIRED :

SNO APPARATUS RANGE QTY
1 IC - 741 - 1
2 Dual power supply + 15V 1
3 Resistor 10KO, 4.7 KO, Each 1
4 CRO 20Mhz 1
5 Function Generator - 1
6 Bread Board & connecting wires - As required*
THEORY:
.
A Schmitt Trigger is also known as a regenerator comparator. Input signal is
given to the inverting terminal and the positive feedback is applied. The input voltage
triggers the output voltage every time it exceeds certain voltage level. These voltage
levels are called Upper threshold voltage. Suppose the output voltage equals +Vsat then
the voltage at the positive terminals will be +VUT = Vref +(R2 /(R1 +R2) (Vsat Vref).
Similarly VLT = Vref -(R2 /(R1 +R2)
(Vsat +Vref). This occurs when output voltage shifts to Vsat.
VM = VUT - VLT = 2R2 Vsat /(R1 +R2)
PROCEDURE: -
1. The Connections are given as per the circuit diagram.
2. The Dual power supply is switched ON.
3. The function generator is switched ON and set to sine wave
generation Mode.
4. The Wave forms (output & input) are noted with the help of CRO.
5. The values are noted and graphs are plotted.
APPLICATIONS:-
1. Schmitt trigger is mostly used to convert a very slowly varying input
to square wave output.
RESULT:-
Thus a Schmitt trigger were constructed using IC741 op-amp and their
operation was verified.


OBSERVATION :-

Slno Schmitt Trigger
1

Input Output

Time period = Time period =

Amplitude = Amplitude =

Schmitt Trigger
Input Voltage =
Output Voltage =
UTP & LTP =

SCHMITT TRIGGER





~
+15V
2 7
-
IC 741 Vo
3 6
+
4
-15V
R1 = 10KO






R2 = 4.2KO


Vi
FG
MODEL GRAPH: -


VUT
| Vin
t
VLT

+VSAT


Vout |
t

- VSAT

























ASTABLE MULTIVIBRATOR USING OP-AMP IC - 741
EXP NO : 7
DATE :

AIM : To design an Astable Multivibrator using IC 741 for the frequency of 2 khz.

APPARATUS REQUIRED :


THEORY :
It is also known as free running oscillator. The principle of generation of
square wave
is to force an op-amp and to operate in two sdaturation region | =R2/R1+R2.
Thus the Vref is |Vo and may take the values as +ve |Vsat and Ve
|Vsat.The output
is also fed to inverting input & op-amp after integrating by means of a low pass
RC
combination.
FORMULA :-
1) T1 = RC Log e 1 + 2R2
R1
2> FO = 1
2 T1
3> VUT = Vsat R2
R1 +R2
SNO APPARATUS TYPE RANGE QTY
1 Op-amp IC-741 - 1
2 Dual Power Supply DC + 15V 1
3 Resistor -
3.6kO,
15kO, 10kO
Each 1
4 C.R.O - 20 MHZ 1
5 Capacitor - 0.1f 1
6 Function generator - 0-20 MHZ 1
7
Bread Board & connecting
wires
- -
As
required*




PROCEDURE: -
1. The Connections are given as per the circuit diagram.
2. The DPS is switched ON is Set to 15V.
3. The output waveform is noted from the CRO and the time period of
the signal is taken down.
4. The theoretical and practical values of frequency are checked and
verified to be matching.
















RESULT :-
Hence Astable multivibrator using IC 742 for frequency of 2 khz has designed
where
charging time = _____ ms.
Theoritical frequency = _________.
Practical frequency = __________.
















































IC
741



15V
+ VCC
15V
- VCC






VO



10KO




5K O

2 7
-
6
3 4
+

OFFSET1 8 NC
NULL IC 741

INV 2 - 7 +VCC

NIV 3 + 6 O/P
3.6 KO
- VCC 4 5 OFFSET
SUPPLY NULL

PIN DIAGRAM

CIRCUIT DIAGRAM

ASTABLE MULTIVIBRATOR USING OP-AMP
+ V
SAT

+ | V
SAT





-| V
SAT

- V
SAT










MODEL GRAPH

MEASUREMENT OF OP-AMP CHARECTERISTICS
EXP NO :
DATE :

AIM : To measure the input offset voltage input bias current, input offset current and
slew rate of
the given IC-741 op-amp.
APPARATUS REQUIRED :

THEORY :

1) The characteristics of ideal op-amp are given below.
a> input impedence is infinite.
b> Output impedence is zero.
c> Open loop gain (AOL) is infinite.
d> Zero offset voltage i.e VO = 0. when Vi = V2 = 0
e> Bandwidth is infinite.
f> Slew rate is infinite.
g> Common mode rejection ratio is infinite.

2) The characteristics of practical op-amp are given below.
a> DC Charecteristics:-
1) Input offset voltage Vio.
2) Input Offset current Iio.
3) Input bias current, IB.
4) Thermal drift.
b> AC Charecteristics:-
1) Bandwidth.
2) Slew rate.
3) Noise.
4) Frequency compensation.
SNO APPARATUS TYPE RANGE QTY
1 Op-amp IC-741 - 1
2 Dual Power Supply DC + 15V 1
3 Resistor -
50O, 5kO,
10kO,1mO
Each 1
4 C.R.O 20 MHZ 1
5
Bread Board & connecting
wires
-
As
required*




CIRCUIT DIAGRAM :- Rf = 5kO

INPUT OFFSET VOLTAGE :-







R1=50O +15V
2 7
-
IC741 6 Vo

3 +
R1=50O 4
-15V


OFFSET1 8 NC
NULL IC 741

INV 2 - 7 +VCC

NIV 3 + 6 O/P

-VCC 4 5 OFFSET
SUPPLY NULL

PIN DIAGRAM






CIRCUIT DIAGRAM :-
BIAS CURRENT IB
+
:-






+15V

2 7
- 6
Rf = 1mO IC741 Vo
+
3 4
-15V

BIAS CURRENT IB
-
:-



SLEW RATE :-






Rf = 10KO


+15V

R
1
= 10KO 2 7
-
6
I C741 Vo
3 +
3 4

-15V

~
Rf = 1mO


+15V

2 7
-
6
IC741 Vo
+
3 4
-15V


MODEL GRAPH:-


|Vin


Time




dt

dvo


|Vin Time








PROCEDURE :-

1) TO FIND INPUT OFFSET VOLTAGE :-

a> The given circuit is connected as per the given circuit diagram.
b> The output voltage is measured using multimeter, which is negative voltage.
c> The value is tabulated & given formula i.e Vio=VoR1 .
R1+ Rf
is used to calculate the input offset voltage.
2) TO FIND INPUT BIAS CURRENT :-
a> The circuit is connected as per the given circuit diagram.
b> IB
+
is measured using output voltage Vo obtained with the help of digtal
multimeter & then evaluate IB
+
using formula.
IB
+
= Vio -Vo
R1
c> Simillarly,determine IB
-
by using the formula, IB
-
= Vo -Vio
Rf
3) TO FIND THE SLEW RATE ( dVo/dt ) :-
a> The circuit is connected as per given circuit diagram.
b> Vin & Vout is measured to connected to channel 1 (x) and channel 2(y) of CRO
respectively.
c> Function generator is added to keep signal at channel 1 at 1 volt peak to peak
(square wave).
d> The frequency of signal generator is varied.
e> The frequency is kept increasing till the rising edge of Vo is observed to incline.
f> The out slew rate is calculated from output wave form at channel 2 & express it
in terms at volts/sec.
FORMULA :-
1) Input offset voltage = Vio = VoR1 mv
R1+ Rf

2> Input Bias current = IB
+
= Vio Vo A.
R1
= IB
-
= Vo Vio A.
Rf
3> Input Offset current :- , IB
+
- IB
-
, A.

4>Average Input Bias current :- IB
+
+ IB
-
A.
2
5> Slew Rate :- dVo v/s
dt















































RESULT:-
Charecteristic of IC-741 op-amp studied and found to be

1> Input offset voltage = _______________.
2> Input bias current IB
+
= _______________.
3> IB
-
= _______________.
4> Input offset current = _______________.
5> Slew rate = _______________.
6> Average Bias current = _______________.


WEIN BRIDGE OSCILLATOR
EXP NO :
DATE :
AIM : To design and test the wein bridge oscillator for the frequency of 1 kHz by using
operational amplifier (IC-741).
APPARATUS REQUIRED:

SNO APPARATUS RANGE QTY
1 IC-741 - 1
2 Dual Power Supply + 15V 1
3 Resistor
1.5KO,
20 kO, 10kO
2
Each 1
4 Capacitor 0.1F 2
5 C.R.O 20 MHZ 1
6 Bread Board & connecting wires - As required*
THEORY:
A wein bridge oscillator is an audio frequency oscillator. It may be noted
that feedback signal in the circuit is connected to positive input signal / terminal end of
the operational Amplifier. It consists of a series combination and also a parallel
combination of R and C in adjoining arms.
According to Barkhausens criteria product of gain and bandwidth equals
to one.And total phase shift in the network is zero. The above condition may be
achieved by balancing the bridge. Now from the feedback network,
R R
VF = (1 + j erc) =
VO (R-jeC) +R (1+ jeRC) (3R +j (e
2
RC -
1) )

eC
A| = 1, so | must be real, e
2
RC = 1 ; e = 1 ; fo = 1
eC RC 2tRC
Here for Oscillations, Rf = 3
Ri








PROCEDURE: -
1. The Connections are given as per the circuit diagram.
2. The DPS is switched ON is Set to 15V.
3. The output waveform is noted from the CRO and the time period of
the signal is taken down.
4. The theoretical and practical values of frequency are checked and
verified to be matching.

DESIGN: -
F0 = 1

2tRC




Rf = 2Ri

OBSERVATION: -
Time Period Output Voltage
Time /div
No. of
divisions
Time Volt/div
No. of
divisions
Voltage





f = 1/T = ______ KHZ.















MODEL GRAPH: -






Amplitude in volts

Time in sec




RESULT:
Thus the oscillator has been designed constructed and tested. The found out
frequency were
Theoretical frequency = ______ kHz.
Practical frequency = _______kHz.



IC
741
10KO


Ri





RF



15V
+ VCC
15V
- VCC


1.6KO






0.1F


C
VO

R



0.1F

2 7

6
3 4


OFFSET1 8 NC
NULL IC 741

INV 2 - 7 +VCC

NIV 3 + 6 O/P

- VCC 4 5 OFFSET
SUPPLY NULL

PIN DIAGRAM



CIRCUIT DIAGRAM
WEIN BRIDGE OSCILLATOR
CIRCUIT DIAGRAM




























MODEL GRAPH:

















Decimal
Number
Binary Code Theoretical
Voltage
Practical
Voltage
Error=
V
TH-
V
PRAc
/V
PRAC
B3 B2 B1 B0
0 0 0 0 0 0
1 0 0 0 1 -0.625
2 0 0 1 0 -1.25
3 0 0 1 1 -1.875
4 0 1 0 0 -2.5
5 0 1 0 1 -3.125
6 0 1 1 0 -3.75
7 0 1 1 1 -4.375
8 1 0 0 0 -5
9 1 0 0 1 -5.625
10 1 0 1 0 -6.25
11 1 0 1 1 -6.875
12 1 1 0 0 -7.5
13 1 1 0 1 -8.125
14 1 1 1 0 -8.75
15 1 1 1 1 -9.374



SHIFT REGISTERS
Exp No : Date :



AIM :

To study the operation and verify the truth table of Shift Register.



APPARATUS REQUIRED :








THEORY :


Shift registers are sequential circuits . As they employ Flip-Flops,
they possess memory. However, memory is not the only requirement . Shift registers are
used to store binary data momentarily until it is utilized .

The various modes of operation of Shift Registers :

1. SERIAL INPUT / SERAL OUTPUT.
2. SERIAL INPUT / PARALLEL OUTPUT.
3. PARALLEL INPUT / SERIAL OUTPUT.
4. PARALLEL INPUT / PARALLEL OUTPUT.



S.No: NAME QUANTITY
1. IC 7474 2
2. Digital trainer kit 1
3. Connecting wires As required






CIRCUIT DIAGRAM :




TABULATION:-

INPUT DATA 1 :__________

Sl.No Clk pulse A B C D









INPUT DATA 2 :__________

Sl.No Clk pulse A B C D









SN7474 SN7474 SN7474 SN7474




PROCEDURE :

SERIAL INPUT / PARALLEL OUTPUT :

After the register is cleared , any 4-bit serial number can be
loaded into the register .

Proceed as follows :

1. Serial input is switched to High .
2. A clock pulse is applied which will shift the serial input 1 into the register :
QA
will be 1.
3. Three more clock pulses are applied.
4. The Register will show an output 1 1 1 1 .

This procedure converts a serial input into a parallel output .
We can load any 4-bit number into the register in this way .

* NOTE : To CLEAR the register, set the serial input to LOW and apply 4 clock
pulses .










RESULT :

The operation of SIPO Shift Register is studied and truth table is verified .



COUNTER

AIM :

To study the operation and verify the truth table of Counter.

APPARATUS REQUIRED :











THEORY :

COUNTERS , like Shift registers , are sequential circuits and as they employ
Flip-Flops, they possess memory.

RING COUNTERS provide a sequence of equally spaced timing pulses and
therefore , they find considerable application in logic circuits ,
which require such pulses for setting in motion a number of operations in a
predetermined sequence and at very precise time intervals .














S.No: NAME QUANTITY
1. IC 7474 2
2. Digital trainer kit 1
3. Connecting wires As required


CIRCUIT DIAGRAM:-
TABULATION:-














PROCEDURE :

1. Serial input is switched to High .

2. A clock pulse is applied which will shift the serial input 1 into the register


3. Seven more clock pulses are applied.

4. The output of the Ring Counter is noted after each clock pulse

5. Thus , the Truth Table is verified .


RESULT :


The operation of Johnson Counter is studied and truth table is verified .
SN7474 SN7474 SN7474 SN7474
Sl.No Clk pulse A B C D












MULTIPLEXER AND DEMULTIPLEXER


AIM :-

To control a circuit and check the truth tables of Multiplexer and Demultiplexer
by Auto-multiplexer .


APPARATUS REQUIRED :-










THEORY :-

Multiplexers and Demultiplexers are some of the most useful logic devices
and they can be used for numerous purposes.

MULTIPLEXER can select any one of a number of inputs and route them to
a single output .

DEMULTIPLEXER has a single input and many outputs . The input of a
demultiplexer can be routed to any of the output channels . for this reason a demultiplexer
is also called as a Data Distributor .



S.No: NAME QUANTITY
1. IC 74153 1
2. IC 74139 1
3. Digital trainer kit 1
4. Connecting wires As required



MULTIPLEXER LOGICAL DIAGRAM:-



IC7408
IC7408
IC7408
IC7408
I
C
7
4
0
4
I
C
7
4
0
4
I
C
7
4
0
4
IC7432
S1
E1
So
Y
I o
I 1
I 2
I 3
PIN DIAGRAM:-





I
C
7
4
1
5
3
Ea
So
S1
I o
I 1
I 2
I 3
GND
Vcc
E1
Yo
Yo
I o
I 1
I 2
I 3
MULTIPLEXER
1
2
3
4
5
6
7
8
9
10
11
12
13
14
16
15
DEMULTIPLEXER LOGICAL DIAGRAM




PIN DIAGRAM:-




IC7408
IC7408
IC7408
IC7408
I
C
7
4
0
4
I
C
7
4
0
4
IC7432
I o
I 1
I 2
I 3
S1
So
Y
Ea
GND
Vcc
A1
Ao Eb
A1
Ao
I
C
7
4
1
3
9
0a
1a
3a
2a
0b
1b
2b
3b
DEMULTIPLEXER
1
2
3
4
5
6
7
8 9
10
11
12
13
14
15
16
Truth table for Multiplexer:-


S.No Enable S
1
S
0
D
3
D
2
D
1
D
0
Output
Y
1. 0 0 0 0 0 0 1 0
2. 1 0 0 0 0 0 1 1
3. 0 0 1 0 0 1 0 0
4. 1 0 1 0 0 1 0 1
5. 0 1 0 0 1 0 0 0
6. 1 1 0 0 1 0 0 1
7. 0 1 1 1 0 0 0 0
8. 1 1 1 1 0 0 0 1
















Truth table for Demultiplexer:-


S.No Enable S
1
S
0
Y
3
Y
2
Y
1
Y
0
1. 0 0 0 1 1 1 0
2. 1 0 0 1 1 1 1
3. 0 0 1 1 1 0 1
4. 1 0 1 1 1 1 1
5. 0 1 0 1 0 1 1
6. 1 1 0 1 1 1 1
7. 0 1 1 0 1 1 1
8. 1 1 1 1 1 1 1


PROCEDURE :

1. The connections are made as per the circuit diagram .

2. For different combinations , the outputs of multiplexer and
demultiplexer are noted .

3. The Truth Tables are verified .





RESULT :

Thus the truth tables of Multiplexer and Demultiplexer are verified .

Exp No : Date :



REALISATION OF FLIP FLOP USING LOGIC GATES
AIM:-
To realize the following clocked flip-flop using logic gates and to verify the
respective
characteristics tables.

- S R flip-flop
- D flip-flop.
APPARATUS REQUIRED:-

S.NO NAME OF THE APPARATUS RANGE QUANTITY
1 IC7400 (NAND) Two i/p 2
2 IC7404(NOT) Two i/p 1
3 DC power supply - 1
4 Trainer kit - 1
5 Bread board - 1

THEORY:

Flip-flop is the basic building block of combinational logic circuit. It has two
stable states and it is capable of storing single bit of data.

SR FLIPFLOP:

In the SR ff, if the input to S is high then FF will be in set condition. If it is
low the FF will reset. When both input were low the FF will remain in the previous
state. The main drawback of SR FF is if both input are high it will go to invalid state.









D FLIP FLOP:

The single input version of SR FF is Delay FF. To Overcome the
drawback in SR FF ,both inputs are coupled with a NOT gate . So when the input is
high , the FF is in set condition similarly when the input is low the FF will reset .
Hence the output of D FF follows the input.
PROCEDURE:-
Connections are given as per the circuit diagram.
The input are given to input module and output are obtained by LED.
A square or rectangular pulses with the frequency of order 20 to 60 MHZ is
fed from TTC of the function generator by using the pulse generator circuit
directly which acts as the clock pulse for the entire circuit.
With the initial value of present stable either with different J and K inputs
and input the next state or the revolution state of the flip-flop are determined
these values found to be in accordance to the respective characteristics.
























LOGIC CIRCUIT :
SR FLIPFLOP TRUTH TABLE


D FLIPFLOP TRUTH TABLE












RESULT:-
Thus the RS Flip Flop and D flip flop were constructed and
verified.

U1
U2
U3
U4
U1
U2
U3
U4
U
5
S.NO S R Q
1. 0 0 NC
2. 0 1 0
3. 1 0 1
4. 1 1 *
S.NO D Q
1. 0 0
2. 1 1


DIGITAL TO ANALOG CONVERTER

Aim:
To construct a four bit DAC using R-2R ladder type DAC with IC-741 and to test its
performance.



Apparatus Required:
Sl No: Name Of Apparatus Range Quantity
1 Op-Amp IC-741 1
2 Resistors 20K
10K
6
3
3 Push Button Switches 4
4 Dual Power Supply 15V 2
5 Bread Board 1
6 Connecting Wires As required


Theory:
A digital to analog converter is used to convert digital signal to analog signal. The output
of a DAC is usually a staircase waveform. Wide ranges of resistors are required for binary
weighted DAC. This can be avoided by using R-2R ladder type DAC, where only two values of
resistors are needed. The typical value of resistors range from 2.2K to 20K. The basic
principle of DAC is that the binary input is combined with the reference voltage V
M
to give an
analog output.

Applications:
1. It is used in communication systems such as FM and AM.
2. It is used in digital audio recording, digital signal processing, pulse code modulation,
transmission and in microprocessor based instrumentation.


Formula:

Output voltage V0 = -R
f
[b
3
2
-1
+ b
2
2
-2
+ b
1
2
-3
+ b
0
2
-4
]
R
i

Procedure:
1. Connections are given as per circuit diagram.
2. Binary inputs given to the resistor ladder network.
3. Output in analog form is noted down from the voltmeter.
4. For four bit DAC the 16-combinations are set as inputs and corresponding analog output
is taken.
5. The error voltage is calculated and graph is plotted between input and analog output.





Result:
Hence, the 4-bit digital to analog converter using R-2R ladder type cicuit with IC-741
was constructed and its performance was tested.

Error Voltage =