Pin Information for the Cyclone EP1C6 Device Version 1.

5
Bank Number B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 VREF Bank Pin Name/Function VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 IO IO IO IO IO IO IO IO VCCIO1 GND IO IO IO IO IO IO IO IO IO IO IO VCCIO1 IO IO DATA0 nCONFIG VCCA_PLL1 CLK0 CLK1 GNDA_PLL1 GNDG_PLL1 nCEO nCE MSEL0 MSEL1 DCLK Optional Function(s) LVDS14p LVDS14n LVDS13p LVDS13n VREF0B1 LVDS12p LVDS12n Configuration Function INIT_DONE CRC_ERROR CLKUSR T144 1 2 3 4 5 6 7 8 9 10 Q240 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 F256 D4 C3 C2 B1 G5 F4 D3 E4 DQS for x8 in the T144 DM1L DQ1L0 DQ1L1 DQS for x8 in the Q240 DQS for x8 in the F256

DQ1L2 DQ1L3

DQ0L0 DQ0L1

DQ0L0 DQ0L1

DPCLK1 LVDS11p LVDS11n LVDS10p LVDS10n LVDS9p LVDS9n LVDS8p LVDS8n LVDS7p LVDS7n VREF1B1 nCSO DATA0 nCONFIG LVDSCLK1p LVDSCLK1n

F5 E3 D2 E2 D1 F3 G3 F2 E1 G2 F1 H5 G4 H2 H3 H6 G1 H1 J6 J5 H4 J4 J3 J2 K4

DQS0L

DQS0L DQ0L2 DQ0L3

DQS0L DQ0L2 DQ0L3

DM0L

DM0L

B1 B1 B1 B1 B1

nCEO nCE MSEL0 MSEL1 DCLK

11 12 13 14 15 16 17 18 19 20 21 22 23 24

PT-EP1C6-1.5 Copyright 2006 Altera Corp. EP1C6 Pin List

Page 1 of 13

Pin Information for the Cyclone EP1C6 Device Version 1.5

Bank Number B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 VREF Bank Pin Name/Function VREF1B1 VREF1B1 VREF1B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 IO IO IO GND IO IO IO IO IO IO IO IO IO IO VCCIO1 GND IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO GND VCCIO4 GND VCCINT Optional Function(s) PLL1_OUTp PLL1_OUTn Configuration Function ASDO T144 25 26 27 Q240 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 F256 K3 J1 K2 L3 K1 L1 L2 M1 N1 M2 N2 M3 L5 DQS for x8 in the T144 DQS for x8 in the Q240 DQS for x8 in the F256

LVDS6p LVDS6n LVDS5p LVDS5n LVDS4p LVDS4n LVDS3p LVDS3n DPCLK0

28 29 30

DQS1L

DQ0L4 DQ0L5 DQS1L

DQ0L4 DQ0L5 DQS1L

LVDS2p LVDS2n VREF2B1 LVDS1p LVDS1n LVDS0p LVDS0n LVDS71p LVDS71n LVDS70p LVDS70n LVDS69p LVDS69n LVDS68p LVDS68n

31 32 33 34 35 36 37 38

39 40 41 42 43 44 45 46

M4 N3 K5 L4 R1 P2 P3 N4 R2 T2 R3 P4 R4 T4 R5 P5

DQ0L6 DQ0L7 DQ1L4 DQ1L5 DQ1L6 DQ1L7

DQ0L6 DQ0L7

DQ1B7 DQ1B6 DQ1B5 DQ1B4

DQ1B7 DQ1B6

DQ1B7 DQ1B6

PT-EP1C6-1.5 Copyright 2006 Altera Corp. EP1C6 Pin List

Page 2 of 13

Pin Information for the Cyclone EP1C6 Device Version 1.5

Bank Number B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 VREF Bank Pin Name/Function VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO GND VCCINT GND VCCIO4 IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO Optional Function(s) DPCLK7 VREF2B4 LVDS67p LVDS67n LVDS66p LVDS66n LVDS65p LVDS65n LVDS64p LVDS64n LVDS63p LVDS63n LVDS62p LVDS62n Configuration Function T144 47 48 49 Q240 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 F256 M5 M6 N5 N6 P6 R6 M7 T6 R7 P7 N7 R8 T8 N8 P8 M8 DQS for x8 in the T144 DQS1B DQS for x8 in the Q240 DQS1B DQS for x8 in the F256 DQS1B

DQ1B5 DQ1B4

DQ1B5 DQ1B4

50 51 52 53 54 55

B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4

VREF1B4 LVDS61p LVDS61n LVDS60p LVDS60n LVDS59p LVDS59n LVDS58p LVDS58n LVDS57p LVDS57n LVDS56p LVDS56n VREF0B4 DPCLK6

56 57 58

59

60 61 62

M10 R9 T9 P9 N9 R10 T11 N10 P10 R11 P11 N11 N12 M9 M11 M12

DM1B

DM1B

DM1B

DQS0B

DQS0B

DQS0B

PT-EP1C6-1.5 Copyright 2006 Altera Corp. EP1C6 Pin List

Page 3 of 13

Pin Information for the Cyclone EP1C6 Device Version 1.5

Bank Number VREF Bank Pin Name/Function VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF1B3 VREF1B3 GND VCCINT GND VCCIO4 IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO GND VCCIO3 IO IO IO IO IO IO IO IO IO IO IO GND IO IO Optional Function(s) Configuration Function T144 63 64 65 66 67 68 69 70 Q240 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 F256 DQS for x8 in the T144 DQS for x8 in the Q240 DQS for x8 in the F256

B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3

LVDS55p LVDS55n LVDS54p LVDS54n LVDS53p LVDS53n LVDS52p LVDS52n LVDS51n LVDS51p LVDS50n LVDS50p LVDS49n LVDS49p VREF2B3

71 72 73 74 75 76 77 78 79 80 81 82 83 84 85

P12 R12 T13 R13 R14 P13 T15 R15 N13 P14 P15 R16 N15 N16 K12 K14

DQ1B3 DQ1B2 DQ1B1 DQ1B0

DQ1B3 DQ1B2 DQ1B1 DQ1B0

DQ1B3 DQ1B2 DQ1B1 DQ1B0

DQ1R7 DQ1R6

DQ1R7

DQ1R7

DQ1R6

DQ1R6

DPCLK5 LVDS48n LVDS48p LVDS47n LVDS47p LVDS46n LVDS46p LVDS45n LVDS45p LVDS44n LVDS44p PLL2_OUTn PLL2_OUTp

L12 N14 M13 M14 L13 M15 M16 L14 L15 L16 K16 K15 J16

DQS1R DQ1R5 DQ1R4 DM1R

DQS1R DQ1R5 DQ1R4

DQS1R DQ1R5 DQ1R4

PT-EP1C6-1.5 Copyright 2006 Altera Corp. EP1C6 Pin List

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Pin Information for the Cyclone EP1C6 Device Version 1.5

Bank Number B3 B3 B3 B3 B3 VREF Bank Pin Name/Function VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 CONF_DONE nSTATUS TCK TMS TDO GNDG_PLL2 GNDA_PLL2 CLK3 CLK2 VCCA_PLL2 TDI IO VCCIO3 IO IO IO IO IO IO IO IO IO IO IO IO IO GND VCCIO3 IO IO IO IO IO IO IO IO Optional Function(s) Configuration Function CONF_DONE nSTATUS TCK TMS TDO T144 86 87 88 89 90 91 92 93 94 95 96 Q240 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 F256 K13 J13 J14 J15 H15 J12 J11 H16 G16 H11 H14 H12 G14 G13 G15 F16 F14 F13 F15 E16 E15 D16 D15 E14 F12 DM1R DM1R DQS for x8 in the T144 DQS for x8 in the Q240 DQS for x8 in the F256

B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3

LVDSCLK2n LVDSCLK2p TDI VREF1B3 LVDS43n LVDS43p LVDS42n LVDS42p LVDS41n LVDS41p LVDS40n LVDS40p LVDS39n LVDS39p LVDS38n LVDS38p DPCLK4

97 98 99 100 101 102

DQ1R3 DQ1R2 DQ1R1 DQS0R

DQ1R3 DQS0R

DQ1R3 DQS0R

LVDS37n LVDS37p VREF0B3 LVDS36n LVDS36p LVDS35n LVDS35p 103 104 105 106 107 108

E13 D14 H13 G12 B16 C15 C14 D13

DQ1R0

DQ1R2 DQ1R1 DQ1R0

DQ1R2 DQ1R1 DQ1R0

PT-EP1C6-1.5 Copyright 2006 Altera Corp. EP1C6 Pin List

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Pin Information for the Cyclone EP1C6 Device Version 1.5

Bank Number B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 VREF Bank Pin Name/Function VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF2B2 IO IO IO IO IO IO IO IO VCCIO2 GND VCCINT GND IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO VCCIO2 GND VCCINT GND IO IO IO IO Optional Function(s) LVDS34n LVDS34p LVDS33n LVDS33p LVDS32n LVDS32p LVDS31n LVDS31p Configuration Function T144 109 110 Q240 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 F256 B15 A15 B14 C13 B13 A13 B12 C12 DQS for x8 in the T144 DQS for x8 in the Q240 DQS for x8 in the F256

B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2

DPCLK3 VREF0B2 LVDS30n LVDS30p LVDS29n LVDS29p LVDS28n LVDS28p LVDS27n LVDS27p LVDS26n LVDS26p LVDS25n LVDS25p VREF1B2

111 112 113 114 115 116 117 118 119 120 121

DQ0T0 DQ0T1 DQ0T2 DQ0T3

DQ0T0 DQ0T1 DQ0T2 DQ0T3

DQ0T0 DQ0T1 DQ0T2 DQ0T3

122

123 124 125

E12 E11 E9 D12 D11 C11 B11 A11 B10 C10 D10 A9 B9 D9 C9 E10

DQS0T

DQS0T

DQS0T

DM0T

DM0T

DM0T

126 127 LVDS24n LVDS24p LVDS23n 128 129 130

B2 B2 B2 B2

E8 C8 D8 A8

PT-EP1C6-1.5 Copyright 2006 Altera Corp. EP1C6 Pin List

Page 6 of 13

Pin Information for the Cyclone EP1C6 Device Version 1.5

Bank Number B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 VREF Bank Pin Name/Function VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 IO IO IO IO IO IO IO IO IO IO IO IO VCCINT GND VCCIO2 GND IO IO IO IO IO IO IO IO VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT Optional Function(s) LVDS23p LVDS22n LVDS22p LVDS21n LVDS21p LVDS20n LVDS20p LVDS19n LVDS19p VREF2B2 DPCLK2 Configuration Function T144 131 Q240 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 F256 B8 D7 C7 B7 A6 E7 B6 C6 D6 D5 E6 E5 DQS for x8 in the T144 DQS for x8 in the Q240 DQS for x8 in the F256

B2 B2 B2 B2 B2 B2 B2 B2 B2 B2

LVDS18n LVDS18p LVDS17n LVDS17p LVDS16n LVDS16p LVDS15n LVDS15p

132 133 134 135 136 137 138 139 140 141 142

DQS1T

DQS1T

DQS1T

DEV_OE DEV_CLRn

143 144

C5 B5 A4 B4 C4 B3 A2 B2 A7 A10 G8 G10 H7 H9 J8 J10 K7 K9 T7 T10

DQ0T4 DQ0T5 DQ0T6 DQ0T7

DQ0T4 DQ0T5 DQ0T6 DQ0T7

DQ0T4 DQ0T5 DQ0T6 DQ0T7

PT-EP1C6-1.5 Copyright 2006 Altera Corp. EP1C6 Pin List

Page 7 of 13

Pin Information for the Cyclone EP1C6 Device Version 1.5

Bank Number VREF Bank Pin Name/Function VCCIO1 VCCIO1 VCCIO1 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO3 VCCIO3 VCCIO3 VCCIO2 VCCIO2 VCCIO2 VCCIO2 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Optional Function(s) Configuration Function T144 Q240 F256 C1 G6 P1 T3 L7 L10 T14 P16 K11 C16 A14 F10 F7 A3 A1 A16 A5 A12 F6 F8 F9 F11 G7 G9 G11 H8 H10 J7 J9 K6 K8 K10 L6 L8 L9 L11 DQS for x8 in the T144 DQS for x8 in the Q240 DQS for x8 in the F256

PT-EP1C6-1.5 Copyright 2006 Altera Corp. EP1C6 Pin List

Page 8 of 13

Pin Information for the Cyclone EP1C6 Device Version 1.5

Bank Number VREF Bank Pin Name/Function GND GND GND GND Optional Function(s) Configuration Function T144 Q240 F256 T1 T5 T12 T16 DQS for x8 in the T144 DQS for x8 in the Q240 DQS for x8 in the F256

PT-EP1C6-1.5 Copyright 2006 Altera Corp. EP1C6 Pin List

Page 9 of 13

Pin Information for the Cyclone EP1C6 Device Version 1.5

Pin Name Pin Type (1st, 2nd, & 3rd Function) Pin Description Supply and Reference Pins These are I/O supply voltage pins for banks 1 through 4. Each bank can support a different voltage level. VCCIO supplies power to the output buffers for all I/O standards. VCCIO also supplies power to the input buffers used for the LVTTL, LVCMOS, 1.5-V, 1.8-V, 2.5-V, and 3.3-V PCI I/O standards. These are internal logic array voltage supply pins. VCCINT also supplies power to the input buffers used for the LVDS, SSTL2, and SSTL3 I/O standards. Device ground pins. All GND pins should be connected to the board GND plane. Input reference voltage for banks 1-4. If a bank uses a voltage-referenced I/O standard, then these pins are used as the voltage-reference pins for the bank. If voltage reference I/O standards are not used in the bank, the VREF pins are available as user I/O pins. Analog power for PLLs[1..2]. The designer must connect this pin to 1.5 V, even if the PLL is not used. Analog ground for PLLs[1..2]. The designer can connect this pin to the GND plane on the board. Guard ring ground for PLLs[1..2]. The designer can connect this pin to the GND plane on the board. No connect pins should not be connected on the board. They should be left floating. Configuration and JTAG Pins

VCCIO[1..4] VCCINT GND

Power Power Ground

VREF[0..2]B[1..4] VCCA_PLL[1..2] GNDA_PLL[1..2] GNDG_PLL[1..2] NC

I/O, Input Power Ground Ground No Connect

CONF_DONE nSTATUS nCONFIG

Bidirectional (open-drain) This is a dedicated configuration status pin; it is not available as a user I/O pin. Bidirectional (open-drain) This is a dedicated configuration status pin; it is not available as a user I/O pin. Dedicated configuration control input. A low transition resets the target device; a low-to-high transition begins configuration. All I/O pins tri-state when nCONFIG is driven low. Input In passive serial configuration mode, DCLK is a clock input used to clock configuration data from an external source into the Cyclone device. In active serial configuration mode, DCLK is a clock output Input (PS mode), Output from the Cyclone device (the Cyclone device acts as master in this mode). This is a dedicated pin used for configuration. (AS mode) Dedicated configuration data input pin. Input Active-low chip enable. Dedicated chip enable input used to detect which device is active in a chain of devices. When nCE is low, the device is enabled. When nCE is high, the device is disabled. Output that drives low when device configuration is complete. During multi-device configuration, this pin feeds a subsequent devices nCE pin. Active serial data output from the Cyclone device. This output pin is utilized during active serial configuration mode. The Cyclone device controls configuration and drives address and control information out on ASDO. In passive serial configuration, this pin is available as a user I/O pin. Chip select output that enables/disables a serial configuration device. This output is utilized during active serial configuration mode. The Cyclone device controls configuration and enables the serial configuration device by driving nCSO low. In passive serial configuration, this pin is available as a user I/O pin.

DCLK DATA0

nCE nCEO

Input Output

ASDO

I/O, Output

nCSO

I/O, Output

CRC_ERROR

I/O, Output

INIT_DONE CLKUSR

Active high signal that indicates that the error detection circuit has detected errors in the configuration SRAM bits. This pin is optional and is used when the CRC error detection circuit is enabled. This is a dual-purpose pin and can be used as an I/O pin when not enabled as INIT_DONE. When enabled, the pin indicates when the device has entered user mode. This pin can be used as a user I/O I/O, Output (open-drain) pin after configuration. Optional user-supplied clock input. Synchronizes the initialization of one or more devices. This pin can be used as a user I/O pin after configuration. I/O, Input Dual-purpose pin that can override all clears on all device registers. When this pin is driven low, all registers are cleared; when this pin is driven high, all registers behave as defined in the design. Dual-purpose pin that can override all tri-states on the device. When this pin is driven low, all I/O pins are tri-stated; when this pin is driven high, all I/O pins behave as defined in the design. Dedicated mode select control pins that set the configuration mode for the device. This is a dedicated JTAG input pin. This is a dedicated JTAG input pin. This is a dedicated JTAG input pin. This is a dedicated JTAG output pin. Clock and PLL Pins Dedicated global clock input. The dual-function of CLK0 is LVDSCLK1p, which is used for differential input to PLL1. Dedicated global clock input. The dual-function of CLK1 is LVDSCLK1n, which is used for differential input to PLL1. Dedicated global clock input. The dual-function of CLK2 is LVDSCLK2p, which is used for differential input to PLL2. Dedicated global clock input. The dual-function of CLK3 is LVDSCLK2n, which is used for differential input to PLL2. Dual-purpose clock pins that can connect to the global clock network. These pins can be used for high fan-out control signals, such as clocks, clears, IRDY, TRDY, or DQS signals. These pins are also available as user I/O pins. External clock output from PLL 1. This pin can be used with differential or single ended I/O standards. If clock output from PLL1 is not used, this pin is available as a user I/O pin. Negative terminal for external clock output from PLL1. If the clock output is single ended, this pin is available as a user I/O pin.

DEV_CLRn

I/O, Input

DEV_OE MSEL[1..0] TMS TDI TCK TDO

I/O, Input Input Input Input Input Output

CLK0 CLK1 CLK2 CLK3

Input, LVDS Input Input, LVDS Input Input, LVDS Input Input, LVDS Input

DPCLK[7..0] PLL1_OUTp PLL1_OUTn

I/O I/O, Output I/O, Output

PT-EP1C6-1.5 Copyright 2006 Altera Corp. Pin Definitions

Page 10 of 13

Pin Information for the Cyclone EP1C6 Device Version 1.5

Pin Name Pin Type (1st, 2nd, & 3rd Function) Pin Description External clock output from PLL 2. This pin can be used with differential or single ended I/O standards. If clock output from PLL2 is not used, this pin is available as a user I/O pin. The EP1C6T144 does not support this output pin. Negative terminal for external clock output from PLL2. If the clock output is single ended, this pin is available as a user I/O pin. The EP1C6T144 does not support this output pin. Dual-Purpose LVDS & External Memory Interface Pins Dual-purpose LVDS I/O channels 0 to 71. These channels can be used for receiving or transmitting LVDS compatible signals. Pins with a "p" suffix carry the positive signal for the differential channel. If not used for LVDS interfacing, these pins are available as user I/O pins. Both the positive pin and negative pin needs to be bonded out in order to use the LVDS channel. Dual-purpose LVDS I/O channels 0 to 71. These channels can be used for receiving or transmitting LVDS compatible signals. Pins with an "n" suffix carry the negative signal for the differential channel. If not used for LVDS interfacing, these pins are available as user I/O pins. Both the positive pin and negative pin needs to be bonded out in order to use the LVDS channel.

PLL2_OUTp PLL2_OUTn

I/O, Output I/O, Output

LVDS[0..71]p

I/O, LVDS RX or TX

LVDS[0..71]n

I/O, LVDS RX or TX Input, LVDS Input Input, LVDS Input Input, LVDS Input Input, LVDS Input

LVDSCLK1p LVDSCLK1n LVDSCLK2p LVDSCLK2n

Dual-purpose LVDS clock input to PLL1. is available as the CLK0 input pin. Dual-purpose LVDS clock input to PLL1. is available as the CLK1 input pin. Dual-purpose LVDS clock input to PLL2. is available as the CLK2 input pin. Dual-purpose LVDS clock input to PLL2. is available as the CLK3 input pin.

If differential input to PLL1 is not required, this pin If differential input to PLL1 is not required, this pin If differential input to PLL2 is not required, this pin If differential input to PLL2 is not required, this pin

DQS[0..1][L,R,T,B] DQ[0..7][L,R,T,B] DM[0..1][L,R,T,B]

I/O I/O I/O

Optional data strobe signal for use in external memory interfacing. These pins also function as DPCLK pins; therefore, the DQS signals can connect to the global clock network. A programmable delay chain is used to shift the DQS signals by 90 or 72 degrees. Optional data signal for use in external memory interfacing. Optional data mask output signal for use in external memory interfacing.

PT-EP1C6-1.5 Copyright 2006 Altera Corp. Pin Definitions

Page 11 of 13

Pin Information for the Cyclone EP1C6 Device, ver 1.5

VREF2B2

VREF1B2

VREF0B2

B2
VREF0B1 VREF0B3

VREF1B1

PLL1

PLL2

VREB2B1

B4
VREF2B4 VREF1B4 VREF0B4 Notes: 1.This is a top view of the silicon die. 2.This is a pictoral representation only to get an idea of placement on the device. Refer to the pin-list and the Quartus II for exact locations.

PT-EP1C6-1.5 Copyright 2006 Altera Corp. Bank & PLL Diagram

VREB2B3

VREF1B3

B1

B3

Page 12 of 13

Pin Information for the Cyclone EP1C6 Device Version 1.5

Version Number 1.5 Date 3/6/2006 Changes Made Added CRC_ERROR pin in Pin List and Pin Definitions

PT-EP1C6-1.5 Copyright 2006 Altera Corp. Revision History

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